Commit | Line | Data |
---|---|---|
bb3cee2b LW |
1 | /* |
2 | * | |
3 | * arch/arm/mach-u300/core.c | |
4 | * | |
5 | * | |
ec8f1253 | 6 | * Copyright (C) 2007-2010 ST-Ericsson SA |
bb3cee2b LW |
7 | * License terms: GNU General Public License (GPL) version 2 |
8 | * Core platform support, IRQ handling and device definitions. | |
9 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/mm.h> | |
18 | #include <linux/termios.h> | |
ec8f1253 | 19 | #include <linux/dmaengine.h> |
bb3cee2b | 20 | #include <linux/amba/bus.h> |
ec8f1253 | 21 | #include <linux/amba/serial.h> |
bb3cee2b LW |
22 | #include <linux/platform_device.h> |
23 | #include <linux/gpio.h> | |
b7276b23 LW |
24 | #include <linux/clk.h> |
25 | #include <linux/err.h> | |
93ac5a55 LW |
26 | #include <linux/mtd/nand.h> |
27 | #include <linux/mtd/fsmc.h> | |
98da3529 | 28 | #include <linux/pinctrl/machine.h> |
28a8d14c | 29 | #include <linux/pinctrl/consumer.h> |
d70a5969 | 30 | #include <linux/dma-mapping.h> |
bb3cee2b LW |
31 | |
32 | #include <asm/types.h> | |
33 | #include <asm/setup.h> | |
34 | #include <asm/memory.h> | |
35 | #include <asm/hardware/vic.h> | |
36 | #include <asm/mach/map.h> | |
37 | #include <asm/mach/irq.h> | |
38 | ||
93ac5a55 | 39 | #include <mach/coh901318.h> |
bb3cee2b LW |
40 | #include <mach/hardware.h> |
41 | #include <mach/syscon.h> | |
08d1e2e6 | 42 | #include <mach/dma_channels.h> |
cc890cd7 | 43 | #include <mach/gpio-u300.h> |
bb3cee2b LW |
44 | |
45 | #include "clock.h" | |
46 | #include "mmc.h" | |
c7c8c78f | 47 | #include "spi.h" |
6be2a0ca | 48 | #include "i2c.h" |
bb3cee2b LW |
49 | |
50 | /* | |
51 | * Static I/O mappings that are needed for booting the U300 platforms. The | |
52 | * only things we need are the areas where we find the timer, syscon and | |
53 | * intcon, since the remaining device drivers will map their own memory | |
54 | * physical to virtual as the need arise. | |
55 | */ | |
56 | static struct map_desc u300_io_desc[] __initdata = { | |
57 | { | |
58 | .virtual = U300_SLOW_PER_VIRT_BASE, | |
59 | .pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE), | |
60 | .length = SZ_64K, | |
61 | .type = MT_DEVICE, | |
62 | }, | |
63 | { | |
64 | .virtual = U300_AHB_PER_VIRT_BASE, | |
65 | .pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE), | |
66 | .length = SZ_32K, | |
67 | .type = MT_DEVICE, | |
68 | }, | |
69 | { | |
70 | .virtual = U300_FAST_PER_VIRT_BASE, | |
71 | .pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE), | |
72 | .length = SZ_32K, | |
73 | .type = MT_DEVICE, | |
74 | }, | |
bb3cee2b LW |
75 | }; |
76 | ||
77 | void __init u300_map_io(void) | |
78 | { | |
79 | iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc)); | |
d70a5969 JM |
80 | /* We enable a real big DMA buffer if need be. */ |
81 | init_consistent_dma_size(SZ_4M); | |
bb3cee2b LW |
82 | } |
83 | ||
84 | /* | |
85 | * Declaration of devices found on the U300 board and | |
86 | * their respective memory locations. | |
87 | */ | |
ec8f1253 LW |
88 | |
89 | static struct amba_pl011_data uart0_plat_data = { | |
90 | #ifdef CONFIG_COH901318 | |
91 | .dma_filter = coh901318_filter_id, | |
92 | .dma_rx_param = (void *) U300_DMA_UART0_RX, | |
93 | .dma_tx_param = (void *) U300_DMA_UART0_TX, | |
94 | #endif | |
95 | }; | |
96 | ||
bb3cee2b LW |
97 | static struct amba_device uart0_device = { |
98 | .dev = { | |
ec8f1253 | 99 | .coherent_dma_mask = ~0, |
bb3cee2b | 100 | .init_name = "uart0", /* Slow device at 0x3000 offset */ |
ec8f1253 | 101 | .platform_data = &uart0_plat_data, |
bb3cee2b LW |
102 | }, |
103 | .res = { | |
104 | .start = U300_UART0_BASE, | |
105 | .end = U300_UART0_BASE + SZ_4K - 1, | |
106 | .flags = IORESOURCE_MEM, | |
107 | }, | |
108 | .irq = { IRQ_U300_UART0, NO_IRQ }, | |
109 | }; | |
110 | ||
111 | /* The U335 have an additional UART1 on the APP CPU */ | |
112 | #ifdef CONFIG_MACH_U300_BS335 | |
ec8f1253 LW |
113 | static struct amba_pl011_data uart1_plat_data = { |
114 | #ifdef CONFIG_COH901318 | |
115 | .dma_filter = coh901318_filter_id, | |
116 | .dma_rx_param = (void *) U300_DMA_UART1_RX, | |
117 | .dma_tx_param = (void *) U300_DMA_UART1_TX, | |
118 | #endif | |
119 | }; | |
120 | ||
bb3cee2b LW |
121 | static struct amba_device uart1_device = { |
122 | .dev = { | |
ec8f1253 | 123 | .coherent_dma_mask = ~0, |
bb3cee2b | 124 | .init_name = "uart1", /* Fast device at 0x7000 offset */ |
ec8f1253 | 125 | .platform_data = &uart1_plat_data, |
bb3cee2b LW |
126 | }, |
127 | .res = { | |
128 | .start = U300_UART1_BASE, | |
129 | .end = U300_UART1_BASE + SZ_4K - 1, | |
130 | .flags = IORESOURCE_MEM, | |
131 | }, | |
132 | .irq = { IRQ_U300_UART1, NO_IRQ }, | |
133 | }; | |
134 | #endif | |
135 | ||
136 | static struct amba_device pl172_device = { | |
137 | .dev = { | |
138 | .init_name = "pl172", /* AHB device at 0x4000 offset */ | |
139 | .platform_data = NULL, | |
140 | }, | |
141 | .res = { | |
142 | .start = U300_EMIF_CFG_BASE, | |
143 | .end = U300_EMIF_CFG_BASE + SZ_4K - 1, | |
144 | .flags = IORESOURCE_MEM, | |
145 | }, | |
146 | }; | |
147 | ||
148 | ||
149 | /* | |
150 | * Everything within this next ifdef deals with external devices connected to | |
151 | * the APP SPI bus. | |
152 | */ | |
153 | static struct amba_device pl022_device = { | |
154 | .dev = { | |
155 | .coherent_dma_mask = ~0, | |
156 | .init_name = "pl022", /* Fast device at 0x6000 offset */ | |
157 | }, | |
158 | .res = { | |
159 | .start = U300_SPI_BASE, | |
160 | .end = U300_SPI_BASE + SZ_4K - 1, | |
161 | .flags = IORESOURCE_MEM, | |
162 | }, | |
163 | .irq = {IRQ_U300_SPI, NO_IRQ }, | |
164 | /* | |
165 | * This device has a DMA channel but the Linux driver does not use | |
166 | * it currently. | |
167 | */ | |
168 | }; | |
169 | ||
170 | static struct amba_device mmcsd_device = { | |
171 | .dev = { | |
172 | .init_name = "mmci", /* Fast device at 0x1000 offset */ | |
173 | .platform_data = NULL, /* Added later */ | |
174 | }, | |
175 | .res = { | |
176 | .start = U300_MMCSD_BASE, | |
177 | .end = U300_MMCSD_BASE + SZ_4K - 1, | |
178 | .flags = IORESOURCE_MEM, | |
179 | }, | |
180 | .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }, | |
181 | /* | |
182 | * This device has a DMA channel but the Linux driver does not use | |
183 | * it currently. | |
184 | */ | |
185 | }; | |
186 | ||
187 | /* | |
188 | * The order of device declaration may be important, since some devices | |
189 | * have dependencies on other devices being initialized first. | |
190 | */ | |
191 | static struct amba_device *amba_devs[] __initdata = { | |
192 | &uart0_device, | |
193 | #ifdef CONFIG_MACH_U300_BS335 | |
194 | &uart1_device, | |
195 | #endif | |
196 | &pl022_device, | |
197 | &pl172_device, | |
198 | &mmcsd_device, | |
199 | }; | |
200 | ||
201 | /* Here follows a list of all hw resources that the platform devices | |
202 | * allocate. Note, clock dependencies are not included | |
203 | */ | |
204 | ||
205 | static struct resource gpio_resources[] = { | |
206 | { | |
207 | .start = U300_GPIO_BASE, | |
208 | .end = (U300_GPIO_BASE + SZ_4K - 1), | |
209 | .flags = IORESOURCE_MEM, | |
210 | }, | |
211 | { | |
212 | .name = "gpio0", | |
213 | .start = IRQ_U300_GPIO_PORT0, | |
214 | .end = IRQ_U300_GPIO_PORT0, | |
215 | .flags = IORESOURCE_IRQ, | |
216 | }, | |
217 | { | |
218 | .name = "gpio1", | |
219 | .start = IRQ_U300_GPIO_PORT1, | |
220 | .end = IRQ_U300_GPIO_PORT1, | |
221 | .flags = IORESOURCE_IRQ, | |
222 | }, | |
223 | { | |
224 | .name = "gpio2", | |
225 | .start = IRQ_U300_GPIO_PORT2, | |
226 | .end = IRQ_U300_GPIO_PORT2, | |
227 | .flags = IORESOURCE_IRQ, | |
228 | }, | |
cc890cd7 | 229 | #if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335) |
bb3cee2b LW |
230 | { |
231 | .name = "gpio3", | |
232 | .start = IRQ_U300_GPIO_PORT3, | |
233 | .end = IRQ_U300_GPIO_PORT3, | |
234 | .flags = IORESOURCE_IRQ, | |
235 | }, | |
236 | { | |
237 | .name = "gpio4", | |
238 | .start = IRQ_U300_GPIO_PORT4, | |
239 | .end = IRQ_U300_GPIO_PORT4, | |
240 | .flags = IORESOURCE_IRQ, | |
241 | }, | |
cc890cd7 | 242 | #endif |
bb3cee2b LW |
243 | #ifdef CONFIG_MACH_U300_BS335 |
244 | { | |
245 | .name = "gpio5", | |
246 | .start = IRQ_U300_GPIO_PORT5, | |
247 | .end = IRQ_U300_GPIO_PORT5, | |
248 | .flags = IORESOURCE_IRQ, | |
249 | }, | |
250 | { | |
251 | .name = "gpio6", | |
252 | .start = IRQ_U300_GPIO_PORT6, | |
253 | .end = IRQ_U300_GPIO_PORT6, | |
254 | .flags = IORESOURCE_IRQ, | |
255 | }, | |
256 | #endif /* CONFIG_MACH_U300_BS335 */ | |
bb3cee2b LW |
257 | }; |
258 | ||
259 | static struct resource keypad_resources[] = { | |
260 | { | |
261 | .start = U300_KEYPAD_BASE, | |
262 | .end = U300_KEYPAD_BASE + SZ_4K - 1, | |
263 | .flags = IORESOURCE_MEM, | |
264 | }, | |
265 | { | |
266 | .name = "coh901461-press", | |
267 | .start = IRQ_U300_KEYPAD_KEYBF, | |
268 | .end = IRQ_U300_KEYPAD_KEYBF, | |
269 | .flags = IORESOURCE_IRQ, | |
270 | }, | |
271 | { | |
272 | .name = "coh901461-release", | |
273 | .start = IRQ_U300_KEYPAD_KEYBR, | |
274 | .end = IRQ_U300_KEYPAD_KEYBR, | |
275 | .flags = IORESOURCE_IRQ, | |
276 | }, | |
277 | }; | |
278 | ||
279 | static struct resource rtc_resources[] = { | |
280 | { | |
281 | .start = U300_RTC_BASE, | |
282 | .end = U300_RTC_BASE + SZ_4K - 1, | |
283 | .flags = IORESOURCE_MEM, | |
284 | }, | |
285 | { | |
286 | .start = IRQ_U300_RTC, | |
287 | .end = IRQ_U300_RTC, | |
288 | .flags = IORESOURCE_IRQ, | |
289 | }, | |
290 | }; | |
291 | ||
292 | /* | |
293 | * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2) | |
294 | * but these are not yet used by the driver. | |
295 | */ | |
296 | static struct resource fsmc_resources[] = { | |
297 | { | |
93ac5a55 LW |
298 | .name = "nand_data", |
299 | .start = U300_NAND_CS0_PHYS_BASE, | |
300 | .end = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1, | |
301 | .flags = IORESOURCE_MEM, | |
302 | }, | |
303 | { | |
304 | .name = "fsmc_regs", | |
bb3cee2b LW |
305 | .start = U300_NAND_IF_PHYS_BASE, |
306 | .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1, | |
307 | .flags = IORESOURCE_MEM, | |
308 | }, | |
309 | }; | |
310 | ||
311 | static struct resource i2c0_resources[] = { | |
312 | { | |
313 | .start = U300_I2C0_BASE, | |
314 | .end = U300_I2C0_BASE + SZ_4K - 1, | |
315 | .flags = IORESOURCE_MEM, | |
316 | }, | |
317 | { | |
318 | .start = IRQ_U300_I2C0, | |
319 | .end = IRQ_U300_I2C0, | |
320 | .flags = IORESOURCE_IRQ, | |
321 | }, | |
322 | }; | |
323 | ||
324 | static struct resource i2c1_resources[] = { | |
325 | { | |
326 | .start = U300_I2C1_BASE, | |
327 | .end = U300_I2C1_BASE + SZ_4K - 1, | |
328 | .flags = IORESOURCE_MEM, | |
329 | }, | |
330 | { | |
331 | .start = IRQ_U300_I2C1, | |
332 | .end = IRQ_U300_I2C1, | |
333 | .flags = IORESOURCE_IRQ, | |
334 | }, | |
335 | ||
336 | }; | |
337 | ||
338 | static struct resource wdog_resources[] = { | |
339 | { | |
340 | .start = U300_WDOG_BASE, | |
341 | .end = U300_WDOG_BASE + SZ_4K - 1, | |
342 | .flags = IORESOURCE_MEM, | |
343 | }, | |
344 | { | |
345 | .start = IRQ_U300_WDOG, | |
346 | .end = IRQ_U300_WDOG, | |
347 | .flags = IORESOURCE_IRQ, | |
348 | } | |
349 | }; | |
350 | ||
08d1e2e6 LW |
351 | static struct resource dma_resource[] = { |
352 | { | |
353 | .start = U300_DMAC_BASE, | |
354 | .end = U300_DMAC_BASE + PAGE_SIZE - 1, | |
355 | .flags = IORESOURCE_MEM, | |
356 | }, | |
357 | { | |
358 | .start = IRQ_U300_DMA, | |
359 | .end = IRQ_U300_DMA, | |
360 | .flags = IORESOURCE_IRQ, | |
361 | } | |
362 | }; | |
363 | ||
364 | #ifdef CONFIG_MACH_U300_BS335 | |
365 | /* points out all dma slave channels. | |
366 | * Syntax is [A1, B1, A2, B2, .... ,-1,-1] | |
367 | * Select all channels from A to B, end of list is marked with -1,-1 | |
368 | */ | |
369 | static int dma_slave_channels[] = { | |
370 | U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, | |
371 | U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1}; | |
372 | ||
373 | /* points out all dma memcpy channels. */ | |
374 | static int dma_memcpy_channels[] = { | |
375 | U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1}; | |
376 | ||
377 | #else /* CONFIG_MACH_U300_BS335 */ | |
378 | ||
379 | static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1}; | |
380 | static int dma_memcpy_channels[] = { | |
381 | U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1}; | |
382 | ||
383 | #endif | |
384 | ||
385 | /** register dma for memory access | |
386 | * | |
387 | * active 1 means dma intends to access memory | |
388 | * 0 means dma wont access memory | |
389 | */ | |
390 | static void coh901318_access_memory_state(struct device *dev, bool active) | |
391 | { | |
392 | } | |
393 | ||
394 | #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \ | |
395 | COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \ | |
396 | COH901318_CX_CFG_LCR_DISABLE | \ | |
397 | COH901318_CX_CFG_TC_IRQ_ENABLE | \ | |
398 | COH901318_CX_CFG_BE_IRQ_ENABLE) | |
399 | #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \ | |
400 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ | |
401 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ | |
402 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ | |
403 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ | |
404 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ | |
405 | COH901318_CX_CTRL_MASTER_MODE_M1RW | \ | |
406 | COH901318_CX_CTRL_TCP_DISABLE | \ | |
407 | COH901318_CX_CTRL_TC_IRQ_DISABLE | \ | |
408 | COH901318_CX_CTRL_HSP_DISABLE | \ | |
409 | COH901318_CX_CTRL_HSS_DISABLE | \ | |
410 | COH901318_CX_CTRL_DDMA_LEGACY | \ | |
411 | COH901318_CX_CTRL_PRDD_SOURCE) | |
412 | #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \ | |
413 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ | |
414 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ | |
415 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ | |
416 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ | |
417 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ | |
418 | COH901318_CX_CTRL_MASTER_MODE_M1RW | \ | |
419 | COH901318_CX_CTRL_TCP_DISABLE | \ | |
420 | COH901318_CX_CTRL_TC_IRQ_DISABLE | \ | |
421 | COH901318_CX_CTRL_HSP_DISABLE | \ | |
422 | COH901318_CX_CTRL_HSS_DISABLE | \ | |
423 | COH901318_CX_CTRL_DDMA_LEGACY | \ | |
424 | COH901318_CX_CTRL_PRDD_SOURCE) | |
425 | #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \ | |
426 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ | |
427 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ | |
428 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ | |
429 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ | |
430 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ | |
431 | COH901318_CX_CTRL_MASTER_MODE_M1RW | \ | |
432 | COH901318_CX_CTRL_TCP_DISABLE | \ | |
433 | COH901318_CX_CTRL_TC_IRQ_ENABLE | \ | |
434 | COH901318_CX_CTRL_HSP_DISABLE | \ | |
435 | COH901318_CX_CTRL_HSS_DISABLE | \ | |
436 | COH901318_CX_CTRL_DDMA_LEGACY | \ | |
437 | COH901318_CX_CTRL_PRDD_SOURCE) | |
438 | ||
439 | const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { | |
440 | { | |
441 | .number = U300_DMA_MSL_TX_0, | |
442 | .name = "MSL TX 0", | |
443 | .priority_high = 0, | |
444 | .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20, | |
445 | }, | |
446 | { | |
447 | .number = U300_DMA_MSL_TX_1, | |
448 | .name = "MSL TX 1", | |
449 | .priority_high = 0, | |
450 | .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20, | |
451 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
08d1e2e6 LW |
452 | COH901318_CX_CFG_LCR_DISABLE | |
453 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
454 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
455 | .param.ctrl_lli_chained = 0 | | |
456 | COH901318_CX_CTRL_TC_ENABLE | | |
457 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
458 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
459 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
460 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
461 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
462 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
463 | COH901318_CX_CTRL_TCP_DISABLE | | |
464 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
465 | COH901318_CX_CTRL_HSP_ENABLE | | |
466 | COH901318_CX_CTRL_HSS_DISABLE | | |
467 | COH901318_CX_CTRL_DDMA_LEGACY | | |
468 | COH901318_CX_CTRL_PRDD_SOURCE, | |
469 | .param.ctrl_lli = 0 | | |
470 | COH901318_CX_CTRL_TC_ENABLE | | |
471 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
472 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
473 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
474 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
475 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
476 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
477 | COH901318_CX_CTRL_TCP_ENABLE | | |
478 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
479 | COH901318_CX_CTRL_HSP_ENABLE | | |
480 | COH901318_CX_CTRL_HSS_DISABLE | | |
481 | COH901318_CX_CTRL_DDMA_LEGACY | | |
482 | COH901318_CX_CTRL_PRDD_SOURCE, | |
483 | .param.ctrl_lli_last = 0 | | |
484 | COH901318_CX_CTRL_TC_ENABLE | | |
485 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
486 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
487 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
488 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
489 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
490 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
491 | COH901318_CX_CTRL_TCP_ENABLE | | |
492 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
493 | COH901318_CX_CTRL_HSP_ENABLE | | |
494 | COH901318_CX_CTRL_HSS_DISABLE | | |
495 | COH901318_CX_CTRL_DDMA_LEGACY | | |
496 | COH901318_CX_CTRL_PRDD_SOURCE, | |
497 | }, | |
498 | { | |
499 | .number = U300_DMA_MSL_TX_2, | |
500 | .name = "MSL TX 2", | |
501 | .priority_high = 0, | |
502 | .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20, | |
503 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
08d1e2e6 LW |
504 | COH901318_CX_CFG_LCR_DISABLE | |
505 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
506 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
507 | .param.ctrl_lli_chained = 0 | | |
508 | COH901318_CX_CTRL_TC_ENABLE | | |
509 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
510 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
511 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
512 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
513 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
514 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
515 | COH901318_CX_CTRL_TCP_DISABLE | | |
516 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
517 | COH901318_CX_CTRL_HSP_ENABLE | | |
518 | COH901318_CX_CTRL_HSS_DISABLE | | |
519 | COH901318_CX_CTRL_DDMA_LEGACY | | |
520 | COH901318_CX_CTRL_PRDD_SOURCE, | |
521 | .param.ctrl_lli = 0 | | |
522 | COH901318_CX_CTRL_TC_ENABLE | | |
523 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
524 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
525 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
526 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
527 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
528 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
529 | COH901318_CX_CTRL_TCP_ENABLE | | |
530 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
531 | COH901318_CX_CTRL_HSP_ENABLE | | |
532 | COH901318_CX_CTRL_HSS_DISABLE | | |
533 | COH901318_CX_CTRL_DDMA_LEGACY | | |
534 | COH901318_CX_CTRL_PRDD_SOURCE, | |
535 | .param.ctrl_lli_last = 0 | | |
536 | COH901318_CX_CTRL_TC_ENABLE | | |
537 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
538 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
539 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
540 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
541 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
542 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
543 | COH901318_CX_CTRL_TCP_ENABLE | | |
544 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
545 | COH901318_CX_CTRL_HSP_ENABLE | | |
546 | COH901318_CX_CTRL_HSS_DISABLE | | |
547 | COH901318_CX_CTRL_DDMA_LEGACY | | |
548 | COH901318_CX_CTRL_PRDD_SOURCE, | |
549 | .desc_nbr_max = 10, | |
550 | }, | |
551 | { | |
552 | .number = U300_DMA_MSL_TX_3, | |
553 | .name = "MSL TX 3", | |
554 | .priority_high = 0, | |
555 | .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20, | |
556 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
08d1e2e6 LW |
557 | COH901318_CX_CFG_LCR_DISABLE | |
558 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
559 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
560 | .param.ctrl_lli_chained = 0 | | |
561 | COH901318_CX_CTRL_TC_ENABLE | | |
562 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
563 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
564 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
565 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
566 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
567 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
568 | COH901318_CX_CTRL_TCP_DISABLE | | |
569 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
570 | COH901318_CX_CTRL_HSP_ENABLE | | |
571 | COH901318_CX_CTRL_HSS_DISABLE | | |
572 | COH901318_CX_CTRL_DDMA_LEGACY | | |
573 | COH901318_CX_CTRL_PRDD_SOURCE, | |
574 | .param.ctrl_lli = 0 | | |
575 | COH901318_CX_CTRL_TC_ENABLE | | |
576 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
577 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
578 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
579 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
580 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
581 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
582 | COH901318_CX_CTRL_TCP_ENABLE | | |
583 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
584 | COH901318_CX_CTRL_HSP_ENABLE | | |
585 | COH901318_CX_CTRL_HSS_DISABLE | | |
586 | COH901318_CX_CTRL_DDMA_LEGACY | | |
587 | COH901318_CX_CTRL_PRDD_SOURCE, | |
588 | .param.ctrl_lli_last = 0 | | |
589 | COH901318_CX_CTRL_TC_ENABLE | | |
590 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
591 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
592 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
593 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
594 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
595 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
596 | COH901318_CX_CTRL_TCP_ENABLE | | |
597 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
598 | COH901318_CX_CTRL_HSP_ENABLE | | |
599 | COH901318_CX_CTRL_HSS_DISABLE | | |
600 | COH901318_CX_CTRL_DDMA_LEGACY | | |
601 | COH901318_CX_CTRL_PRDD_SOURCE, | |
602 | }, | |
603 | { | |
604 | .number = U300_DMA_MSL_TX_4, | |
605 | .name = "MSL TX 4", | |
606 | .priority_high = 0, | |
607 | .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20, | |
608 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
08d1e2e6 LW |
609 | COH901318_CX_CFG_LCR_DISABLE | |
610 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
611 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
612 | .param.ctrl_lli_chained = 0 | | |
613 | COH901318_CX_CTRL_TC_ENABLE | | |
614 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
615 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
616 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
617 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
618 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
619 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
620 | COH901318_CX_CTRL_TCP_DISABLE | | |
621 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
622 | COH901318_CX_CTRL_HSP_ENABLE | | |
623 | COH901318_CX_CTRL_HSS_DISABLE | | |
624 | COH901318_CX_CTRL_DDMA_LEGACY | | |
625 | COH901318_CX_CTRL_PRDD_SOURCE, | |
626 | .param.ctrl_lli = 0 | | |
627 | COH901318_CX_CTRL_TC_ENABLE | | |
628 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
629 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
630 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
631 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
632 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
633 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
634 | COH901318_CX_CTRL_TCP_ENABLE | | |
635 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
636 | COH901318_CX_CTRL_HSP_ENABLE | | |
637 | COH901318_CX_CTRL_HSS_DISABLE | | |
638 | COH901318_CX_CTRL_DDMA_LEGACY | | |
639 | COH901318_CX_CTRL_PRDD_SOURCE, | |
640 | .param.ctrl_lli_last = 0 | | |
641 | COH901318_CX_CTRL_TC_ENABLE | | |
642 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
643 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
644 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
645 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
646 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
647 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
648 | COH901318_CX_CTRL_TCP_ENABLE | | |
649 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
650 | COH901318_CX_CTRL_HSP_ENABLE | | |
651 | COH901318_CX_CTRL_HSS_DISABLE | | |
652 | COH901318_CX_CTRL_DDMA_LEGACY | | |
653 | COH901318_CX_CTRL_PRDD_SOURCE, | |
654 | }, | |
655 | { | |
656 | .number = U300_DMA_MSL_TX_5, | |
657 | .name = "MSL TX 5", | |
658 | .priority_high = 0, | |
659 | .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20, | |
660 | }, | |
661 | { | |
662 | .number = U300_DMA_MSL_TX_6, | |
663 | .name = "MSL TX 6", | |
664 | .priority_high = 0, | |
665 | .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20, | |
666 | }, | |
667 | { | |
668 | .number = U300_DMA_MSL_RX_0, | |
669 | .name = "MSL RX 0", | |
670 | .priority_high = 0, | |
671 | .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220, | |
672 | }, | |
673 | { | |
674 | .number = U300_DMA_MSL_RX_1, | |
675 | .name = "MSL RX 1", | |
676 | .priority_high = 0, | |
677 | .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220, | |
678 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
08d1e2e6 LW |
679 | COH901318_CX_CFG_LCR_DISABLE | |
680 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
681 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
682 | .param.ctrl_lli_chained = 0 | | |
683 | COH901318_CX_CTRL_TC_ENABLE | | |
684 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
685 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
686 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
687 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
688 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
689 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
690 | COH901318_CX_CTRL_TCP_DISABLE | | |
691 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
692 | COH901318_CX_CTRL_HSP_ENABLE | | |
693 | COH901318_CX_CTRL_HSS_DISABLE | | |
694 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
695 | COH901318_CX_CTRL_PRDD_DEST, | |
696 | .param.ctrl_lli = 0, | |
697 | .param.ctrl_lli_last = 0 | | |
698 | COH901318_CX_CTRL_TC_ENABLE | | |
699 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
700 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
701 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
702 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
703 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
704 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
705 | COH901318_CX_CTRL_TCP_DISABLE | | |
706 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
707 | COH901318_CX_CTRL_HSP_ENABLE | | |
708 | COH901318_CX_CTRL_HSS_DISABLE | | |
709 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
710 | COH901318_CX_CTRL_PRDD_DEST, | |
711 | }, | |
712 | { | |
713 | .number = U300_DMA_MSL_RX_2, | |
714 | .name = "MSL RX 2", | |
715 | .priority_high = 0, | |
716 | .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220, | |
717 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
08d1e2e6 LW |
718 | COH901318_CX_CFG_LCR_DISABLE | |
719 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
720 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
721 | .param.ctrl_lli_chained = 0 | | |
722 | COH901318_CX_CTRL_TC_ENABLE | | |
723 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
724 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
725 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
726 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
727 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
728 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
729 | COH901318_CX_CTRL_TCP_DISABLE | | |
730 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
731 | COH901318_CX_CTRL_HSP_ENABLE | | |
732 | COH901318_CX_CTRL_HSS_DISABLE | | |
733 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
734 | COH901318_CX_CTRL_PRDD_DEST, | |
735 | .param.ctrl_lli = 0 | | |
736 | COH901318_CX_CTRL_TC_ENABLE | | |
737 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
738 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
739 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
740 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
741 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
742 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
743 | COH901318_CX_CTRL_TCP_DISABLE | | |
744 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
745 | COH901318_CX_CTRL_HSP_ENABLE | | |
746 | COH901318_CX_CTRL_HSS_DISABLE | | |
747 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
748 | COH901318_CX_CTRL_PRDD_DEST, | |
749 | .param.ctrl_lli_last = 0 | | |
750 | COH901318_CX_CTRL_TC_ENABLE | | |
751 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
752 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
753 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
754 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
755 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
756 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
757 | COH901318_CX_CTRL_TCP_DISABLE | | |
758 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
759 | COH901318_CX_CTRL_HSP_ENABLE | | |
760 | COH901318_CX_CTRL_HSS_DISABLE | | |
761 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
762 | COH901318_CX_CTRL_PRDD_DEST, | |
763 | }, | |
764 | { | |
765 | .number = U300_DMA_MSL_RX_3, | |
766 | .name = "MSL RX 3", | |
767 | .priority_high = 0, | |
768 | .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220, | |
769 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
08d1e2e6 LW |
770 | COH901318_CX_CFG_LCR_DISABLE | |
771 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
772 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
773 | .param.ctrl_lli_chained = 0 | | |
774 | COH901318_CX_CTRL_TC_ENABLE | | |
775 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
776 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
777 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
778 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
779 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
780 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
781 | COH901318_CX_CTRL_TCP_DISABLE | | |
782 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
783 | COH901318_CX_CTRL_HSP_ENABLE | | |
784 | COH901318_CX_CTRL_HSS_DISABLE | | |
785 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
786 | COH901318_CX_CTRL_PRDD_DEST, | |
787 | .param.ctrl_lli = 0 | | |
788 | COH901318_CX_CTRL_TC_ENABLE | | |
789 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
790 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
791 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
792 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
793 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
794 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
795 | COH901318_CX_CTRL_TCP_DISABLE | | |
796 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
797 | COH901318_CX_CTRL_HSP_ENABLE | | |
798 | COH901318_CX_CTRL_HSS_DISABLE | | |
799 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
800 | COH901318_CX_CTRL_PRDD_DEST, | |
801 | .param.ctrl_lli_last = 0 | | |
802 | COH901318_CX_CTRL_TC_ENABLE | | |
803 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
804 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
805 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
806 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
807 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
808 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
809 | COH901318_CX_CTRL_TCP_DISABLE | | |
810 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
811 | COH901318_CX_CTRL_HSP_ENABLE | | |
812 | COH901318_CX_CTRL_HSS_DISABLE | | |
813 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
814 | COH901318_CX_CTRL_PRDD_DEST, | |
815 | }, | |
816 | { | |
817 | .number = U300_DMA_MSL_RX_4, | |
818 | .name = "MSL RX 4", | |
819 | .priority_high = 0, | |
820 | .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220, | |
821 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
08d1e2e6 LW |
822 | COH901318_CX_CFG_LCR_DISABLE | |
823 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
824 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
825 | .param.ctrl_lli_chained = 0 | | |
826 | COH901318_CX_CTRL_TC_ENABLE | | |
827 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
828 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
829 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
830 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
831 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
832 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
833 | COH901318_CX_CTRL_TCP_DISABLE | | |
834 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
835 | COH901318_CX_CTRL_HSP_ENABLE | | |
836 | COH901318_CX_CTRL_HSS_DISABLE | | |
837 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
838 | COH901318_CX_CTRL_PRDD_DEST, | |
839 | .param.ctrl_lli = 0 | | |
840 | COH901318_CX_CTRL_TC_ENABLE | | |
841 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
842 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
843 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
844 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
845 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
846 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
847 | COH901318_CX_CTRL_TCP_DISABLE | | |
848 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
849 | COH901318_CX_CTRL_HSP_ENABLE | | |
850 | COH901318_CX_CTRL_HSS_DISABLE | | |
851 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
852 | COH901318_CX_CTRL_PRDD_DEST, | |
853 | .param.ctrl_lli_last = 0 | | |
854 | COH901318_CX_CTRL_TC_ENABLE | | |
855 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
856 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
857 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
858 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
859 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
860 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
861 | COH901318_CX_CTRL_TCP_DISABLE | | |
862 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
863 | COH901318_CX_CTRL_HSP_ENABLE | | |
864 | COH901318_CX_CTRL_HSS_DISABLE | | |
865 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
866 | COH901318_CX_CTRL_PRDD_DEST, | |
867 | }, | |
868 | { | |
869 | .number = U300_DMA_MSL_RX_5, | |
870 | .name = "MSL RX 5", | |
871 | .priority_high = 0, | |
872 | .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220, | |
873 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
08d1e2e6 LW |
874 | COH901318_CX_CFG_LCR_DISABLE | |
875 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
876 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
877 | .param.ctrl_lli_chained = 0 | | |
878 | COH901318_CX_CTRL_TC_ENABLE | | |
879 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
880 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
881 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
882 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
883 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
884 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
885 | COH901318_CX_CTRL_TCP_DISABLE | | |
886 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
887 | COH901318_CX_CTRL_HSP_ENABLE | | |
888 | COH901318_CX_CTRL_HSS_DISABLE | | |
889 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
890 | COH901318_CX_CTRL_PRDD_DEST, | |
891 | .param.ctrl_lli = 0 | | |
892 | COH901318_CX_CTRL_TC_ENABLE | | |
893 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
894 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
895 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
896 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
897 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
898 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
899 | COH901318_CX_CTRL_TCP_DISABLE | | |
900 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
901 | COH901318_CX_CTRL_HSP_ENABLE | | |
902 | COH901318_CX_CTRL_HSS_DISABLE | | |
903 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
904 | COH901318_CX_CTRL_PRDD_DEST, | |
905 | .param.ctrl_lli_last = 0 | | |
906 | COH901318_CX_CTRL_TC_ENABLE | | |
907 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
908 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
909 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
910 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
911 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
912 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
913 | COH901318_CX_CTRL_TCP_DISABLE | | |
914 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
915 | COH901318_CX_CTRL_HSP_ENABLE | | |
916 | COH901318_CX_CTRL_HSS_DISABLE | | |
917 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
918 | COH901318_CX_CTRL_PRDD_DEST, | |
919 | }, | |
920 | { | |
921 | .number = U300_DMA_MSL_RX_6, | |
922 | .name = "MSL RX 6", | |
923 | .priority_high = 0, | |
924 | .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220, | |
925 | }, | |
ec8f1253 LW |
926 | /* |
927 | * Don't set up device address, burst count or size of src | |
928 | * or dst bus for this peripheral - handled by PrimeCell | |
929 | * DMA extension. | |
930 | */ | |
08d1e2e6 LW |
931 | { |
932 | .number = U300_DMA_MMCSD_RX_TX, | |
933 | .name = "MMCSD RX TX", | |
934 | .priority_high = 0, | |
08d1e2e6 | 935 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
08d1e2e6 LW |
936 | COH901318_CX_CFG_LCR_DISABLE | |
937 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
938 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
939 | .param.ctrl_lli_chained = 0 | | |
940 | COH901318_CX_CTRL_TC_ENABLE | | |
08d1e2e6 | 941 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
d4095666 | 942 | COH901318_CX_CTRL_TCP_ENABLE | |
ec8f1253 | 943 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
08d1e2e6 LW |
944 | COH901318_CX_CTRL_HSP_ENABLE | |
945 | COH901318_CX_CTRL_HSS_DISABLE | | |
946 | COH901318_CX_CTRL_DDMA_LEGACY, | |
947 | .param.ctrl_lli = 0 | | |
948 | COH901318_CX_CTRL_TC_ENABLE | | |
08d1e2e6 LW |
949 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
950 | COH901318_CX_CTRL_TCP_ENABLE | | |
ec8f1253 | 951 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
08d1e2e6 LW |
952 | COH901318_CX_CTRL_HSP_ENABLE | |
953 | COH901318_CX_CTRL_HSS_DISABLE | | |
954 | COH901318_CX_CTRL_DDMA_LEGACY, | |
955 | .param.ctrl_lli_last = 0 | | |
956 | COH901318_CX_CTRL_TC_ENABLE | | |
08d1e2e6 | 957 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
d4095666 | 958 | COH901318_CX_CTRL_TCP_DISABLE | |
08d1e2e6 LW |
959 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
960 | COH901318_CX_CTRL_HSP_ENABLE | | |
961 | COH901318_CX_CTRL_HSS_DISABLE | | |
962 | COH901318_CX_CTRL_DDMA_LEGACY, | |
963 | ||
964 | }, | |
965 | { | |
966 | .number = U300_DMA_MSPRO_TX, | |
967 | .name = "MSPRO TX", | |
968 | .priority_high = 0, | |
969 | }, | |
970 | { | |
971 | .number = U300_DMA_MSPRO_RX, | |
972 | .name = "MSPRO RX", | |
973 | .priority_high = 0, | |
974 | }, | |
ec8f1253 LW |
975 | /* |
976 | * Don't set up device address, burst count or size of src | |
977 | * or dst bus for this peripheral - handled by PrimeCell | |
978 | * DMA extension. | |
979 | */ | |
08d1e2e6 LW |
980 | { |
981 | .number = U300_DMA_UART0_TX, | |
982 | .name = "UART0 TX", | |
983 | .priority_high = 0, | |
ec8f1253 LW |
984 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
985 | COH901318_CX_CFG_LCR_DISABLE | | |
986 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
987 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
988 | .param.ctrl_lli_chained = 0 | | |
989 | COH901318_CX_CTRL_TC_ENABLE | | |
990 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
991 | COH901318_CX_CTRL_TCP_ENABLE | | |
992 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
993 | COH901318_CX_CTRL_HSP_ENABLE | | |
994 | COH901318_CX_CTRL_HSS_DISABLE | | |
995 | COH901318_CX_CTRL_DDMA_LEGACY, | |
996 | .param.ctrl_lli = 0 | | |
997 | COH901318_CX_CTRL_TC_ENABLE | | |
998 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
999 | COH901318_CX_CTRL_TCP_ENABLE | | |
1000 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1001 | COH901318_CX_CTRL_HSP_ENABLE | | |
1002 | COH901318_CX_CTRL_HSS_DISABLE | | |
1003 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1004 | .param.ctrl_lli_last = 0 | | |
1005 | COH901318_CX_CTRL_TC_ENABLE | | |
1006 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1007 | COH901318_CX_CTRL_TCP_ENABLE | | |
1008 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1009 | COH901318_CX_CTRL_HSP_ENABLE | | |
1010 | COH901318_CX_CTRL_HSS_DISABLE | | |
1011 | COH901318_CX_CTRL_DDMA_LEGACY, | |
08d1e2e6 LW |
1012 | }, |
1013 | { | |
1014 | .number = U300_DMA_UART0_RX, | |
1015 | .name = "UART0 RX", | |
1016 | .priority_high = 0, | |
ec8f1253 LW |
1017 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
1018 | COH901318_CX_CFG_LCR_DISABLE | | |
1019 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
1020 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
1021 | .param.ctrl_lli_chained = 0 | | |
1022 | COH901318_CX_CTRL_TC_ENABLE | | |
1023 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1024 | COH901318_CX_CTRL_TCP_ENABLE | | |
1025 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1026 | COH901318_CX_CTRL_HSP_ENABLE | | |
1027 | COH901318_CX_CTRL_HSS_DISABLE | | |
1028 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1029 | .param.ctrl_lli = 0 | | |
1030 | COH901318_CX_CTRL_TC_ENABLE | | |
1031 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1032 | COH901318_CX_CTRL_TCP_ENABLE | | |
1033 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1034 | COH901318_CX_CTRL_HSP_ENABLE | | |
1035 | COH901318_CX_CTRL_HSS_DISABLE | | |
1036 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1037 | .param.ctrl_lli_last = 0 | | |
1038 | COH901318_CX_CTRL_TC_ENABLE | | |
1039 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1040 | COH901318_CX_CTRL_TCP_ENABLE | | |
1041 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1042 | COH901318_CX_CTRL_HSP_ENABLE | | |
1043 | COH901318_CX_CTRL_HSS_DISABLE | | |
1044 | COH901318_CX_CTRL_DDMA_LEGACY, | |
08d1e2e6 LW |
1045 | }, |
1046 | { | |
1047 | .number = U300_DMA_APEX_TX, | |
1048 | .name = "APEX TX", | |
1049 | .priority_high = 0, | |
1050 | }, | |
1051 | { | |
1052 | .number = U300_DMA_APEX_RX, | |
1053 | .name = "APEX RX", | |
1054 | .priority_high = 0, | |
1055 | }, | |
1056 | { | |
1057 | .number = U300_DMA_PCM_I2S0_TX, | |
1058 | .name = "PCM I2S0 TX", | |
1059 | .priority_high = 1, | |
1060 | .dev_addr = U300_PCM_I2S0_BASE + 0x14, | |
1061 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
08d1e2e6 LW |
1062 | COH901318_CX_CFG_LCR_DISABLE | |
1063 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
1064 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
1065 | .param.ctrl_lli_chained = 0 | | |
1066 | COH901318_CX_CTRL_TC_ENABLE | | |
1067 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1068 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1069 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
1070 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1071 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
1072 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1073 | COH901318_CX_CTRL_TCP_DISABLE | | |
1074 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1075 | COH901318_CX_CTRL_HSP_ENABLE | | |
1076 | COH901318_CX_CTRL_HSS_DISABLE | | |
1077 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1078 | COH901318_CX_CTRL_PRDD_SOURCE, | |
1079 | .param.ctrl_lli = 0 | | |
1080 | COH901318_CX_CTRL_TC_ENABLE | | |
1081 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1082 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1083 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
1084 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1085 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
1086 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1087 | COH901318_CX_CTRL_TCP_ENABLE | | |
1088 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1089 | COH901318_CX_CTRL_HSP_ENABLE | | |
1090 | COH901318_CX_CTRL_HSS_DISABLE | | |
1091 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1092 | COH901318_CX_CTRL_PRDD_SOURCE, | |
1093 | .param.ctrl_lli_last = 0 | | |
1094 | COH901318_CX_CTRL_TC_ENABLE | | |
1095 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1096 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1097 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
1098 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1099 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
1100 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1101 | COH901318_CX_CTRL_TCP_ENABLE | | |
ec8f1253 | 1102 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
08d1e2e6 LW |
1103 | COH901318_CX_CTRL_HSP_ENABLE | |
1104 | COH901318_CX_CTRL_HSS_DISABLE | | |
1105 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1106 | COH901318_CX_CTRL_PRDD_SOURCE, | |
1107 | }, | |
1108 | { | |
1109 | .number = U300_DMA_PCM_I2S0_RX, | |
1110 | .name = "PCM I2S0 RX", | |
1111 | .priority_high = 1, | |
1112 | .dev_addr = U300_PCM_I2S0_BASE + 0x10, | |
1113 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
08d1e2e6 LW |
1114 | COH901318_CX_CFG_LCR_DISABLE | |
1115 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
1116 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
1117 | .param.ctrl_lli_chained = 0 | | |
1118 | COH901318_CX_CTRL_TC_ENABLE | | |
1119 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1120 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1121 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
1122 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1123 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
1124 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1125 | COH901318_CX_CTRL_TCP_DISABLE | | |
1126 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1127 | COH901318_CX_CTRL_HSP_ENABLE | | |
1128 | COH901318_CX_CTRL_HSS_DISABLE | | |
1129 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1130 | COH901318_CX_CTRL_PRDD_DEST, | |
1131 | .param.ctrl_lli = 0 | | |
1132 | COH901318_CX_CTRL_TC_ENABLE | | |
1133 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1134 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1135 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
1136 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1137 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
1138 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1139 | COH901318_CX_CTRL_TCP_ENABLE | | |
1140 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1141 | COH901318_CX_CTRL_HSP_ENABLE | | |
1142 | COH901318_CX_CTRL_HSS_DISABLE | | |
1143 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1144 | COH901318_CX_CTRL_PRDD_DEST, | |
1145 | .param.ctrl_lli_last = 0 | | |
1146 | COH901318_CX_CTRL_TC_ENABLE | | |
1147 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1148 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1149 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
1150 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1151 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
1152 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1153 | COH901318_CX_CTRL_TCP_ENABLE | | |
1154 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1155 | COH901318_CX_CTRL_HSP_ENABLE | | |
1156 | COH901318_CX_CTRL_HSS_DISABLE | | |
1157 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1158 | COH901318_CX_CTRL_PRDD_DEST, | |
1159 | }, | |
1160 | { | |
1161 | .number = U300_DMA_PCM_I2S1_TX, | |
1162 | .name = "PCM I2S1 TX", | |
1163 | .priority_high = 1, | |
1164 | .dev_addr = U300_PCM_I2S1_BASE + 0x14, | |
1165 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
08d1e2e6 LW |
1166 | COH901318_CX_CFG_LCR_DISABLE | |
1167 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
1168 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
1169 | .param.ctrl_lli_chained = 0 | | |
1170 | COH901318_CX_CTRL_TC_ENABLE | | |
1171 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1172 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1173 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
1174 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1175 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
1176 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1177 | COH901318_CX_CTRL_TCP_DISABLE | | |
1178 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1179 | COH901318_CX_CTRL_HSP_ENABLE | | |
1180 | COH901318_CX_CTRL_HSS_DISABLE | | |
1181 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1182 | COH901318_CX_CTRL_PRDD_SOURCE, | |
1183 | .param.ctrl_lli = 0 | | |
1184 | COH901318_CX_CTRL_TC_ENABLE | | |
1185 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1186 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1187 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
1188 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1189 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
1190 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1191 | COH901318_CX_CTRL_TCP_ENABLE | | |
1192 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1193 | COH901318_CX_CTRL_HSP_ENABLE | | |
1194 | COH901318_CX_CTRL_HSS_DISABLE | | |
1195 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1196 | COH901318_CX_CTRL_PRDD_SOURCE, | |
1197 | .param.ctrl_lli_last = 0 | | |
1198 | COH901318_CX_CTRL_TC_ENABLE | | |
1199 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1200 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1201 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
1202 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1203 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
1204 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1205 | COH901318_CX_CTRL_TCP_ENABLE | | |
1206 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1207 | COH901318_CX_CTRL_HSP_ENABLE | | |
1208 | COH901318_CX_CTRL_HSS_DISABLE | | |
1209 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1210 | COH901318_CX_CTRL_PRDD_SOURCE, | |
1211 | }, | |
1212 | { | |
1213 | .number = U300_DMA_PCM_I2S1_RX, | |
1214 | .name = "PCM I2S1 RX", | |
1215 | .priority_high = 1, | |
1216 | .dev_addr = U300_PCM_I2S1_BASE + 0x10, | |
1217 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
08d1e2e6 LW |
1218 | COH901318_CX_CFG_LCR_DISABLE | |
1219 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
1220 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
1221 | .param.ctrl_lli_chained = 0 | | |
1222 | COH901318_CX_CTRL_TC_ENABLE | | |
1223 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1224 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1225 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
1226 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1227 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
1228 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1229 | COH901318_CX_CTRL_TCP_DISABLE | | |
1230 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1231 | COH901318_CX_CTRL_HSP_ENABLE | | |
1232 | COH901318_CX_CTRL_HSS_DISABLE | | |
1233 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1234 | COH901318_CX_CTRL_PRDD_DEST, | |
1235 | .param.ctrl_lli = 0 | | |
1236 | COH901318_CX_CTRL_TC_ENABLE | | |
1237 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1238 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1239 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
1240 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1241 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
1242 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1243 | COH901318_CX_CTRL_TCP_ENABLE | | |
1244 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1245 | COH901318_CX_CTRL_HSP_ENABLE | | |
1246 | COH901318_CX_CTRL_HSS_DISABLE | | |
1247 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1248 | COH901318_CX_CTRL_PRDD_DEST, | |
1249 | .param.ctrl_lli_last = 0 | | |
1250 | COH901318_CX_CTRL_TC_ENABLE | | |
1251 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1252 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1253 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
1254 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1255 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
1256 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1257 | COH901318_CX_CTRL_TCP_ENABLE | | |
1258 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1259 | COH901318_CX_CTRL_HSP_ENABLE | | |
1260 | COH901318_CX_CTRL_HSS_DISABLE | | |
1261 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1262 | COH901318_CX_CTRL_PRDD_DEST, | |
1263 | }, | |
1264 | { | |
1265 | .number = U300_DMA_XGAM_CDI, | |
1266 | .name = "XGAM CDI", | |
1267 | .priority_high = 0, | |
1268 | }, | |
1269 | { | |
1270 | .number = U300_DMA_XGAM_PDI, | |
1271 | .name = "XGAM PDI", | |
1272 | .priority_high = 0, | |
1273 | }, | |
ec8f1253 LW |
1274 | /* |
1275 | * Don't set up device address, burst count or size of src | |
1276 | * or dst bus for this peripheral - handled by PrimeCell | |
1277 | * DMA extension. | |
1278 | */ | |
08d1e2e6 LW |
1279 | { |
1280 | .number = U300_DMA_SPI_TX, | |
1281 | .name = "SPI TX", | |
1282 | .priority_high = 0, | |
ec8f1253 LW |
1283 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
1284 | COH901318_CX_CFG_LCR_DISABLE | | |
1285 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
1286 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
1287 | .param.ctrl_lli_chained = 0 | | |
1288 | COH901318_CX_CTRL_TC_ENABLE | | |
1289 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1290 | COH901318_CX_CTRL_TCP_DISABLE | | |
1291 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1292 | COH901318_CX_CTRL_HSP_ENABLE | | |
1293 | COH901318_CX_CTRL_HSS_DISABLE | | |
1294 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1295 | .param.ctrl_lli = 0 | | |
1296 | COH901318_CX_CTRL_TC_ENABLE | | |
1297 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1298 | COH901318_CX_CTRL_TCP_DISABLE | | |
1299 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1300 | COH901318_CX_CTRL_HSP_ENABLE | | |
1301 | COH901318_CX_CTRL_HSS_DISABLE | | |
1302 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1303 | .param.ctrl_lli_last = 0 | | |
1304 | COH901318_CX_CTRL_TC_ENABLE | | |
1305 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1306 | COH901318_CX_CTRL_TCP_DISABLE | | |
1307 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1308 | COH901318_CX_CTRL_HSP_ENABLE | | |
1309 | COH901318_CX_CTRL_HSS_DISABLE | | |
1310 | COH901318_CX_CTRL_DDMA_LEGACY, | |
08d1e2e6 LW |
1311 | }, |
1312 | { | |
1313 | .number = U300_DMA_SPI_RX, | |
1314 | .name = "SPI RX", | |
1315 | .priority_high = 0, | |
ec8f1253 LW |
1316 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
1317 | COH901318_CX_CFG_LCR_DISABLE | | |
1318 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
1319 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
1320 | .param.ctrl_lli_chained = 0 | | |
1321 | COH901318_CX_CTRL_TC_ENABLE | | |
1322 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1323 | COH901318_CX_CTRL_TCP_DISABLE | | |
1324 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1325 | COH901318_CX_CTRL_HSP_ENABLE | | |
1326 | COH901318_CX_CTRL_HSS_DISABLE | | |
1327 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1328 | .param.ctrl_lli = 0 | | |
1329 | COH901318_CX_CTRL_TC_ENABLE | | |
1330 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1331 | COH901318_CX_CTRL_TCP_DISABLE | | |
1332 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1333 | COH901318_CX_CTRL_HSP_ENABLE | | |
1334 | COH901318_CX_CTRL_HSS_DISABLE | | |
1335 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1336 | .param.ctrl_lli_last = 0 | | |
1337 | COH901318_CX_CTRL_TC_ENABLE | | |
1338 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1339 | COH901318_CX_CTRL_TCP_DISABLE | | |
1340 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1341 | COH901318_CX_CTRL_HSP_ENABLE | | |
1342 | COH901318_CX_CTRL_HSS_DISABLE | | |
1343 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1344 | ||
08d1e2e6 LW |
1345 | }, |
1346 | { | |
1347 | .number = U300_DMA_GENERAL_PURPOSE_0, | |
1348 | .name = "GENERAL 00", | |
1349 | .priority_high = 0, | |
1350 | ||
1351 | .param.config = flags_memcpy_config, | |
1352 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1353 | .param.ctrl_lli = flags_memcpy_lli, | |
1354 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1355 | }, | |
1356 | { | |
1357 | .number = U300_DMA_GENERAL_PURPOSE_1, | |
1358 | .name = "GENERAL 01", | |
1359 | .priority_high = 0, | |
1360 | ||
1361 | .param.config = flags_memcpy_config, | |
1362 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1363 | .param.ctrl_lli = flags_memcpy_lli, | |
1364 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1365 | }, | |
1366 | { | |
1367 | .number = U300_DMA_GENERAL_PURPOSE_2, | |
1368 | .name = "GENERAL 02", | |
1369 | .priority_high = 0, | |
1370 | ||
1371 | .param.config = flags_memcpy_config, | |
1372 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1373 | .param.ctrl_lli = flags_memcpy_lli, | |
1374 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1375 | }, | |
1376 | { | |
1377 | .number = U300_DMA_GENERAL_PURPOSE_3, | |
1378 | .name = "GENERAL 03", | |
1379 | .priority_high = 0, | |
1380 | ||
1381 | .param.config = flags_memcpy_config, | |
1382 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1383 | .param.ctrl_lli = flags_memcpy_lli, | |
1384 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1385 | }, | |
1386 | { | |
1387 | .number = U300_DMA_GENERAL_PURPOSE_4, | |
1388 | .name = "GENERAL 04", | |
1389 | .priority_high = 0, | |
1390 | ||
1391 | .param.config = flags_memcpy_config, | |
1392 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1393 | .param.ctrl_lli = flags_memcpy_lli, | |
1394 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1395 | }, | |
1396 | { | |
1397 | .number = U300_DMA_GENERAL_PURPOSE_5, | |
1398 | .name = "GENERAL 05", | |
1399 | .priority_high = 0, | |
1400 | ||
1401 | .param.config = flags_memcpy_config, | |
1402 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1403 | .param.ctrl_lli = flags_memcpy_lli, | |
1404 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1405 | }, | |
1406 | { | |
1407 | .number = U300_DMA_GENERAL_PURPOSE_6, | |
1408 | .name = "GENERAL 06", | |
1409 | .priority_high = 0, | |
1410 | ||
1411 | .param.config = flags_memcpy_config, | |
1412 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1413 | .param.ctrl_lli = flags_memcpy_lli, | |
1414 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1415 | }, | |
1416 | { | |
1417 | .number = U300_DMA_GENERAL_PURPOSE_7, | |
1418 | .name = "GENERAL 07", | |
1419 | .priority_high = 0, | |
1420 | ||
1421 | .param.config = flags_memcpy_config, | |
1422 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1423 | .param.ctrl_lli = flags_memcpy_lli, | |
1424 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1425 | }, | |
1426 | { | |
1427 | .number = U300_DMA_GENERAL_PURPOSE_8, | |
1428 | .name = "GENERAL 08", | |
1429 | .priority_high = 0, | |
1430 | ||
1431 | .param.config = flags_memcpy_config, | |
1432 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1433 | .param.ctrl_lli = flags_memcpy_lli, | |
1434 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1435 | }, | |
1436 | #ifdef CONFIG_MACH_U300_BS335 | |
1437 | { | |
1438 | .number = U300_DMA_UART1_TX, | |
1439 | .name = "UART1 TX", | |
1440 | .priority_high = 0, | |
1441 | }, | |
1442 | { | |
1443 | .number = U300_DMA_UART1_RX, | |
1444 | .name = "UART1 RX", | |
1445 | .priority_high = 0, | |
1446 | } | |
1447 | #else | |
1448 | { | |
1449 | .number = U300_DMA_GENERAL_PURPOSE_9, | |
1450 | .name = "GENERAL 09", | |
1451 | .priority_high = 0, | |
1452 | ||
1453 | .param.config = flags_memcpy_config, | |
1454 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1455 | .param.ctrl_lli = flags_memcpy_lli, | |
1456 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1457 | }, | |
1458 | { | |
1459 | .number = U300_DMA_GENERAL_PURPOSE_10, | |
1460 | .name = "GENERAL 10", | |
1461 | .priority_high = 0, | |
1462 | ||
1463 | .param.config = flags_memcpy_config, | |
1464 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1465 | .param.ctrl_lli = flags_memcpy_lli, | |
1466 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1467 | } | |
1468 | #endif | |
1469 | }; | |
1470 | ||
1471 | ||
1472 | static struct coh901318_platform coh901318_platform = { | |
1473 | .chans_slave = dma_slave_channels, | |
1474 | .chans_memcpy = dma_memcpy_channels, | |
1475 | .access_memory_state = coh901318_access_memory_state, | |
1476 | .chan_conf = chan_config, | |
1477 | .max_channels = U300_DMA_CHANNELS, | |
1478 | }; | |
1479 | ||
128a06d4 | 1480 | static struct resource pinctrl_resources[] = { |
98da3529 LW |
1481 | { |
1482 | .start = U300_SYSCON_BASE, | |
1483 | .end = U300_SYSCON_BASE + SZ_4K - 1, | |
1484 | .flags = IORESOURCE_MEM, | |
1485 | }, | |
1486 | }; | |
1487 | ||
bb3cee2b | 1488 | static struct platform_device wdog_device = { |
633e81a6 | 1489 | .name = "coh901327_wdog", |
bb3cee2b LW |
1490 | .id = -1, |
1491 | .num_resources = ARRAY_SIZE(wdog_resources), | |
1492 | .resource = wdog_resources, | |
1493 | }; | |
1494 | ||
1495 | static struct platform_device i2c0_device = { | |
6be2a0ca | 1496 | .name = "stu300", |
bb3cee2b LW |
1497 | .id = 0, |
1498 | .num_resources = ARRAY_SIZE(i2c0_resources), | |
1499 | .resource = i2c0_resources, | |
1500 | }; | |
1501 | ||
1502 | static struct platform_device i2c1_device = { | |
6be2a0ca | 1503 | .name = "stu300", |
bb3cee2b LW |
1504 | .id = 1, |
1505 | .num_resources = ARRAY_SIZE(i2c1_resources), | |
1506 | .resource = i2c1_resources, | |
1507 | }; | |
1508 | ||
128a06d4 LW |
1509 | static struct platform_device pinctrl_device = { |
1510 | .name = "pinctrl-u300", | |
1511 | .id = -1, | |
1512 | .num_resources = ARRAY_SIZE(pinctrl_resources), | |
1513 | .resource = pinctrl_resources, | |
1514 | }; | |
1515 | ||
cc890cd7 LW |
1516 | /* |
1517 | * The different variants have a few different versions of the | |
1518 | * GPIO block, with different number of ports. | |
1519 | */ | |
1520 | static struct u300_gpio_platform u300_gpio_plat = { | |
1521 | #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) | |
1522 | .variant = U300_GPIO_COH901335, | |
1523 | .ports = 3, | |
1524 | #endif | |
1525 | #ifdef CONFIG_MACH_U300_BS335 | |
1526 | .variant = U300_GPIO_COH901571_3_BS335, | |
1527 | .ports = 7, | |
1528 | #endif | |
1529 | #ifdef CONFIG_MACH_U300_BS365 | |
1530 | .variant = U300_GPIO_COH901571_3_BS365, | |
1531 | .ports = 5, | |
1532 | #endif | |
1533 | .gpio_base = 0, | |
1534 | .gpio_irq_base = IRQ_U300_GPIO_BASE, | |
128a06d4 | 1535 | .pinctrl_device = &pinctrl_device, |
cc890cd7 LW |
1536 | }; |
1537 | ||
bb3cee2b LW |
1538 | static struct platform_device gpio_device = { |
1539 | .name = "u300-gpio", | |
1540 | .id = -1, | |
1541 | .num_resources = ARRAY_SIZE(gpio_resources), | |
1542 | .resource = gpio_resources, | |
cc890cd7 LW |
1543 | .dev = { |
1544 | .platform_data = &u300_gpio_plat, | |
1545 | }, | |
bb3cee2b LW |
1546 | }; |
1547 | ||
1548 | static struct platform_device keypad_device = { | |
1549 | .name = "keypad", | |
1550 | .id = -1, | |
1551 | .num_resources = ARRAY_SIZE(keypad_resources), | |
1552 | .resource = keypad_resources, | |
1553 | }; | |
1554 | ||
1555 | static struct platform_device rtc_device = { | |
378ce74b | 1556 | .name = "rtc-coh901331", |
bb3cee2b LW |
1557 | .id = -1, |
1558 | .num_resources = ARRAY_SIZE(rtc_resources), | |
1559 | .resource = rtc_resources, | |
1560 | }; | |
1561 | ||
93ac5a55 LW |
1562 | static struct mtd_partition u300_partitions[] = { |
1563 | { | |
1564 | .name = "bootrecords", | |
1565 | .offset = 0, | |
1566 | .size = SZ_128K, | |
1567 | }, | |
1568 | { | |
1569 | .name = "free", | |
1570 | .offset = SZ_128K, | |
1571 | .size = 8064 * SZ_1K, | |
1572 | }, | |
1573 | { | |
1574 | .name = "platform", | |
1575 | .offset = 8192 * SZ_1K, | |
1576 | .size = 253952 * SZ_1K, | |
1577 | }, | |
1578 | }; | |
1579 | ||
1580 | static struct fsmc_nand_platform_data nand_platform_data = { | |
1581 | .partitions = u300_partitions, | |
1582 | .nr_partitions = ARRAY_SIZE(u300_partitions), | |
1583 | .options = NAND_SKIP_BBTSCAN, | |
1584 | .width = FSMC_NAND_BW8, | |
1585 | }; | |
1586 | ||
1587 | static struct platform_device nand_device = { | |
1588 | .name = "fsmc-nand", | |
bb3cee2b | 1589 | .id = -1, |
bb3cee2b | 1590 | .resource = fsmc_resources, |
93ac5a55 LW |
1591 | .num_resources = ARRAY_SIZE(fsmc_resources), |
1592 | .dev = { | |
1593 | .platform_data = &nand_platform_data, | |
1594 | }, | |
bb3cee2b LW |
1595 | }; |
1596 | ||
08d1e2e6 LW |
1597 | static struct platform_device dma_device = { |
1598 | .name = "coh901318", | |
1599 | .id = -1, | |
1600 | .resource = dma_resource, | |
1601 | .num_resources = ARRAY_SIZE(dma_resource), | |
1602 | .dev = { | |
1603 | .platform_data = &coh901318_platform, | |
1604 | .coherent_dma_mask = ~0, | |
1605 | }, | |
1606 | }; | |
1607 | ||
98da3529 | 1608 | /* Pinmux settings */ |
e93bcee0 | 1609 | static struct pinctrl_map __initdata u300_pinmux_map[] = { |
98da3529 | 1610 | /* anonymous maps for chip power and EMIFs */ |
1e2082b5 SW |
1611 | PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"), |
1612 | PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"), | |
1613 | PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"), | |
98da3529 | 1614 | /* per-device maps for MMC/SD, SPI and UART */ |
1e2082b5 SW |
1615 | PIN_MAP_MUX_GROUP_DEFAULT("mmci", "pinctrl-u300", NULL, "mmc0"), |
1616 | PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"), | |
1617 | PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"), | |
98da3529 LW |
1618 | }; |
1619 | ||
1620 | struct u300_mux_hog { | |
98da3529 | 1621 | struct device *dev; |
e93bcee0 | 1622 | struct pinctrl *p; |
98da3529 LW |
1623 | }; |
1624 | ||
1625 | static struct u300_mux_hog u300_mux_hogs[] = { | |
1626 | { | |
98da3529 LW |
1627 | .dev = &uart0_device.dev, |
1628 | }, | |
1629 | { | |
98da3529 LW |
1630 | .dev = &pl022_device.dev, |
1631 | }, | |
1632 | { | |
98da3529 LW |
1633 | .dev = &mmcsd_device.dev, |
1634 | }, | |
1635 | }; | |
1636 | ||
e93bcee0 | 1637 | static int __init u300_pinctrl_fetch(void) |
98da3529 LW |
1638 | { |
1639 | int i; | |
1640 | ||
1641 | for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) { | |
e93bcee0 | 1642 | struct pinctrl *p; |
98da3529 LW |
1643 | int ret; |
1644 | ||
6e5e959d | 1645 | p = pinctrl_get_select_default(u300_mux_hogs[i].dev); |
e93bcee0 | 1646 | if (IS_ERR(p)) { |
6e5e959d SW |
1647 | pr_err("u300: could not get pinmux hog for dev %s\n", |
1648 | dev_name(u300_mux_hogs[i].dev)); | |
98da3529 LW |
1649 | continue; |
1650 | } | |
e93bcee0 | 1651 | u300_mux_hogs[i].p = p; |
98da3529 LW |
1652 | } |
1653 | return 0; | |
1654 | } | |
e93bcee0 | 1655 | subsys_initcall(u300_pinctrl_fetch); |
98da3529 | 1656 | |
bb3cee2b LW |
1657 | /* |
1658 | * Notice that AMBA devices are initialized before platform devices. | |
1659 | * | |
1660 | */ | |
1661 | static struct platform_device *platform_devs[] __initdata = { | |
08d1e2e6 | 1662 | &dma_device, |
bb3cee2b LW |
1663 | &i2c0_device, |
1664 | &i2c1_device, | |
1665 | &keypad_device, | |
1666 | &rtc_device, | |
1667 | &gpio_device, | |
93ac5a55 | 1668 | &nand_device, |
bb3cee2b | 1669 | &wdog_device, |
bb3cee2b LW |
1670 | }; |
1671 | ||
bb3cee2b LW |
1672 | /* |
1673 | * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected | |
1674 | * together so some interrupts are connected to the first one and some | |
1675 | * to the second one. | |
1676 | */ | |
1677 | void __init u300_init_irq(void) | |
1678 | { | |
1679 | u32 mask[2] = {0, 0}; | |
b7276b23 | 1680 | struct clk *clk; |
bb3cee2b LW |
1681 | int i; |
1682 | ||
379aae5d LW |
1683 | /* initialize clocking early, we want to clock the INTCON */ |
1684 | u300_clock_init(); | |
1685 | ||
b7276b23 LW |
1686 | /* Clock the interrupt controller */ |
1687 | clk = clk_get_sys("intcon", NULL); | |
1688 | BUG_ON(IS_ERR(clk)); | |
1689 | clk_enable(clk); | |
1690 | ||
cc890cd7 | 1691 | for (i = 0; i < U300_VIC_IRQS_END; i++) |
bb3cee2b | 1692 | set_bit(i, (unsigned long *) &mask[0]); |
6860107a LW |
1693 | vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]); |
1694 | vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]); | |
bb3cee2b LW |
1695 | } |
1696 | ||
1697 | ||
1698 | /* | |
1699 | * U300 platforms peripheral handling | |
1700 | */ | |
1701 | struct db_chip { | |
1702 | u16 chipid; | |
1703 | const char *name; | |
1704 | }; | |
1705 | ||
1706 | /* | |
1707 | * This is a list of the Digital Baseband chips used in the U300 platform. | |
1708 | */ | |
1709 | static struct db_chip db_chips[] __initdata = { | |
1710 | { | |
1711 | .chipid = 0xb800, | |
1712 | .name = "DB3000", | |
1713 | }, | |
1714 | { | |
1715 | .chipid = 0xc000, | |
1716 | .name = "DB3100", | |
1717 | }, | |
1718 | { | |
1719 | .chipid = 0xc800, | |
1720 | .name = "DB3150", | |
1721 | }, | |
1722 | { | |
1723 | .chipid = 0xd800, | |
1724 | .name = "DB3200", | |
1725 | }, | |
1726 | { | |
1727 | .chipid = 0xe000, | |
1728 | .name = "DB3250", | |
1729 | }, | |
1730 | { | |
1731 | .chipid = 0xe800, | |
1732 | .name = "DB3210", | |
1733 | }, | |
1734 | { | |
1735 | .chipid = 0xf000, | |
1736 | .name = "DB3350 P1x", | |
1737 | }, | |
1738 | { | |
1739 | .chipid = 0xf100, | |
1740 | .name = "DB3350 P2x", | |
1741 | }, | |
1742 | { | |
1743 | .chipid = 0x0000, /* List terminator */ | |
1744 | .name = NULL, | |
1745 | } | |
1746 | }; | |
1747 | ||
a2bb9f4d | 1748 | static void __init u300_init_check_chip(void) |
bb3cee2b LW |
1749 | { |
1750 | ||
1751 | u16 val; | |
1752 | struct db_chip *chip; | |
1753 | const char *chipname; | |
1754 | const char unknown[] = "UNKNOWN"; | |
1755 | ||
1756 | /* Read out and print chip ID */ | |
1757 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR); | |
1758 | /* This is in funky bigendian order... */ | |
1759 | val = (val & 0xFFU) << 8 | (val >> 8); | |
1760 | chip = db_chips; | |
1761 | chipname = unknown; | |
1762 | ||
1763 | for ( ; chip->chipid; chip++) { | |
1764 | if (chip->chipid == (val & 0xFF00U)) { | |
1765 | chipname = chip->name; | |
1766 | break; | |
1767 | } | |
1768 | } | |
1769 | printk(KERN_INFO "Initializing U300 system on %s baseband chip " \ | |
1770 | "(chip ID 0x%04x)\n", chipname, val); | |
1771 | ||
bb3cee2b LW |
1772 | #ifdef CONFIG_MACH_U300_BS330 |
1773 | if ((val & 0xFF00U) != 0xd800) { | |
1774 | printk(KERN_ERR "Platform configured for BS330 " \ | |
1775 | "with DB3200 but %s detected, expect problems!", | |
1776 | chipname); | |
1777 | } | |
1778 | #endif | |
1779 | #ifdef CONFIG_MACH_U300_BS335 | |
1780 | if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) { | |
ec8f1253 | 1781 | printk(KERN_ERR "Platform configured for BS335 " \ |
bb3cee2b LW |
1782 | " with DB3350 but %s detected, expect problems!", |
1783 | chipname); | |
1784 | } | |
1785 | #endif | |
1786 | #ifdef CONFIG_MACH_U300_BS365 | |
1787 | if ((val & 0xFF00U) != 0xe800) { | |
1788 | printk(KERN_ERR "Platform configured for BS365 " \ | |
1789 | "with DB3210 but %s detected, expect problems!", | |
1790 | chipname); | |
1791 | } | |
1792 | #endif | |
1793 | ||
1794 | ||
1795 | } | |
1796 | ||
1797 | /* | |
1798 | * Some devices and their resources require reserved physical memory from | |
1799 | * the end of the available RAM. This function traverses the list of devices | |
3ad2f3fb | 1800 | * and assigns actual addresses to these. |
bb3cee2b LW |
1801 | */ |
1802 | static void __init u300_assign_physmem(void) | |
1803 | { | |
1804 | unsigned long curr_start = __pa(high_memory); | |
1805 | int i, j; | |
1806 | ||
1807 | for (i = 0; i < ARRAY_SIZE(platform_devs); i++) { | |
1808 | for (j = 0; j < platform_devs[i]->num_resources; j++) { | |
1809 | struct resource *const res = | |
1810 | &platform_devs[i]->resource[j]; | |
1811 | ||
1812 | if (IORESOURCE_MEM == res->flags && | |
1813 | 0 == res->start) { | |
1814 | res->start = curr_start; | |
1815 | res->end += curr_start; | |
28f65c11 | 1816 | curr_start += resource_size(res); |
bb3cee2b LW |
1817 | |
1818 | printk(KERN_INFO "core.c: Mapping RAM " \ | |
1819 | "%#x-%#x to device %s:%s\n", | |
1820 | res->start, res->end, | |
1821 | platform_devs[i]->name, res->name); | |
1822 | } | |
1823 | } | |
1824 | } | |
1825 | } | |
1826 | ||
1827 | void __init u300_init_devices(void) | |
1828 | { | |
1829 | int i; | |
1830 | u16 val; | |
1831 | ||
1832 | /* Check what platform we run and print some status information */ | |
1833 | u300_init_check_chip(); | |
1834 | ||
1835 | /* Set system to run at PLL208, max performance, a known state. */ | |
1836 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); | |
1837 | val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK; | |
1838 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); | |
1839 | /* Wait for the PLL208 to lock if not locked in yet */ | |
1840 | while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) & | |
1841 | U300_SYSCON_CSR_PLL208_LOCK_IND)); | |
c7c8c78f LW |
1842 | /* Initialize SPI device with some board specifics */ |
1843 | u300_spi_init(&pl022_device); | |
bb3cee2b LW |
1844 | |
1845 | /* Register the AMBA devices in the AMBA bus abstraction layer */ | |
bb3cee2b LW |
1846 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
1847 | struct amba_device *d = amba_devs[i]; | |
1848 | amba_device_register(d, &iomem_resource); | |
1849 | } | |
bb3cee2b LW |
1850 | |
1851 | u300_assign_physmem(); | |
1852 | ||
98da3529 | 1853 | /* Initialize pinmuxing */ |
e93bcee0 LW |
1854 | pinctrl_register_mappings(u300_pinmux_map, |
1855 | ARRAY_SIZE(u300_pinmux_map)); | |
98da3529 | 1856 | |
6be2a0ca LW |
1857 | /* Register subdevices on the I2C buses */ |
1858 | u300_i2c_register_board_devices(); | |
1859 | ||
bb3cee2b LW |
1860 | /* Register the platform devices */ |
1861 | platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); | |
1862 | ||
ec8f1253 LW |
1863 | /* Register subdevices on the SPI bus */ |
1864 | u300_spi_register_board_devices(); | |
1865 | ||
c43ed560 | 1866 | /* Enable SEMI self refresh */ |
bb3cee2b LW |
1867 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) | |
1868 | U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE; | |
1869 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR); | |
bb3cee2b LW |
1870 | } |
1871 | ||
1872 | static int core_module_init(void) | |
1873 | { | |
1874 | /* | |
1875 | * This needs to be initialized later: it needs the input framework | |
1876 | * to be initialized first. | |
1877 | */ | |
1878 | return mmc_init(&mmcsd_device); | |
1879 | } | |
1880 | module_init(core_module_init); | |
7e3974b2 RK |
1881 | |
1882 | /* Forward declare this function from the watchdog */ | |
1883 | void coh901327_watchdog_reset(void); | |
1884 | ||
1885 | void u300_restart(char mode, const char *cmd) | |
1886 | { | |
1887 | switch (mode) { | |
1888 | case 's': | |
1889 | case 'h': | |
7e3974b2 RK |
1890 | #ifdef CONFIG_COH901327_WATCHDOG |
1891 | coh901327_watchdog_reset(); | |
1892 | #endif | |
1893 | break; | |
1894 | default: | |
1895 | /* Do nothing */ | |
1896 | break; | |
1897 | } | |
1898 | /* Wait for system do die/reset. */ | |
1899 | while (1); | |
1900 | } |