[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-spear3xx / spear3xx.c

/*
 * arch/arm/mach-spear3xx/spear3xx.c
 *
 * SPEAr3XX machines common source file
 *
 * Copyright (C) 2009-2012 ST Microelectronics
 * Viresh Kumar <viresh.linux@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#define pr_fmt(fmt) "SPEAr3xx: " fmt

#include <linux/amba/pl022.h>
#include <linux/amba/pl080.h>
#include <linux/io.h>
#include <plat/pl080.h>
#include <mach/generic.h>
#include <mach/spear.h>

/* ssp device registration */
struct pl022_ssp_controller pl022_plat_data = {
	.bus_id = 0,
	.enable_dma = 1,
	.dma_filter = pl08x_filter_id,
	.dma_tx_param = "ssp0_tx",
	.dma_rx_param = "ssp0_rx",
	/*
	 * This is number of spi devices that can be connected to spi. There are
	 * two type of chipselects on which slave devices can work. One is chip
	 * select provided by spi masters other is controlled through external
	 * gpio's. We can't use chipselect provided from spi master (because as
	 * soon as FIFO becomes empty, CS is disabled and transfer ends). So
	 * this number now depends on number of gpios available for spi. each
	 * slave on each master requires a separate gpio pin.
	 */
	.num_chipselect = 2,
};

/* dmac device registration */
struct pl08x_platform_data pl080_plat_data = {
	.memcpy_channel = {
		.bus_id = "memcpy",
		.cctl_memcpy =
			(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
			PL080_CONTROL_PROT_SYS),
	},
	.lli_buses = PL08X_AHB1,
	.mem_buses = PL08X_AHB1,
	.get_signal = pl080_get_signal,
	.put_signal = pl080_put_signal,
};

/*
 * Following will create 16MB static virtual/physical mappings
 * PHYSICAL		VIRTUAL
 * 0xD0000000		0xFD000000
 * 0xFC000000		0xFC000000
 */
struct map_desc spear3xx_io_desc[] __initdata = {
	{
		.virtual	= VA_SPEAR3XX_ICM1_2_BASE,
		.pfn		= __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	}, {
		.virtual	= VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	},
};

/* This will create static memory mapping for selected devices */
void __init spear3xx_map_io(void)
{
	iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
}

void __init spear3xx_timer_init(void)
{
	char pclk_name[] = "pll3_clk";
	struct clk *gpt_clk, *pclk;

	spear3xx_clk_init();

	/* get the system timer clock */
	gpt_clk = clk_get_sys("gpt0", NULL);
	if (IS_ERR(gpt_clk)) {
		pr_err("%s:couldn't get clk for gpt\n", __func__);
		BUG();
	}

	/* get the suitable parent clock for timer*/
	pclk = clk_get(NULL, pclk_name);
	if (IS_ERR(pclk)) {
		pr_err("%s:couldn't get %s as parent for gpt\n",
				__func__, pclk_name);
		BUG();
	}

	clk_set_parent(gpt_clk, pclk);
	clk_put(gpt_clk);
	clk_put(pclk);

	spear_setup_of_timer();
}
Commit	Line	Data
bc4e814e VK	1	/*
	2	* arch/arm/mach-spear3xx/spear3xx.c
	3	*
	4	* SPEAr3XX machines common source file
	5	*
c5fa4fdc	6	* Copyright (C) 2009-2012 ST Microelectronics
10d8935f	7	* Viresh Kumar <viresh.linux@gmail.com>
bc4e814e VK	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
5fb00f96 VK	14	#define pr_fmt(fmt) "SPEAr3xx: " fmt
5fb00f96 VK	15
c5fa4fdc	16	#include <linux/amba/pl022.h>
27f423fe	17	#include <linux/amba/pl080.h>
bc4e814e	18	#include <linux/io.h>
0b7ee717	19	#include <plat/pl080.h>
bc4e814e	20	#include <mach/generic.h>
5019f0b1	21	#include <mach/spear.h>
bc4e814e	22
c5fa4fdc VK	23	/* ssp device registration */
	24	struct pl022_ssp_controller pl022_plat_data = {
	25	.bus_id = 0,
	26	.enable_dma = 1,
	27	.dma_filter = pl08x_filter_id,
	28	.dma_tx_param = "ssp0_tx",
	29	.dma_rx_param = "ssp0_rx",
	30	/*
	31	* This is number of spi devices that can be connected to spi. There are
	32	* two type of chipselects on which slave devices can work. One is chip
	33	* select provided by spi masters other is controlled through external
	34	* gpio's. We can't use chipselect provided from spi master (because as
	35	* soon as FIFO becomes empty, CS is disabled and transfer ends). So
	36	* this number now depends on number of gpios available for spi. each
	37	* slave on each master requires a separate gpio pin.
	38	*/
	39	.num_chipselect = 2,
	40	};
	41
0b7ee717 VK	42	/* dmac device registration */
	43	struct pl08x_platform_data pl080_plat_data = {
	44	.memcpy_channel = {
	45	.bus_id = "memcpy",
dc8d5f8d RK	46	.cctl_memcpy =
dc8d5f8d RK	47	(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT \| \
0b7ee717 VK	48	PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT \| \
	49	PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT \| \
	50	PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT \| \
	51	PL080_CONTROL_PROT_BUFF \| PL080_CONTROL_PROT_CACHE \| \
	52	PL080_CONTROL_PROT_SYS),
	53	},
	54	.lli_buses = PL08X_AHB1,
	55	.mem_buses = PL08X_AHB1,
	56	.get_signal = pl080_get_signal,
	57	.put_signal = pl080_put_signal,
bc4e814e VK	58	};
bc4e814e VK	59
c5fa4fdc VK	60	/*
	61	* Following will create 16MB static virtual/physical mappings
	62	* PHYSICAL VIRTUAL
	63	* 0xD0000000 0xFD000000
	64	* 0xFC000000 0xFC000000
	65	*/
bc4e814e VK	66	struct map_desc spear3xx_io_desc[] __initdata = {
bc4e814e VK	67	{
c5fa4fdc VK	68	.virtual = VA_SPEAR3XX_ICM1_2_BASE,
	69	.pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
	70	.length = SZ_16M,
bc4e814e VK	71	.type = MT_DEVICE
bc4e814e VK	72	}, {
c5fa4fdc VK	73	.virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
	74	.pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
	75	.length = SZ_16M,
bc4e814e VK	76	.type = MT_DEVICE
	77	},
	78	};
	79
	80	/* This will create static memory mapping for selected devices */
	81	void __init spear3xx_map_io(void)
	82	{
	83	iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
bc4e814e	84	}
70f4c0bf	85
6bb27d73	86	void __init spear3xx_timer_init(void)
5c881d9a	87	{
5cfc545f	88	char pclk_name[] = "pll3_clk";
5c881d9a SH	89	struct clk gpt_clk, pclk;
5c881d9a SH	90
5df33a62 VK	91	spear3xx_clk_init();
5df33a62 VK	92
5c881d9a SH	93	/* get the system timer clock */
	94	gpt_clk = clk_get_sys("gpt0", NULL);
	95	if (IS_ERR(gpt_clk)) {
	96	pr_err("%s:couldn't get clk for gpt\n", __func__);
	97	BUG();
	98	}
	99
	100	/* get the suitable parent clock for timer*/
	101	pclk = clk_get(NULL, pclk_name);
	102	if (IS_ERR(pclk)) {
	103	pr_err("%s:couldn't get %s as parent for gpt\n",
	104	__func__, pclk_name);
	105	BUG();
	106	}
	107
	108	clk_set_parent(gpt_clk, pclk);
	109	clk_put(gpt_clk);
	110	clk_put(pclk);
	111
30551c01	112	spear_setup_of_timer();
5c881d9a	113	}