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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-spear3xx / spear300.c
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bc4e814e
VK		 1/*
2 * arch/arm/mach-spear3xx/spear300.c
3 *
4 * SPEAr300 machine source file
5 *
c5fa4fdc 6 * Copyright (C) 2009-2012 ST Microelectronics
10d8935f 7 * Viresh Kumar <viresh.linux@gmail.com>
bc4e814e
VK		 8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
5fb00f96
VK		 14#define pr_fmt(fmt) "SPEAr300: " fmt
15
0b7ee717 16#include <linux/amba/pl08x.h>
c5fa4fdc
VK		 17#include <linux/of_platform.h>
18#include <asm/hardware/vic.h>
19#include <asm/mach/arch.h>
410782be 20#include <plat/shirq.h>
bc4e814e 21#include <mach/generic.h>
5019f0b1
AB		 22#include <mach/spear.h>
23
24/* Base address of various IPs */
25#define SPEAR300_TELECOM_BASE UL(0x50000000)
26
27/* Interrupt registers offsets and masks */
28#define SPEAR300_INT_ENB_MASK_REG 0x54
29#define SPEAR300_INT_STS_MASK_REG 0x58
30#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
31#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
32#define SPEAR300_I2S_IRQ_MASK (1 << 2)
33#define SPEAR300_TDM_IRQ_MASK (1 << 3)
34#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
35#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
36#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
37#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
38#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
39
40#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
41
42#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
43
44
45/* SPEAr300 Virtual irq definitions */
46/* IRQs sharing IRQ_GEN_RAS_1 */
47#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
48#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
49#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
50#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
51#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
52#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
53#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
54#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
55#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
56
57/* IRQs sharing IRQ_GEN_RAS_3 */
58#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
59
60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
bc4e814e 62
4c18e77f 63/* spear3xx shared irq */
f6558bf9 64static struct shirq_dev_config shirq_ras1_config[] = {
4c18e77f 65 {
61e72bca
RM		 66 .virq = SPEAR300_VIRQ_IT_PERS_S,
67 .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
68 .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
4c18e77f 69 }, {
61e72bca
RM		 70 .virq = SPEAR300_VIRQ_IT_CHANGE_S,
71 .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
72 .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
4c18e77f 73 }, {
61e72bca
RM		 74 .virq = SPEAR300_VIRQ_I2S,
75 .enb_mask = SPEAR300_I2S_IRQ_MASK,
76 .status_mask = SPEAR300_I2S_IRQ_MASK,
4c18e77f 77 }, {
61e72bca
RM		 78 .virq = SPEAR300_VIRQ_TDM,
79 .enb_mask = SPEAR300_TDM_IRQ_MASK,
80 .status_mask = SPEAR300_TDM_IRQ_MASK,
4c18e77f 81 }, {
61e72bca
RM		 82 .virq = SPEAR300_VIRQ_CAMERA_L,
83 .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
84 .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
4c18e77f 85 }, {
61e72bca
RM		 86 .virq = SPEAR300_VIRQ_CAMERA_F,
87 .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
88 .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
4c18e77f 89 }, {
61e72bca
RM		 90 .virq = SPEAR300_VIRQ_CAMERA_V,
91 .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
92 .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
4c18e77f 93 }, {
61e72bca
RM		 94 .virq = SPEAR300_VIRQ_KEYBOARD,
95 .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
96 .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
4c18e77f 97 }, {
61e72bca
RM		 98 .virq = SPEAR300_VIRQ_GPIO1,
99 .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
100 .status_mask = SPEAR300_GPIO1_IRQ_MASK,
4c18e77f
VK		 101 },
102};
103
f6558bf9 104static struct spear_shirq shirq_ras1 = {
61e72bca 105 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
4c18e77f
VK		 106 .dev_config = shirq_ras1_config,
107 .dev_count = ARRAY_SIZE(shirq_ras1_config),
108 .regs = {
61e72bca
RM		 109 .enb_reg = SPEAR300_INT_ENB_MASK_REG,
110 .status_reg = SPEAR300_INT_STS_MASK_REG,
111 .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
4c18e77f
VK		 112 .clear_reg = -1,
113 },
bc4e814e
VK		 114};
115
0b7ee717
VK		 116/* DMAC platform data's slave info */
117struct pl08x_channel_data spear300_dma_info[] = {
118 {
119 .bus_id = "uart0_rx",
120 .min_signal = 2,
121 .max_signal = 2,
122 .muxval = 0,
123 .cctl = 0,
124 .periph_buses = PL08X_AHB1,
125 }, {
126 .bus_id = "uart0_tx",
127 .min_signal = 3,
128 .max_signal = 3,
129 .muxval = 0,
130 .cctl = 0,
131 .periph_buses = PL08X_AHB1,
132 }, {
133 .bus_id = "ssp0_rx",
134 .min_signal = 8,
135 .max_signal = 8,
136 .muxval = 0,
137 .cctl = 0,
138 .periph_buses = PL08X_AHB1,
139 }, {
140 .bus_id = "ssp0_tx",
141 .min_signal = 9,
142 .max_signal = 9,
143 .muxval = 0,
144 .cctl = 0,
145 .periph_buses = PL08X_AHB1,
146 }, {
147 .bus_id = "i2c_rx",
148 .min_signal = 10,
149 .max_signal = 10,
150 .muxval = 0,
151 .cctl = 0,
152 .periph_buses = PL08X_AHB1,
153 }, {
154 .bus_id = "i2c_tx",
155 .min_signal = 11,
156 .max_signal = 11,
157 .muxval = 0,
158 .cctl = 0,
159 .periph_buses = PL08X_AHB1,
160 }, {
161 .bus_id = "irda",
162 .min_signal = 12,
163 .max_signal = 12,
164 .muxval = 0,
165 .cctl = 0,
166 .periph_buses = PL08X_AHB1,
167 }, {
168 .bus_id = "adc",
169 .min_signal = 13,
170 .max_signal = 13,
171 .muxval = 0,
172 .cctl = 0,
173 .periph_buses = PL08X_AHB1,
174 }, {
175 .bus_id = "to_jpeg",
176 .min_signal = 14,
177 .max_signal = 14,
178 .muxval = 0,
179 .cctl = 0,
180 .periph_buses = PL08X_AHB1,
181 }, {
182 .bus_id = "from_jpeg",
183 .min_signal = 15,
184 .max_signal = 15,
185 .muxval = 0,
186 .cctl = 0,
187 .periph_buses = PL08X_AHB1,
188 }, {
189 .bus_id = "ras0_rx",
190 .min_signal = 0,
191 .max_signal = 0,
192 .muxval = 1,
193 .cctl = 0,
194 .periph_buses = PL08X_AHB1,
195 }, {
196 .bus_id = "ras0_tx",
197 .min_signal = 1,
198 .max_signal = 1,
199 .muxval = 1,
200 .cctl = 0,
201 .periph_buses = PL08X_AHB1,
202 }, {
203 .bus_id = "ras1_rx",
204 .min_signal = 2,
205 .max_signal = 2,
206 .muxval = 1,
207 .cctl = 0,
208 .periph_buses = PL08X_AHB1,
209 }, {
210 .bus_id = "ras1_tx",
211 .min_signal = 3,
212 .max_signal = 3,
213 .muxval = 1,
214 .cctl = 0,
215 .periph_buses = PL08X_AHB1,
216 }, {
217 .bus_id = "ras2_rx",
218 .min_signal = 4,
219 .max_signal = 4,
220 .muxval = 1,
221 .cctl = 0,
222 .periph_buses = PL08X_AHB1,
223 }, {
224 .bus_id = "ras2_tx",
225 .min_signal = 5,
226 .max_signal = 5,
227 .muxval = 1,
228 .cctl = 0,
229 .periph_buses = PL08X_AHB1,
230 }, {
231 .bus_id = "ras3_rx",
232 .min_signal = 6,
233 .max_signal = 6,
234 .muxval = 1,
235 .cctl = 0,
236 .periph_buses = PL08X_AHB1,
237 }, {
238 .bus_id = "ras3_tx",
239 .min_signal = 7,
240 .max_signal = 7,
241 .muxval = 1,
242 .cctl = 0,
243 .periph_buses = PL08X_AHB1,
244 }, {
245 .bus_id = "ras4_rx",
246 .min_signal = 8,
247 .max_signal = 8,
248 .muxval = 1,
249 .cctl = 0,
250 .periph_buses = PL08X_AHB1,
251 }, {
252 .bus_id = "ras4_tx",
253 .min_signal = 9,
254 .max_signal = 9,
255 .muxval = 1,
256 .cctl = 0,
257 .periph_buses = PL08X_AHB1,
258 }, {
259 .bus_id = "ras5_rx",
260 .min_signal = 10,
261 .max_signal = 10,
262 .muxval = 1,
263 .cctl = 0,
264 .periph_buses = PL08X_AHB1,
265 }, {
266 .bus_id = "ras5_tx",
267 .min_signal = 11,
268 .max_signal = 11,
269 .muxval = 1,
270 .cctl = 0,
271 .periph_buses = PL08X_AHB1,
272 }, {
273 .bus_id = "ras6_rx",
274 .min_signal = 12,
275 .max_signal = 12,
276 .muxval = 1,
277 .cctl = 0,
278 .periph_buses = PL08X_AHB1,
279 }, {
280 .bus_id = "ras6_tx",
281 .min_signal = 13,
282 .max_signal = 13,
283 .muxval = 1,
284 .cctl = 0,
285 .periph_buses = PL08X_AHB1,
286 }, {
287 .bus_id = "ras7_rx",
288 .min_signal = 14,
289 .max_signal = 14,
290 .muxval = 1,
291 .cctl = 0,
292 .periph_buses = PL08X_AHB1,
293 }, {
294 .bus_id = "ras7_tx",
295 .min_signal = 15,
296 .max_signal = 15,
297 .muxval = 1,
298 .cctl = 0,
299 .periph_buses = PL08X_AHB1,
300 },
301};
302
c5fa4fdc
VK		 303/* Add SPEAr300 auxdata to pass platform data */
304static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
305 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
306 &pl022_plat_data),
0b7ee717
VK		 307 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
308 &pl080_plat_data),
c5fa4fdc
VK		 309 {}
310};
c2c07831 311
c5fa4fdc 312static void __init spear300_dt_init(void)
bc4e814e 313{
8076dd1b 314 int ret;
4c18e77f 315
0b7ee717
VK		 316 pl080_plat_data.slave_channels = spear300_dma_info;
317 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
318
c5fa4fdc
VK		 319 of_platform_populate(NULL, of_default_bus_match_table,
320 spear300_auxdata_lookup, NULL);
4c18e77f 321
b595076a 322 /* shared irq registration */
53821162 323 shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
4c18e77f
VK		 324 if (shirq_ras1.regs.base) {
325 ret = spear_shirq_register(&shirq_ras1);
326 if (ret)
5fb00f96 327 pr_err("Error registering Shared IRQ\n");
4c18e77f 328 }
70f4c0bf 329}
c5fa4fdc
VK		 330
331static const char * const spear300_dt_board_compat[] = {
332 "st,spear300",
333 "st,spear300-evb",
334 NULL,
335};
336
337static void __init spear300_map_io(void)
338{
339 spear3xx_map_io();
c5fa4fdc
VK		 340}
341
342DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
343 .map_io = spear300_map_io,
344 .init_irq = spear3xx_dt_init_irq,
345 .handle_irq = vic_handle_irq,
346 .timer = &spear3xx_timer,
347 .init_machine = spear300_dt_init,
348 .restart = spear_restart,
349 .dt_compat = spear300_dt_board_compat,
350MACHINE_END
kernel source for telekom puls (alcatel/mediatek)