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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-shmobile / board-mackerel.c
CommitLineData
920adc75
KM		 1/*
2 * mackerel board support
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on ap4evb
8 * Copyright (C) 2010 Magnus Damm
9 * Copyright (C) 2008 Yoshihiro Shimoda
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 */
12c4309b 24#include <linux/delay.h>
920adc75
KM		 25#include <linux/kernel.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/platform_device.h>
30#include <linux/gpio.h>
31#include <linux/input.h>
32#include <linux/io.h>
1a44d72a 33#include <linux/i2c.h>
d44deb35 34#include <linux/leds.h>
6dff7da2
YG		 35#include <linux/mfd/tmio.h>
36#include <linux/mmc/host.h>
41491b9a 37#include <linux/mmc/sh_mmcif.h>
17e75d82 38#include <linux/mmc/sh_mobile_sdhi.h>
920adc75
KM		 39#include <linux/mtd/mtd.h>
40#include <linux/mtd/partitions.h>
41#include <linux/mtd/physmap.h>
2aab52e8 42#include <linux/mtd/sh_flctl.h>
b5e8d269 43#include <linux/pm_clock.h>
2264c151 44#include <linux/smsc911x.h>
1a44d72a 45#include <linux/sh_intc.h>
cd8ab004 46#include <linux/tca6416_keypad.h>
66ee3bef 47#include <linux/usb/renesas_usbhs.h>
9b742024 48#include <linux/dma-mapping.h>
920adc75 49
12c4309b 50#include <video/sh_mobile_hdmi.h>
11fee467 51#include <video/sh_mobile_lcdc.h>
ae37c8de
MD		 52#include <media/sh_mobile_ceu.h>
53#include <media/soc_camera.h>
54#include <media/soc_camera_platform.h>
1a44d72a 55#include <sound/sh_fsi.h>
af8a2fe1 56#include <sound/simple_card.h>
1a44d72a 57
920adc75 58#include <mach/common.h>
250a2723 59#include <mach/irqs.h>
920adc75
KM		 60#include <mach/sh7372.h>
61
62#include <asm/mach/arch.h>
920adc75
KM		 63#include <asm/mach-types.h>
64
65/*
66 * Address Interface BusWidth note
67 * ------------------------------------------------------------------
68 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON
69 * 0x0800_0000 user area -
70 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF
71 * 0x1400_0000 Ether (LAN9220) 16bit
72 * 0x1600_0000 user area - cannot use with NAND
73 * 0x1800_0000 user area -
74 * 0x1A00_0000 -
75 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit
76 */
77
4b82b689
KM		 78/*
79 * CPU mode
80 *
81 * SW4 | Boot Area| Master | Remarks
82 * 1 | 2 | 3 | 4 | 5 | 6 | 8 | | Processor|
83 * ----+-----+-----+-----+-----+-----+-----+----------+----------+--------------
84 * ON | ON | OFF | ON | ON | OFF | OFF | External | System | External ROM
85 * ON | ON | ON | ON | ON | OFF | OFF | External | System | ROM Debug
86 * ON | ON | X | ON | OFF | OFF | OFF | Built-in | System | ROM Debug
87 * X | OFF | X | X | X | X | OFF | Built-in | System | MaskROM
88 * OFF | X | X | X | X | X | OFF | Built-in | System | MaskROM
89 * X | X | X | OFF | X | X | OFF | Built-in | System | MaskROM
90 * OFF | ON | OFF | X | X | OFF | ON | External | System | Standalone
91 * ON | OFF | OFF | X | X | OFF | ON | External | Realtime | Standalone
92*/
93
94/*
95 * NOR Flash ROM
96 *
97 * SW1 | SW2 | SW7 | NOR Flash ROM
98 * bit1 | bit1 bit2 | bit1 | Memory allocation
99 * ------+------------+------+------------------
100 * OFF | ON OFF | ON | Area 0
101 * OFF | ON OFF | OFF | Area 4
102 */
103
104/*
105 * SMSC 9220
106 *
107 * SW1 SMSC 9220
108 * -----------------------
109 * ON access disable
110 * OFF access enable
111 */
112
113/*
114 * NAND Flash ROM
115 *
116 * SW1 | SW2 | SW7 | NAND Flash ROM
117 * bit1 | bit1 bit2 | bit2 | Memory allocation
118 * ------+------------+------+------------------
119 * OFF | ON OFF | ON | FCE 0
120 * OFF | ON OFF | OFF | FCE 1
121 */
122
123/*
124 * External interrupt pin settings
125 *
126 * IRQX | pin setting | device | level
127 * ------+--------------------+--------------------+-------
128 * IRQ0 | ICR1A.IRQ0SA=0010 | SDHI2 card detect | Low
129 * IRQ6 | ICR1A.IRQ6SA=0011 | Ether(LAN9220) | High
e2a53b7c 130 * IRQ7 | ICR1A.IRQ7SA=0010 | LCD Touch Panel | Low
4b82b689
KM		 131 * IRQ8 | ICR2A.IRQ8SA=0010 | MMC/SD card detect | Low
132 * IRQ9 | ICR2A.IRQ9SA=0010 | KEY(TCA6408) | Low
133 * IRQ21 | ICR4A.IRQ21SA=0011 | Sensor(ADXL345) | High
134 * IRQ22 | ICR4A.IRQ22SA=0011 | Sensor(AK8975) | High
25338f2e 135 */
4b82b689 136
25338f2e
KM		 137/*
138 * USB
139 *
140 * USB0 : CN22 : Function
141 * USB1 : CN31 : Function/Host *1
142 *
143 * J30 (for CN31) *1
144 * ----------+---------------+-------------
145 * 1-2 short | VBUS 5V | Host
146 * open | external VBUS | Function
147 *
66ee3bef
KM		 148 * CAUTION
149 *
150 * renesas_usbhs driver can use external interrupt mode
151 * (which come from USB-PHY) or autonomy mode (it use own interrupt)
152 * for detecting connection/disconnection when Function.
153 * USB will be power OFF while it has been disconnecting
154 * if external interrupt mode, and it is always power ON if autonomy mode,
155 *
156 * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0",
157 * because Touchscreen is using IRQ7-PORT40.
158 * It is impossible to use IRQ7 demux on this board.
25338f2e 159 */
4b82b689 160
6dff7da2
YG		 161/*
162 * SDHI0 (CN12)
163 *
164 * SW56 : OFF
165 *
166 */
167
168/* MMC /SDHI1 (CN7)
169 *
170 * I/O voltage : 1.8v
171 *
172 * Power voltage : 1.8v or 3.3v
41491b9a 173 * J22 : select power voltage *1
6dff7da2
YG		 174 * 1-2 pin : 1.8v
175 * 2-3 pin : 3.3v
176 *
41491b9a
YG		 177 * *1
178 * Please change J22 depends the card to be used.
179 * MMC's OCR field set to support either voltage for the card inserted.
180 *
6dff7da2
YG		 181 * SW1 | SW33
182 * | bit1 | bit2 | bit3 | bit4
183 * -------------+------+------+------+-------
2150dace
SH		 184 * MMC0 OFF | OFF | X | ON | X (Use MMCIF)
185 * SDHI1 OFF | ON | X | OFF | X (Use MFD_SH_MOBILE_SDHI)
6dff7da2
YG		 186 *
187 */
188
189/*
190 * SDHI2 (CN23)
191 *
192 * microSD card sloct
193 *
194 */
195
6d9b7dd0
KM		 196/*
197 * FSI - AK4642
198 *
199 * it needs amixer settings for playing
200 *
201 * amixer set "Headphone" on
202 * amixer set "HPOUTL Mixer DACH" on
203 * amixer set "HPOUTR Mixer DACH" on
204 */
205
1a44d72a
KM		 206/*
207 * FIXME !!
208 *
209 * gpio_no_direction
66ee3bef 210 * gpio_pull_down
1a44d72a
KM		 211 * are quick_hack.
212 *
213 * current gpio frame work doesn't have
214 * the method to control only pull up/down/free.
215 * this function should be replaced by correct gpio function
216 */
217static void __init gpio_no_direction(u32 addr)
218{
219 __raw_writeb(0x00, addr);
220}
221
66ee3bef
KM		 222static void __init gpio_pull_down(u32 addr)
223{
224 u8 data = __raw_readb(addr);
225
226 data &= 0x0F;
227 data |= 0xA0;
228
229 __raw_writeb(data, addr);
230}
231
920adc75
KM		 232/* MTD */
233static struct mtd_partition nor_flash_partitions[] = {
234 {
235 .name = "loader",
236 .offset = 0x00000000,
237 .size = 512 * 1024,
238 .mask_flags = MTD_WRITEABLE,
239 },
240 {
241 .name = "bootenv",
242 .offset = MTDPART_OFS_APPEND,
243 .size = 512 * 1024,
244 .mask_flags = MTD_WRITEABLE,
245 },
246 {
247 .name = "kernel_ro",
248 .offset = MTDPART_OFS_APPEND,
249 .size = 8 * 1024 * 1024,
250 .mask_flags = MTD_WRITEABLE,
251 },
252 {
253 .name = "kernel",
254 .offset = MTDPART_OFS_APPEND,
255 .size = 8 * 1024 * 1024,
256 },
257 {
258 .name = "data",
259 .offset = MTDPART_OFS_APPEND,
260 .size = MTDPART_SIZ_FULL,
261 },
262};
263
264static struct physmap_flash_data nor_flash_data = {
265 .width = 2,
266 .parts = nor_flash_partitions,
267 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
268};
269
270static struct resource nor_flash_resources[] = {
271 [0] = {
487881c0
MD		 272 .start = 0x20000000, /* CS0 shadow instead of regular CS0 */
273 .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
920adc75
KM		 274 .flags = IORESOURCE_MEM,
275 }
276};
277
278static struct platform_device nor_flash_device = {
279 .name = "physmap-flash",
280 .dev = {
281 .platform_data = &nor_flash_data,
282 },
283 .num_resources = ARRAY_SIZE(nor_flash_resources),
284 .resource = nor_flash_resources,
285};
286
2264c151
KM		 287/* SMSC */
288static struct resource smc911x_resources[] = {
289 {
290 .start = 0x14000000,
291 .end = 0x16000000 - 1,
292 .flags = IORESOURCE_MEM,
293 }, {
294 .start = evt2irq(0x02c0) /* IRQ6A */,
295 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
296 },
297};
298
299static struct smsc911x_platform_config smsc911x_info = {
300 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
301 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
302 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
303};
304
305static struct platform_device smc911x_device = {
306 .name = "smsc911x",
307 .id = -1,
308 .num_resources = ARRAY_SIZE(smc911x_resources),
309 .resource = smc911x_resources,
310 .dev = {
311 .platform_data = &smsc911x_info,
312 },
313};
314
1c7fcbed
DHG		 315/* MERAM */
316static struct sh_mobile_meram_info mackerel_meram_info = {
317 .addr_mode = SH_MOBILE_MERAM_MODE1,
318};
319
320static struct resource meram_resources[] = {
321 [0] = {
e71504d5 322 .name = "regs",
1c7fcbed 323 .start = 0xe8000000,
e71504d5
LP		 324 .end = 0xe807ffff,
325 .flags = IORESOURCE_MEM,
326 },
327 [1] = {
328 .name = "meram",
329 .start = 0xe8080000,
1c7fcbed
DHG		 330 .end = 0xe81fffff,
331 .flags = IORESOURCE_MEM,
332 },
333};
334
335static struct platform_device meram_device = {
336 .name = "sh_mobile_meram",
337 .id = 0,
338 .num_resources = ARRAY_SIZE(meram_resources),
339 .resource = meram_resources,
340 .dev = {
341 .platform_data = &mackerel_meram_info,
342 },
343};
344
11fee467
KM		 345/* LCDC */
346static struct fb_videomode mackerel_lcdc_modes[] = {
347 {
348 .name = "WVGA Panel",
349 .xres = 800,
350 .yres = 480,
351 .left_margin = 220,
352 .right_margin = 110,
353 .hsync_len = 70,
354 .upper_margin = 20,
355 .lower_margin = 5,
356 .vsync_len = 5,
357 .sync = 0,
358 },
359};
360
018882aa 361static int mackerel_set_brightness(int brightness)
1fbdfcde
MD		 362{
363 gpio_set_value(GPIO_PORT31, brightness);
364
365 return 0;
366}
367
018882aa 368static int mackerel_get_brightness(void)
1fbdfcde
MD		 369{
370 return gpio_get_value(GPIO_PORT31);
371}
372
c241a0e0 373static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
1c7fcbed 374 .icb[0] = {
1c7fcbed
DHG		 375 .meram_size = 0x40,
376 },
377 .icb[1] = {
1c7fcbed
DHG		 378 .meram_size = 0x40,
379 },
380};
381
11fee467 382static struct sh_mobile_lcdc_info lcdc_info = {
1c7fcbed 383 .meram_dev = &mackerel_meram_info,
11fee467
KM		 384 .clock_source = LCDC_CLK_BUS,
385 .ch[0] = {
386 .chan = LCDC_CHAN_MAINLCD,
edd153a3 387 .fourcc = V4L2_PIX_FMT_RGB565,
93ff2598
LP		 388 .lcd_modes = mackerel_lcdc_modes,
389 .num_modes = ARRAY_SIZE(mackerel_lcdc_modes),
11fee467 390 .interface_type = RGB24,
2c34e939 391 .clock_divider = 3,
11fee467 392 .flags = 0,
afaad83b
LP		 393 .panel_cfg = {
394 .width = 152,
395 .height = 91,
1fbdfcde
MD		 396 },
397 .bl_info = {
398 .name = "sh_mobile_lcdc_bl",
399 .max_brightness = 1,
43059b0f
LP		 400 .set_brightness = mackerel_set_brightness,
401 .get_brightness = mackerel_get_brightness,
1fbdfcde 402 },
1c7fcbed 403 .meram_cfg = &lcd_meram_cfg,
11fee467
KM		 404 }
405};
406
407static struct resource lcdc_resources[] = {
408 [0] = {
409 .name = "LCDC",
410 .start = 0xfe940000,
411 .end = 0xfe943fff,
412 .flags = IORESOURCE_MEM,
413 },
414 [1] = {
415 .start = intcs_evt2irq(0x580),
416 .flags = IORESOURCE_IRQ,
417 },
418};
419
420static struct platform_device lcdc_device = {
421 .name = "sh_mobile_lcdc_fb",
422 .num_resources = ARRAY_SIZE(lcdc_resources),
423 .resource = lcdc_resources,
424 .dev = {
425 .platform_data = &lcdc_info,
426 .coherent_dma_mask = ~0,
427 },
428};
429
a1022adb 430/* HDMI */
a1022adb 431static struct sh_mobile_hdmi_info hdmi_info = {
a1022adb
LP		 432 .flags = HDMI_SND_SRC_SPDIF,
433};
434
435static struct resource hdmi_resources[] = {
436 [0] = {
437 .name = "HDMI",
438 .start = 0xe6be0000,
439 .end = 0xe6be00ff,
440 .flags = IORESOURCE_MEM,
441 },
442 [1] = {
443 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
444 .start = evt2irq(0x17e0),
445 .flags = IORESOURCE_IRQ,
446 },
447};
448
449static struct platform_device hdmi_device = {
450 .name = "sh-mobile-hdmi",
451 .num_resources = ARRAY_SIZE(hdmi_resources),
452 .resource = hdmi_resources,
453 .id = -1,
454 .dev = {
455 .platform_data = &hdmi_info,
456 },
457};
458
c241a0e0 459static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
1c7fcbed 460 .icb[0] = {
1c7fcbed
DHG		 461 .meram_size = 0x100,
462 },
463 .icb[1] = {
1c7fcbed
DHG		 464 .meram_size = 0x100,
465 },
466};
a1022adb 467
12c4309b 468static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
1c7fcbed 469 .meram_dev = &mackerel_meram_info,
12c4309b
KM		 470 .clock_source = LCDC_CLK_EXTERNAL,
471 .ch[0] = {
472 .chan = LCDC_CHAN_MAINLCD,
edd153a3 473 .fourcc = V4L2_PIX_FMT_RGB565,
12c4309b
KM		 474 .interface_type = RGB24,
475 .clock_divider = 1,
476 .flags = LCDC_FLAGS_DWPOL,
1c7fcbed 477 .meram_cfg = &hdmi_meram_cfg,
a1022adb 478 .tx_dev = &hdmi_device,
12c4309b
KM		 479 }
480};
481
482static struct resource hdmi_lcdc_resources[] = {
483 [0] = {
484 .name = "LCDC1",
485 .start = 0xfe944000,
486 .end = 0xfe947fff,
487 .flags = IORESOURCE_MEM,
488 },
489 [1] = {
490 .start = intcs_evt2irq(0x1780),
491 .flags = IORESOURCE_IRQ,
492 },
493};
494
495static struct platform_device hdmi_lcdc_device = {
496 .name = "sh_mobile_lcdc_fb",
497 .num_resources = ARRAY_SIZE(hdmi_lcdc_resources),
498 .resource = hdmi_lcdc_resources,
499 .id = 1,
500 .dev = {
501 .platform_data = &hdmi_lcdc_info,
502 .coherent_dma_mask = ~0,
503 },
504};
505
fa063b48
KM		 506static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = {
507 .cpu_daifmt = SND_SOC_DAIFMT_CBM_CFM,
508};
509
510static struct asoc_simple_card_info fsi2_hdmi_info = {
511 .name = "HDMI",
512 .card = "FSI2B-HDMI",
513 .cpu_dai = "fsib-dai",
514 .codec = "sh-mobile-hdmi",
515 .platform = "sh_fsi2",
516 .codec_dai = "sh_mobile_hdmi-hifi",
517 .init = &fsi2_hdmi_init_info,
518};
519
3f25c9cc 520static struct platform_device fsi_hdmi_device = {
fa063b48
KM		 521 .name = "asoc-simple-card",
522 .id = 1,
523 .dev = {
524 .platform_data = &fsi2_hdmi_info,
525 },
3f25c9cc
KM		 526};
527
2ce51f8b 528static void __init hdmi_init_pm_clock(void)
12c4309b
KM		 529{
530 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
531 int ret;
532 long rate;
533
534 if (IS_ERR(hdmi_ick)) {
535 ret = PTR_ERR(hdmi_ick);
536 pr_err("Cannot get HDMI ICK: %d\n", ret);
537 goto out;
538 }
539
540 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
541 if (ret < 0) {
542 pr_err("Cannot set PLLC2 parent: %d, %d users\n",
543 ret, sh7372_pllc2_clk.usecount);
544 goto out;
545 }
546
547 pr_debug("PLLC2 initial frequency %lu\n",
548 clk_get_rate(&sh7372_pllc2_clk));
549
550 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
551 if (rate < 0) {
552 pr_err("Cannot get suitable rate: %ld\n", rate);
553 ret = rate;
554 goto out;
555 }
556
557 ret = clk_set_rate(&sh7372_pllc2_clk, rate);
558 if (ret < 0) {
559 pr_err("Cannot set rate %ld: %d\n", rate, ret);
560 goto out;
561 }
562
12c4309b
KM		 563 pr_debug("PLLC2 set frequency %lu\n", rate);
564
565 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
2ce51f8b 566 if (ret < 0)
12c4309b 567 pr_err("Cannot set HDMI parent: %d\n", ret);
12c4309b
KM		 568
569out:
570 if (!IS_ERR(hdmi_ick))
571 clk_put(hdmi_ick);
12c4309b 572}
12c4309b 573
e2a53b7c
MD		 574/* USBHS0 is connected to CN22 which takes a USB Mini-B plug
575 *
576 * The sh7372 SoC has IRQ7 set aside for USBHS0 hotplug,
577 * but on this particular board IRQ7 is already used by
578 * the touch screen. This leaves us with software polling.
579 */
580#define USBHS0_POLL_INTERVAL (HZ * 5)
581
582struct usbhs_private {
583 unsigned int usbphyaddr;
584 unsigned int usbcrcaddr;
585 struct renesas_usbhs_platform_info info;
586 struct delayed_work work;
587 struct platform_device *pdev;
588};
589
590#define usbhs_get_priv(pdev) \
591 container_of(renesas_usbhs_get_info(pdev), \
592 struct usbhs_private, info)
593
594#define usbhs_is_connected(priv) \
595 (!((1 << 7) & __raw_readw(priv->usbcrcaddr)))
596
597static int usbhs_get_vbus(struct platform_device *pdev)
598{
599 return usbhs_is_connected(usbhs_get_priv(pdev));
600}
601
602static void usbhs_phy_reset(struct platform_device *pdev)
603{
604 struct usbhs_private *priv = usbhs_get_priv(pdev);
605
606 /* init phy */
607 __raw_writew(0x8a0a, priv->usbcrcaddr);
608}
609
610static int usbhs0_get_id(struct platform_device *pdev)
611{
612 return USBHS_GADGET;
613}
614
615static void usbhs0_work_function(struct work_struct *work)
616{
617 struct usbhs_private *priv = container_of(work, struct usbhs_private,
618 work.work);
619
620 renesas_usbhs_call_notify_hotplug(priv->pdev);
621 schedule_delayed_work(&priv->work, USBHS0_POLL_INTERVAL);
622}
623
624static int usbhs0_hardware_init(struct platform_device *pdev)
625{
626 struct usbhs_private *priv = usbhs_get_priv(pdev);
627
628 priv->pdev = pdev;
629 INIT_DELAYED_WORK(&priv->work, usbhs0_work_function);
630 schedule_delayed_work(&priv->work, USBHS0_POLL_INTERVAL);
631 return 0;
632}
633
634static void usbhs0_hardware_exit(struct platform_device *pdev)
635{
636 struct usbhs_private *priv = usbhs_get_priv(pdev);
637
638 cancel_delayed_work_sync(&priv->work);
639}
640
e2a53b7c
MD		 641static struct usbhs_private usbhs0_private = {
642 .usbcrcaddr = 0xe605810c, /* USBCR2 */
643 .info = {
644 .platform_callback = {
645 .hardware_init = usbhs0_hardware_init,
646 .hardware_exit = usbhs0_hardware_exit,
647 .phy_reset = usbhs_phy_reset,
648 .get_id = usbhs0_get_id,
649 .get_vbus = usbhs_get_vbus,
650 },
651 .driver_param = {
652 .buswait_bwait = 4,
fe437561
KM		 653 .d0_tx_id = SHDMA_SLAVE_USB0_TX,
654 .d1_rx_id = SHDMA_SLAVE_USB0_RX,
e2a53b7c
MD		 655 },
656 },
657};
658
659static struct resource usbhs0_resources[] = {
660 [0] = {
661 .name = "USBHS0",
662 .start = 0xe6890000,
663 .end = 0xe68900e6 - 1,
664 .flags = IORESOURCE_MEM,
665 },
666 [1] = {
667 .start = evt2irq(0x1ca0) /* USB0_USB0I0 */,
668 .flags = IORESOURCE_IRQ,
669 },
670};
671
672static struct platform_device usbhs0_device = {
673 .name = "renesas_usbhs",
674 .id = 0,
675 .dev = {
676 .platform_data = &usbhs0_private.info,
677 },
678 .num_resources = ARRAY_SIZE(usbhs0_resources),
679 .resource = usbhs0_resources,
680};
681
682/* USBHS1 is connected to CN31 which takes a USB Mini-AB plug
683 *
684 * Use J30 to select between Host and Function. This setting
685 * can however not be detected by software. Hotplug of USBHS1
686 * is provided via IRQ8.
0ada2da5
KM		 687 *
688 * Current USB1 works as "USB Host".
689 * - set J30 "short"
690 *
691 * If you want to use it as "USB gadget",
692 * - J30 "open"
693 * - modify usbhs1_get_id() USBHS_HOST -> USBHS_GADGET
694 * - add .get_vbus = usbhs_get_vbus in usbhs1_private
e2a53b7c
MD		 695 */
696#define IRQ8 evt2irq(0x0300)
66ee3bef
KM		 697#define USB_PHY_MODE (1 << 4)
698#define USB_PHY_INT_EN ((1 << 3) | (1 << 2))
699#define USB_PHY_ON (1 << 1)
700#define USB_PHY_OFF (1 << 0)
701#define USB_PHY_INT_CLR (USB_PHY_ON | USB_PHY_OFF)
702
66ee3bef
KM		 703static irqreturn_t usbhs1_interrupt(int irq, void *data)
704{
705 struct platform_device *pdev = data;
706 struct usbhs_private *priv = usbhs_get_priv(pdev);
707
708 dev_dbg(&pdev->dev, "%s\n", __func__);
709
710 renesas_usbhs_call_notify_hotplug(pdev);
711
712 /* clear status */
713 __raw_writew(__raw_readw(priv->usbphyaddr) | USB_PHY_INT_CLR,
714 priv->usbphyaddr);
715
716 return IRQ_HANDLED;
717}
718
719static int usbhs1_hardware_init(struct platform_device *pdev)
720{
721 struct usbhs_private *priv = usbhs_get_priv(pdev);
722 int ret;
723
66ee3bef
KM		 724 /* clear interrupt status */
725 __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
726
e2a53b7c 727 ret = request_irq(IRQ8, usbhs1_interrupt, IRQF_TRIGGER_HIGH,
66ee3bef
KM		 728 dev_name(&pdev->dev), pdev);
729 if (ret) {
730 dev_err(&pdev->dev, "request_irq err\n");
731 return ret;
732 }
733
734 /* enable USB phy interrupt */
735 __raw_writew(USB_PHY_MODE | USB_PHY_INT_EN, priv->usbphyaddr);
736
737 return 0;
738}
739
740static void usbhs1_hardware_exit(struct platform_device *pdev)
741{
742 struct usbhs_private *priv = usbhs_get_priv(pdev);
743
744 /* clear interrupt status */
745 __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
746
e2a53b7c 747 free_irq(IRQ8, pdev);
66ee3bef
KM		 748}
749
05a7929f
KM		 750static int usbhs1_get_id(struct platform_device *pdev)
751{
0ada2da5 752 return USBHS_HOST;
05a7929f
KM		 753}
754
66ee3bef
KM		 755static u32 usbhs1_pipe_cfg[] = {
756 USB_ENDPOINT_XFER_CONTROL,
757 USB_ENDPOINT_XFER_ISOC,
758 USB_ENDPOINT_XFER_ISOC,
759 USB_ENDPOINT_XFER_BULK,
760 USB_ENDPOINT_XFER_BULK,
761 USB_ENDPOINT_XFER_BULK,
762 USB_ENDPOINT_XFER_INT,
763 USB_ENDPOINT_XFER_INT,
764 USB_ENDPOINT_XFER_INT,
765 USB_ENDPOINT_XFER_BULK,
766 USB_ENDPOINT_XFER_BULK,
767 USB_ENDPOINT_XFER_BULK,
768 USB_ENDPOINT_XFER_BULK,
769 USB_ENDPOINT_XFER_BULK,
770 USB_ENDPOINT_XFER_BULK,
771 USB_ENDPOINT_XFER_BULK,
772};
773
774static struct usbhs_private usbhs1_private = {
e2a53b7c
MD		 775 .usbphyaddr = 0xe60581e2, /* USBPHY1INTAP */
776 .usbcrcaddr = 0xe6058130, /* USBCR4 */
66ee3bef
KM		 777 .info = {
778 .platform_callback = {
779 .hardware_init = usbhs1_hardware_init,
780 .hardware_exit = usbhs1_hardware_exit,
05a7929f 781 .get_id = usbhs1_get_id,
e2a53b7c 782 .phy_reset = usbhs_phy_reset,
66ee3bef
KM		 783 },
784 .driver_param = {
785 .buswait_bwait = 4,
f427eb64 786 .has_otg = 1,
66ee3bef
KM		 787 .pipe_type = usbhs1_pipe_cfg,
788 .pipe_size = ARRAY_SIZE(usbhs1_pipe_cfg),
fe437561
KM		 789 .d0_tx_id = SHDMA_SLAVE_USB1_TX,
790 .d1_rx_id = SHDMA_SLAVE_USB1_RX,
66ee3bef
KM		 791 },
792 },
793};
794
795static struct resource usbhs1_resources[] = {
796 [0] = {
e2a53b7c
MD		 797 .name = "USBHS1",
798 .start = 0xe68b0000,
799 .end = 0xe68b00e6 - 1,
66ee3bef
KM		 800 .flags = IORESOURCE_MEM,
801 },
802 [1] = {
803 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
804 .flags = IORESOURCE_IRQ,
805 },
806};
807
808static struct platform_device usbhs1_device = {
809 .name = "renesas_usbhs",
810 .id = 1,
811 .dev = {
812 .platform_data = &usbhs1_private.info,
813 },
814 .num_resources = ARRAY_SIZE(usbhs1_resources),
815 .resource = usbhs1_resources,
816};
817
d44deb35
KM		 818/* LED */
819static struct gpio_led mackerel_leds[] = {
820 {
821 .name = "led0",
822 .gpio = GPIO_PORT0,
823 .default_state = LEDS_GPIO_DEFSTATE_ON,
824 },
825 {
826 .name = "led1",
827 .gpio = GPIO_PORT1,
828 .default_state = LEDS_GPIO_DEFSTATE_ON,
829 },
830 {
831 .name = "led2",
832 .gpio = GPIO_PORT2,
833 .default_state = LEDS_GPIO_DEFSTATE_ON,
834 },
835 {
836 .name = "led3",
837 .gpio = GPIO_PORT159,
838 .default_state = LEDS_GPIO_DEFSTATE_ON,
839 }
840};
841
842static struct gpio_led_platform_data mackerel_leds_pdata = {
843 .leds = mackerel_leds,
844 .num_leds = ARRAY_SIZE(mackerel_leds),
845};
846
847static struct platform_device leds_device = {
848 .name = "leds-gpio",
849 .id = 0,
850 .dev = {
851 .platform_data = &mackerel_leds_pdata,
852 },
853};
854
1a44d72a
KM		 855/* FSI */
856#define IRQ_FSI evt2irq(0x1840)
98d27b8a
KM		 857static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
858{
859 int ret;
860
861 if (rate <= 0)
862 return 0;
863
864 if (!enable) {
865 clk_disable(clk);
866 return 0;
867 }
868
869 ret = clk_set_rate(clk, clk_round_rate(clk, rate));
870 if (ret < 0)
871 return ret;
872
873 return clk_enable(clk);
874}
875
fec691e7 876static int fsi_b_set_rate(struct device *dev, int rate, int enable)
98d27b8a
KM		 877{
878 struct clk *fsib_clk;
879 struct clk *fdiv_clk = &sh7372_fsidivb_clk;
880 long fsib_rate = 0;
881 long fdiv_rate = 0;
882 int ackmd_bpfmd;
883 int ret;
884
98d27b8a
KM		 885 /* clock start */
886 switch (rate) {
887 case 44100:
888 fsib_rate = rate * 256;
889 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
890 break;
891 case 48000:
892 fsib_rate = 85428000; /* around 48kHz x 256 x 7 */
893 fdiv_rate = rate * 256;
894 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
895 break;
896 default:
897 pr_err("unsupported rate in FSI2 port B\n");
898 return -EINVAL;
899 }
900
901 /* FSI B setting */
902 fsib_clk = clk_get(dev, "ickb");
903 if (IS_ERR(fsib_clk))
904 return -EIO;
905
906 /* fsib */
907 ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
908 if (ret < 0)
909 goto fsi_set_rate_end;
910
911 /* FSI DIV */
912 ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
913 if (ret < 0) {
914 /* disable FSI B */
915 if (enable)
916 __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
917 goto fsi_set_rate_end;
918 }
919
920 ret = ackmd_bpfmd;
921
922fsi_set_rate_end:
923 clk_put(fsib_clk);
924 return ret;
925}
926
1a44d72a 927static struct sh_fsi_platform_info fsi_info = {
fec691e7
KM		 928 .port_a = {
929 .flags = SH_FSI_BRS_INV,
c650a1f4
KM		 930 .tx_id = SHDMA_SLAVE_FSIA_TX,
931 .rx_id = SHDMA_SLAVE_FSIA_RX,
fec691e7
KM		 932 },
933 .port_b = {
934 .flags = SH_FSI_BRS_INV |
98d27b8a
KM		 935 SH_FSI_BRM_INV |
936 SH_FSI_LRS_INV |
f17c13ca 937 SH_FSI_FMT_SPDIF,
fec691e7
KM		 938 .set_rate = fsi_b_set_rate,
939 }
1a44d72a
KM		 940};
941
942static struct resource fsi_resources[] = {
943 [0] = {
c650a1f4
KM		 944 /* we need 0xFE1F0000 to access DMA
945 * instead of 0xFE3C0000 */
1a44d72a 946 .name = "FSI",
c650a1f4
KM		 947 .start = 0xFE1F0000,
948 .end = 0xFE1F0400 - 1,
1a44d72a
KM		 949 .flags = IORESOURCE_MEM,
950 },
951 [1] = {
952 .start = IRQ_FSI,
953 .flags = IORESOURCE_IRQ,
954 },
955};
956
957static struct platform_device fsi_device = {
958 .name = "sh_fsi2",
959 .id = -1,
960 .num_resources = ARRAY_SIZE(fsi_resources),
961 .resource = fsi_resources,
962 .dev = {
963 .platform_data = &fsi_info,
964 },
965};
966
af8a2fe1
KM		 967static struct asoc_simple_dai_init_info fsi2_ak4643_init_info = {
968 .fmt = SND_SOC_DAIFMT_LEFT_J,
969 .codec_daifmt = SND_SOC_DAIFMT_CBM_CFM,
970 .cpu_daifmt = SND_SOC_DAIFMT_CBS_CFS,
971 .sysclk = 11289600,
972};
973
974static struct asoc_simple_card_info fsi2_ak4643_info = {
45f31216
KM		 975 .name = "AK4643",
976 .card = "FSI2A-AK4643",
977 .cpu_dai = "fsia-dai",
978 .codec = "ak4642-codec.0-0013",
979 .platform = "sh_fsi2",
af8a2fe1
KM		 980 .codec_dai = "ak4642-hifi",
981 .init = &fsi2_ak4643_init_info,
45f31216
KM		 982};
983
1a44d72a 984static struct platform_device fsi_ak4643_device = {
af8a2fe1 985 .name = "asoc-simple-card",
45f31216
KM		 986 .dev = {
987 .platform_data = &fsi2_ak4643_info,
988 },
1a44d72a 989};
d44deb35 990
2aab52e8
BH		 991/* FLCTL */
992static struct mtd_partition nand_partition_info[] = {
993 {
994 .name = "system",
995 .offset = 0,
996 .size = 128 * 1024 * 1024,
997 },
998 {
999 .name = "userdata",
1000 .offset = MTDPART_OFS_APPEND,
1001 .size = 256 * 1024 * 1024,
1002 },
1003 {
1004 .name = "cache",
1005 .offset = MTDPART_OFS_APPEND,
1006 .size = 128 * 1024 * 1024,
1007 },
1008};
1009
1010static struct resource nand_flash_resources[] = {
1011 [0] = {
1012 .start = 0xe6a30000,
1013 .end = 0xe6a3009b,
1014 .flags = IORESOURCE_MEM,
1015 }
1016};
1017
1018static struct sh_flctl_platform_data nand_flash_data = {
1019 .parts = nand_partition_info,
1020 .nr_parts = ARRAY_SIZE(nand_partition_info),
1021 .flcmncr_val = CLK_16B_12L_4H | TYPESEL_SET
1022 | SHBUSSEL | SEL_16BIT | SNAND_E,
1023 .use_holden = 1,
1024};
1025
1026static struct platform_device nand_flash_device = {
1027 .name = "sh_flctl",
1028 .resource = nand_flash_resources,
1029 .num_resources = ARRAY_SIZE(nand_flash_resources),
1030 .dev = {
1031 .platform_data = &nand_flash_data,
1032 },
1033};
1034
6dff7da2
YG		 1035/*
1036 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
1037 * connected to GPIO A22 of SH7372 (GPIO_PORT41).
1038 */
1039static int slot_cn7_get_cd(struct platform_device *pdev)
1040{
ceb50f33 1041 return !gpio_get_value(GPIO_PORT41);
6dff7da2
YG		 1042}
1043
1044/* SDHI0 */
1045static struct sh_mobile_sdhi_info sdhi0_info = {
1046 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
1047 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
2b3e38c4 1048 .tmio_flags = TMIO_MMC_USE_GPIO_CD,
da97da73 1049 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
2b3e38c4 1050 .cd_gpio = GPIO_PORT172,
6dff7da2
YG		 1051};
1052
1053static struct resource sdhi0_resources[] = {
1054 [0] = {
1055 .name = "SDHI0",
1056 .start = 0xe6850000,
31d31fe7 1057 .end = 0xe68500ff,
6dff7da2
YG		 1058 .flags = IORESOURCE_MEM,
1059 },
1060 [1] = {
2007aea1
SH		 1061 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
1062 .flags = IORESOURCE_IRQ,
1063 },
1064 [2] = {
1065 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
1066 .flags = IORESOURCE_IRQ,
1067 },
1068 [3] = {
1069 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
6dff7da2
YG		 1070 .flags = IORESOURCE_IRQ,
1071 },
1072};
1073
1074static struct platform_device sdhi0_device = {
1075 .name = "sh_mobile_sdhi",
1076 .num_resources = ARRAY_SIZE(sdhi0_resources),
1077 .resource = sdhi0_resources,
1078 .id = 0,
1079 .dev = {
1080 .platform_data = &sdhi0_info,
1081 },
1082};
1083
5bcd7517 1084#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
6dff7da2
YG		 1085/* SDHI1 */
1086static struct sh_mobile_sdhi_info sdhi1_info = {
1087 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
1088 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
1089 .tmio_ocr_mask = MMC_VDD_165_195,
1090 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
da97da73 1091 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
6dff7da2
YG		 1092 MMC_CAP_NEEDS_POLL,
1093 .get_cd = slot_cn7_get_cd,
1094};
1095
1096static struct resource sdhi1_resources[] = {
1097 [0] = {
1098 .name = "SDHI1",
1099 .start = 0xe6860000,
31d31fe7 1100 .end = 0xe68600ff,
6dff7da2
YG		 1101 .flags = IORESOURCE_MEM,
1102 },
1103 [1] = {
cb2ccc32 1104 .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
2007aea1
SH		 1105 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
1106 .flags = IORESOURCE_IRQ,
1107 },
1108 [2] = {
cb2ccc32 1109 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
2007aea1
SH		 1110 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
1111 .flags = IORESOURCE_IRQ,
1112 },
1113 [3] = {
cb2ccc32 1114 .name = SH_MOBILE_SDHI_IRQ_SDIO,
2007aea1 1115 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
6dff7da2
YG		 1116 .flags = IORESOURCE_IRQ,
1117 },
1118};
1119
1120static struct platform_device sdhi1_device = {
1121 .name = "sh_mobile_sdhi",
1122 .num_resources = ARRAY_SIZE(sdhi1_resources),
1123 .resource = sdhi1_resources,
1124 .id = 1,
1125 .dev = {
1126 .platform_data = &sdhi1_info,
1127 },
1128};
41491b9a 1129#endif
6dff7da2 1130
da5d1f4c
YG		 1131/*
1132 * The card detect pin of the top SD/MMC slot (CN23) is active low and is
1133 * connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162).
1134 */
1135static int slot_cn23_get_cd(struct platform_device *pdev)
1136{
1137 return !gpio_get_value(GPIO_PORT162);
1138}
1139
6dff7da2
YG		 1140/* SDHI2 */
1141static struct sh_mobile_sdhi_info sdhi2_info = {
1142 .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX,
1143 .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX,
1144 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
da97da73 1145 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
6dff7da2 1146 MMC_CAP_NEEDS_POLL,
da5d1f4c 1147 .get_cd = slot_cn23_get_cd,
6dff7da2
YG		 1148};
1149
1150static struct resource sdhi2_resources[] = {
1151 [0] = {
1152 .name = "SDHI2",
1153 .start = 0xe6870000,
31d31fe7 1154 .end = 0xe68700ff,
6dff7da2
YG		 1155 .flags = IORESOURCE_MEM,
1156 },
1157 [1] = {
cb2ccc32 1158 .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
2007aea1
SH		 1159 .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */
1160 .flags = IORESOURCE_IRQ,
1161 },
1162 [2] = {
cb2ccc32 1163 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
2007aea1
SH		 1164 .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
1165 .flags = IORESOURCE_IRQ,
1166 },
1167 [3] = {
cb2ccc32 1168 .name = SH_MOBILE_SDHI_IRQ_SDIO,
2007aea1 1169 .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
6dff7da2
YG		 1170 .flags = IORESOURCE_IRQ,
1171 },
1172};
1173
1174static struct platform_device sdhi2_device = {
1175 .name = "sh_mobile_sdhi",
1176 .num_resources = ARRAY_SIZE(sdhi2_resources),
1177 .resource = sdhi2_resources,
1178 .id = 2,
1179 .dev = {
1180 .platform_data = &sdhi2_info,
1181 },
1182};
1183
41491b9a
YG		 1184/* SH_MMCIF */
1185static struct resource sh_mmcif_resources[] = {
1186 [0] = {
1187 .name = "MMCIF",
1188 .start = 0xE6BD0000,
1189 .end = 0xE6BD00FF,
1190 .flags = IORESOURCE_MEM,
1191 },
1192 [1] = {
1193 /* MMC ERR */
1194 .start = evt2irq(0x1ac0),
1195 .flags = IORESOURCE_IRQ,
1196 },
1197 [2] = {
1198 /* MMC NOR */
1199 .start = evt2irq(0x1ae0),
1200 .flags = IORESOURCE_IRQ,
1201 },
1202};
1203
1204static struct sh_mmcif_plat_data sh_mmcif_plat = {
1205 .sup_pclk = 0,
1206 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
1207 .caps = MMC_CAP_4_BIT_DATA |
1208 MMC_CAP_8_BIT_DATA |
1209 MMC_CAP_NEEDS_POLL,
1210 .get_cd = slot_cn7_get_cd,
d5bb386d
GL		 1211 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
1212 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
41491b9a
YG		 1213};
1214
1215static struct platform_device sh_mmcif_device = {
1216 .name = "sh_mmcif",
1217 .id = 0,
1218 .dev = {
1219 .dma_mask = NULL,
1220 .coherent_dma_mask = 0xffffffff,
1221 .platform_data = &sh_mmcif_plat,
1222 },
1223 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
1224 .resource = sh_mmcif_resources,
1225};
1226
ae37c8de 1227
7dfff953
GL		 1228static int mackerel_camera_add(struct soc_camera_device *icd);
1229static void mackerel_camera_del(struct soc_camera_device *icd);
ae37c8de
MD		 1230
1231static int camera_set_capture(struct soc_camera_platform_info *info,
1232 int enable)
1233{
1234 return 0; /* camera sensor always enabled */
1235}
1236
1237static struct soc_camera_platform_info camera_info = {
1238 .format_name = "UYVY",
1239 .format_depth = 16,
1240 .format = {
1241 .code = V4L2_MBUS_FMT_UYVY8_2X8,
1242 .colorspace = V4L2_COLORSPACE_SMPTE170M,
1243 .field = V4L2_FIELD_NONE,
1244 .width = 640,
1245 .height = 480,
1246 },
d1e87ed7
GL		 1247 .mbus_param = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
1248 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1249 V4L2_MBUS_DATA_ACTIVE_HIGH,
1250 .mbus_type = V4L2_MBUS_PARALLEL,
ae37c8de
MD		 1251 .set_capture = camera_set_capture,
1252};
1253
1254static struct soc_camera_link camera_link = {
1255 .bus_id = 0,
1256 .add_device = mackerel_camera_add,
1257 .del_device = mackerel_camera_del,
1258 .module_name = "soc_camera_platform",
1259 .priv = &camera_info,
1260};
1261
86a73144
GL		 1262static struct platform_device *camera_device;
1263
1264static void mackerel_camera_release(struct device *dev)
ae37c8de 1265{
86a73144 1266 soc_camera_platform_release(&camera_device);
ae37c8de
MD		 1267}
1268
7dfff953 1269static int mackerel_camera_add(struct soc_camera_device *icd)
ae37c8de 1270{
7dfff953 1271 return soc_camera_platform_add(icd, &camera_device, &camera_link,
86a73144 1272 mackerel_camera_release, 0);
ae37c8de
MD		 1273}
1274
7dfff953 1275static void mackerel_camera_del(struct soc_camera_device *icd)
ae37c8de 1276{
7dfff953 1277 soc_camera_platform_del(icd, camera_device, &camera_link);
ae37c8de
MD		 1278}
1279
1280static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
1281 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
ef8f41ff
GL		 1282 .max_width = 8188,
1283 .max_height = 8188,
ae37c8de
MD		 1284};
1285
1286static struct resource ceu_resources[] = {
1287 [0] = {
1288 .name = "CEU",
1289 .start = 0xfe910000,
1290 .end = 0xfe91009f,
1291 .flags = IORESOURCE_MEM,
1292 },
1293 [1] = {
1294 .start = intcs_evt2irq(0x880),
1295 .flags = IORESOURCE_IRQ,
1296 },
1297 [2] = {
1298 /* place holder for contiguous memory */
1299 },
1300};
1301
1302static struct platform_device ceu_device = {
1303 .name = "sh_mobile_ceu",
1304 .id = 0, /* "ceu0" clock */
1305 .num_resources = ARRAY_SIZE(ceu_resources),
1306 .resource = ceu_resources,
1307 .dev = {
05a5f01c
GL		 1308 .platform_data = &sh_mobile_ceu_info,
1309 .coherent_dma_mask = 0xffffffff,
ae37c8de
MD		 1310 },
1311};
1312
1313static struct platform_device mackerel_camera = {
1314 .name = "soc-camera-pdrv",
1315 .id = 0,
1316 .dev = {
1317 .platform_data = &camera_link,
1318 },
1319};
1320
920adc75
KM		 1321static struct platform_device *mackerel_devices[] __initdata = {
1322 &nor_flash_device,
2264c151 1323 &smc911x_device,
11fee467 1324 &lcdc_device,
66ee3bef 1325 &usbhs1_device,
5a568552 1326 &usbhs0_device,
d44deb35 1327 &leds_device,
1a44d72a
KM		 1328 &fsi_device,
1329 &fsi_ak4643_device,
3f25c9cc 1330 &fsi_hdmi_device,
2aab52e8 1331 &nand_flash_device,
6dff7da2 1332 &sdhi0_device,
5bcd7517 1333#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
6dff7da2 1334 &sdhi1_device,
41491b9a 1335#endif
6dff7da2 1336 &sdhi2_device,
41491b9a 1337 &sh_mmcif_device,
ae37c8de
MD		 1338 &ceu_device,
1339 &mackerel_camera,
12c4309b 1340 &hdmi_device,
a1022adb 1341 &hdmi_lcdc_device,
1c7fcbed 1342 &meram_device,
1a44d72a
KM		 1343};
1344
cd8ab004
TS		 1345/* Keypad Initialization */
1346#define KEYPAD_BUTTON(ev_type, ev_code, act_low) \
1347{ \
1348 .type = ev_type, \
1349 .code = ev_code, \
1350 .active_low = act_low, \
1351}
1352
1353#define KEYPAD_BUTTON_LOW(event_code) KEYPAD_BUTTON(EV_KEY, event_code, 1)
1354
1355static struct tca6416_button mackerel_gpio_keys[] = {
1356 KEYPAD_BUTTON_LOW(KEY_HOME),
1357 KEYPAD_BUTTON_LOW(KEY_MENU),
1358 KEYPAD_BUTTON_LOW(KEY_BACK),
1359 KEYPAD_BUTTON_LOW(KEY_POWER),
1360};
1361
1362static struct tca6416_keys_platform_data mackerel_tca6416_keys_info = {
1363 .buttons = mackerel_gpio_keys,
1364 .nbuttons = ARRAY_SIZE(mackerel_gpio_keys),
1365 .rep = 1,
1366 .use_polling = 0,
1367 .pinmask = 0x000F,
1368};
1369
1a44d72a 1370/* I2C */
6ae1e19d 1371#define IRQ7 evt2irq(0x02e0)
cd8ab004
TS		 1372#define IRQ9 evt2irq(0x0320)
1373
1a44d72a
KM		 1374static struct i2c_board_info i2c0_devices[] = {
1375 {
1376 I2C_BOARD_INFO("ak4643", 0x13),
1377 },
cd8ab004
TS		 1378 /* Keypad */
1379 {
1380 I2C_BOARD_INFO("tca6408-keys", 0x20),
1381 .platform_data = &mackerel_tca6416_keys_info,
1382 .irq = IRQ9,
1383 },
6ae1e19d
TS		 1384 /* Touchscreen */
1385 {
1386 I2C_BOARD_INFO("st1232-ts", 0x55),
1387 .irq = IRQ7,
1388 },
920adc75
KM		 1389};
1390
80f1dc7c
TS		 1391#define IRQ21 evt2irq(0x32a0)
1392
1393static struct i2c_board_info i2c1_devices[] = {
1394 /* Accelerometer */
1395 {
1396 I2C_BOARD_INFO("adxl34x", 0x53),
1397 .irq = IRQ21,
1398 },
1399};
1400
1a44d72a
KM		 1401#define GPIO_PORT9CR 0xE6051009
1402#define GPIO_PORT10CR 0xE605100A
e2a53b7c 1403#define GPIO_PORT167CR 0xE60520A7
66ee3bef 1404#define GPIO_PORT168CR 0xE60520A8
12c4309b 1405#define SRCR4 0xe61580bc
98d27b8a 1406#define USCCR1 0xE6058144
920adc75
KM		 1407static void __init mackerel_init(void)
1408{
12c4309b 1409 u32 srcr4;
98d27b8a 1410 struct clk *clk;
12c4309b 1411
12bb16d2
MD		 1412 /* External clock source */
1413 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1414
920adc75
KM		 1415 sh7372_pinmux_init();
1416
1417 /* enable SCIFA0 */
1418 gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
1419 gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
1420
2264c151
KM		 1421 /* enable SMSC911X */
1422 gpio_request(GPIO_FN_CS5A, NULL);
1423 gpio_request(GPIO_FN_IRQ6_39, NULL);
1424
11fee467 1425 /* LCDC */
eb87e677
KM		 1426 gpio_request(GPIO_FN_LCDD23, NULL);
1427 gpio_request(GPIO_FN_LCDD22, NULL);
1428 gpio_request(GPIO_FN_LCDD21, NULL);
1429 gpio_request(GPIO_FN_LCDD20, NULL);
1430 gpio_request(GPIO_FN_LCDD19, NULL);
1431 gpio_request(GPIO_FN_LCDD18, NULL);
11fee467
KM		 1432 gpio_request(GPIO_FN_LCDD17, NULL);
1433 gpio_request(GPIO_FN_LCDD16, NULL);
1434 gpio_request(GPIO_FN_LCDD15, NULL);
1435 gpio_request(GPIO_FN_LCDD14, NULL);
1436 gpio_request(GPIO_FN_LCDD13, NULL);
1437 gpio_request(GPIO_FN_LCDD12, NULL);
1438 gpio_request(GPIO_FN_LCDD11, NULL);
1439 gpio_request(GPIO_FN_LCDD10, NULL);
1440 gpio_request(GPIO_FN_LCDD9, NULL);
1441 gpio_request(GPIO_FN_LCDD8, NULL);
1442 gpio_request(GPIO_FN_LCDD7, NULL);
1443 gpio_request(GPIO_FN_LCDD6, NULL);
1444 gpio_request(GPIO_FN_LCDD5, NULL);
1445 gpio_request(GPIO_FN_LCDD4, NULL);
1446 gpio_request(GPIO_FN_LCDD3, NULL);
1447 gpio_request(GPIO_FN_LCDD2, NULL);
1448 gpio_request(GPIO_FN_LCDD1, NULL);
1449 gpio_request(GPIO_FN_LCDD0, NULL);
1450 gpio_request(GPIO_FN_LCDDISP, NULL);
1451 gpio_request(GPIO_FN_LCDDCK, NULL);
1452
1453 gpio_request(GPIO_PORT31, NULL); /* backlight */
1fbdfcde 1454 gpio_direction_output(GPIO_PORT31, 0); /* off by default */
11fee467
KM		 1455
1456 gpio_request(GPIO_PORT151, NULL); /* LCDDON */
1457 gpio_direction_output(GPIO_PORT151, 1);
1458
e2a53b7c
MD		 1459 /* USBHS0 */
1460 gpio_request(GPIO_FN_VBUS0_0, NULL);
1461 gpio_pull_down(GPIO_PORT168CR); /* VBUS0_0 pull down */
1462
1463 /* USBHS1 */
1464 gpio_request(GPIO_FN_VBUS0_1, NULL);
1465 gpio_pull_down(GPIO_PORT167CR); /* VBUS0_1 pull down */
1466 gpio_request(GPIO_FN_IDIN_1_113, NULL);
1467
1a44d72a
KM		 1468 /* enable FSI2 port A (ak4643) */
1469 gpio_request(GPIO_FN_FSIAIBT, NULL);
1470 gpio_request(GPIO_FN_FSIAILR, NULL);
1471 gpio_request(GPIO_FN_FSIAISLD, NULL);
1472 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1473 gpio_request(GPIO_PORT161, NULL);
1474 gpio_direction_output(GPIO_PORT161, 0); /* slave */
1475
1476 gpio_request(GPIO_PORT9, NULL);
1477 gpio_request(GPIO_PORT10, NULL);
1478 gpio_no_direction(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1479 gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
1480
1481 intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
1482
98d27b8a
KM		 1483 /* setup FSI2 port B (HDMI) */
1484 gpio_request(GPIO_FN_FSIBCK, NULL);
1485 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
1486
1487 /* set SPU2 clock to 119.6 MHz */
1488 clk = clk_get(NULL, "spu_clk");
1489 if (!IS_ERR(clk)) {
1490 clk_set_rate(clk, clk_round_rate(clk, 119600000));
1491 clk_put(clk);
1492 }
1493
cd8ab004
TS		 1494 /* enable Keypad */
1495 gpio_request(GPIO_FN_IRQ9_42, NULL);
6845664a 1496 irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
cd8ab004 1497
6ae1e19d
TS		 1498 /* enable Touchscreen */
1499 gpio_request(GPIO_FN_IRQ7_40, NULL);
6845664a 1500 irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
6ae1e19d 1501
80f1dc7c
TS		 1502 /* enable Accelerometer */
1503 gpio_request(GPIO_FN_IRQ21, NULL);
6845664a 1504 irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
1a44d72a 1505
6dff7da2 1506 /* enable SDHI0 */
6dff7da2
YG		 1507 gpio_request(GPIO_FN_SDHIWP0, NULL);
1508 gpio_request(GPIO_FN_SDHICMD0, NULL);
1509 gpio_request(GPIO_FN_SDHICLK0, NULL);
1510 gpio_request(GPIO_FN_SDHID0_3, NULL);
1511 gpio_request(GPIO_FN_SDHID0_2, NULL);
1512 gpio_request(GPIO_FN_SDHID0_1, NULL);
1513 gpio_request(GPIO_FN_SDHID0_0, NULL);
1514
56fb523f
GL		 1515 /* SDHI0 PORT172 card-detect IRQ26 */
1516 gpio_request(GPIO_FN_IRQ26_172, NULL);
1517
5bcd7517 1518#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
6dff7da2
YG		 1519 /* enable SDHI1 */
1520 gpio_request(GPIO_FN_SDHICMD1, NULL);
1521 gpio_request(GPIO_FN_SDHICLK1, NULL);
1522 gpio_request(GPIO_FN_SDHID1_3, NULL);
1523 gpio_request(GPIO_FN_SDHID1_2, NULL);
1524 gpio_request(GPIO_FN_SDHID1_1, NULL);
1525 gpio_request(GPIO_FN_SDHID1_0, NULL);
41491b9a 1526#endif
6dff7da2
YG		 1527 /* card detect pin for MMC slot (CN7) */
1528 gpio_request(GPIO_PORT41, NULL);
1529 gpio_direction_input(GPIO_PORT41);
1530
1531 /* enable SDHI2 */
1532 gpio_request(GPIO_FN_SDHICMD2, NULL);
1533 gpio_request(GPIO_FN_SDHICLK2, NULL);
1534 gpio_request(GPIO_FN_SDHID2_3, NULL);
1535 gpio_request(GPIO_FN_SDHID2_2, NULL);
1536 gpio_request(GPIO_FN_SDHID2_1, NULL);
1537 gpio_request(GPIO_FN_SDHID2_0, NULL);
1538
da5d1f4c
YG		 1539 /* card detect pin for microSD slot (CN23) */
1540 gpio_request(GPIO_PORT162, NULL);
1541 gpio_direction_input(GPIO_PORT162);
1542
41491b9a
YG		 1543 /* MMCIF */
1544 gpio_request(GPIO_FN_MMCD0_0, NULL);
1545 gpio_request(GPIO_FN_MMCD0_1, NULL);
1546 gpio_request(GPIO_FN_MMCD0_2, NULL);
1547 gpio_request(GPIO_FN_MMCD0_3, NULL);
1548 gpio_request(GPIO_FN_MMCD0_4, NULL);
1549 gpio_request(GPIO_FN_MMCD0_5, NULL);
1550 gpio_request(GPIO_FN_MMCD0_6, NULL);
1551 gpio_request(GPIO_FN_MMCD0_7, NULL);
1552 gpio_request(GPIO_FN_MMCCMD0, NULL);
1553 gpio_request(GPIO_FN_MMCCLK0, NULL);
1554
2aab52e8
BH		 1555 /* FLCTL */
1556 gpio_request(GPIO_FN_D0_NAF0, NULL);
1557 gpio_request(GPIO_FN_D1_NAF1, NULL);
1558 gpio_request(GPIO_FN_D2_NAF2, NULL);
1559 gpio_request(GPIO_FN_D3_NAF3, NULL);
1560 gpio_request(GPIO_FN_D4_NAF4, NULL);
1561 gpio_request(GPIO_FN_D5_NAF5, NULL);
1562 gpio_request(GPIO_FN_D6_NAF6, NULL);
1563 gpio_request(GPIO_FN_D7_NAF7, NULL);
1564 gpio_request(GPIO_FN_D8_NAF8, NULL);
1565 gpio_request(GPIO_FN_D9_NAF9, NULL);
1566 gpio_request(GPIO_FN_D10_NAF10, NULL);
1567 gpio_request(GPIO_FN_D11_NAF11, NULL);
1568 gpio_request(GPIO_FN_D12_NAF12, NULL);
1569 gpio_request(GPIO_FN_D13_NAF13, NULL);
1570 gpio_request(GPIO_FN_D14_NAF14, NULL);
1571 gpio_request(GPIO_FN_D15_NAF15, NULL);
1572 gpio_request(GPIO_FN_FCE0, NULL);
1573 gpio_request(GPIO_FN_WE0_FWE, NULL);
1574 gpio_request(GPIO_FN_FRB, NULL);
1575 gpio_request(GPIO_FN_A4_FOE, NULL);
1576 gpio_request(GPIO_FN_A5_FCDE, NULL);
1577 gpio_request(GPIO_FN_RD_FSC, NULL);
1578
56e78daf
YG		 1579 /* enable GPS module (GT-720F) */
1580 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
1581 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
1582
ae37c8de
MD		 1583 /* CEU */
1584 gpio_request(GPIO_FN_VIO_CLK, NULL);
1585 gpio_request(GPIO_FN_VIO_VD, NULL);
1586 gpio_request(GPIO_FN_VIO_HD, NULL);
1587 gpio_request(GPIO_FN_VIO_FIELD, NULL);
1588 gpio_request(GPIO_FN_VIO_CKO, NULL);
1589 gpio_request(GPIO_FN_VIO_D7, NULL);
1590 gpio_request(GPIO_FN_VIO_D6, NULL);
1591 gpio_request(GPIO_FN_VIO_D5, NULL);
1592 gpio_request(GPIO_FN_VIO_D4, NULL);
1593 gpio_request(GPIO_FN_VIO_D3, NULL);
1594 gpio_request(GPIO_FN_VIO_D2, NULL);
1595 gpio_request(GPIO_FN_VIO_D1, NULL);
1596 gpio_request(GPIO_FN_VIO_D0, NULL);
1597
12c4309b
KM		 1598 /* HDMI */
1599 gpio_request(GPIO_FN_HDMI_HPD, NULL);
1600 gpio_request(GPIO_FN_HDMI_CEC, NULL);
1601
1602 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
1603 srcr4 = __raw_readl(SRCR4);
1604 __raw_writel(srcr4 | (1 << 13), SRCR4);
1605 udelay(50);
1606 __raw_writel(srcr4 & ~(1 << 13), SRCR4);
1607
1a44d72a
KM		 1608 i2c_register_board_info(0, i2c0_devices,
1609 ARRAY_SIZE(i2c0_devices));
80f1dc7c
TS		 1610 i2c_register_board_info(1, i2c1_devices,
1611 ARRAY_SIZE(i2c1_devices));
11fee467 1612
920adc75
KM		 1613 sh7372_add_standard_devices();
1614
1615 platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
2ce51f8b 1616
e3e01091
RW		 1617 sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
1618 sh7372_add_device_to_domain(&sh7372_a4lc, &hdmi_lcdc_device);
91142bfe 1619 sh7372_add_device_to_domain(&sh7372_a4lc, &meram_device);
c1ba5bb5 1620 sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
d93f5cde
MD		 1621 sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device);
1622 sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs1_device);
2aab52e8 1623 sh7372_add_device_to_domain(&sh7372_a3sp, &nand_flash_device);
d93f5cde
MD		 1624 sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
1625 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
1626#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
1627 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
1628#endif
1629 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device);
382414b9 1630 sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);
e3e01091 1631
2ce51f8b 1632 hdmi_init_pm_clock();
97991657 1633 sh7372_pm_init();
a41b6466 1634 pm_clk_add(&fsi_device.dev, "spu2");
5c3f96b2 1635 pm_clk_add(&hdmi_lcdc_device.dev, "hdmi");
920adc75
KM		 1636}
1637
920adc75 1638MACHINE_START(MACKEREL, "mackerel")
426f1af9 1639 .map_io = sh7372_map_io,
5d7220ec 1640 .init_early = sh7372_add_early_devices,
920adc75 1641 .init_irq = sh7372_init_irq,
863b1719 1642 .handle_irq = shmobile_handle_irq_intc,
920adc75 1643 .init_machine = mackerel_init,
21cc1b7e 1644 .init_late = shmobile_init_late,
17254bff 1645 .timer = &shmobile_timer,
920adc75 1646MACHINE_END
kernel source for telekom puls (alcatel/mediatek)