projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 86cd4f5f KP |
1 | /* linux/arch/arm/mach-s5pc100/setup-sdhci.c |
| 2 | * | |
| 3 | * Copyright 2008 Samsung Electronics | |
| 4 | * | |
| 5 | * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC) | |
| 6 | * | |
| 7 | * Based on mach-s3c6410/setup-sdhci.c | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License version 2 as | |
| 11 | * published by the Free Software Foundation. | |
| 12 | */ | |
| 13 | ||
| 14 | #include <linux/kernel.h> | |
| 15 | #include <linux/types.h> | |
| 16 | #include <linux/interrupt.h> | |
| 17 | #include <linux/platform_device.h> | |
| 18 | #include <linux/io.h> | |
| 19 | ||
| 20 | #include <linux/mmc/card.h> | |
| 21 | #include <linux/mmc/host.h> | |
| 22 | ||
| 23 | #include <plat/regs-sdhci.h> | |
| 24 | #include <plat/sdhci.h> | |
| 25 | ||
| 26 | /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ | |
| 27 | ||
| 28 | char *s5pc100_hsmmc_clksrcs[4] = { | |
| aaeedff6 MS |
29 | [0] = "hsmmc", /* HCLK */ |
| 30 | /* [1] = "hsmmc", - duplicate HCLK entry */ | |
| 31 | [2] = "sclk_mmc", /* mmc_bus */ | |
| 32 | /* [3] = "48m", - note not successfully used yet */ | |
| 86cd4f5f KP |
33 | }; |
| 34 | ||
| 35 | ||
| 36 | void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev, | |
| 37 | void __iomem *r, | |
| 38 | struct mmc_ios *ios, | |
| 39 | struct mmc_card *card) | |
| 40 | { | |
| 41 | u32 ctrl2, ctrl3; | |
| 42 | ||
| 25985edc | 43 | /* don't need to alter anything according to card-type */ |
| 86cd4f5f KP |
44 | |
| 45 | writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); | |
| 46 | ||
| 47 | ctrl2 = readl(r + S3C_SDHCI_CONTROL2); | |
| 48 | ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; | |
| 49 | ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | | |
| 50 | S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | | |
| 51 | S3C_SDHCI_CTRL2_ENFBCLKRX | | |
| 52 | S3C_SDHCI_CTRL2_DFCNT_NONE | | |
| 53 | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); | |
| 54 | ||
| 55 | if (ios->clock < 25 * 1000000) | |
| 56 | ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | | |
| 57 | S3C_SDHCI_CTRL3_FCSEL2 | | |
| 58 | S3C_SDHCI_CTRL3_FCSEL1 | | |
| 59 | S3C_SDHCI_CTRL3_FCSEL0); | |
| 60 | else | |
| 61 | ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); | |
| 62 | ||
| 63 | writel(ctrl2, r + S3C_SDHCI_CONTROL2); | |
| 64 | writel(ctrl3, r + S3C_SDHCI_CONTROL3); | |
| 65 | } |