[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-s3c2410 / mach-bast.c

/* linux/arch/arm/mach-s3c2410/mach-bast.c
 *
 * Copyright (c) 2003-2005 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.simtec.co.uk/products/EB2410ITX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/dm9000.h>

#include <net/ax88796.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <asm/arch/bast-map.h>
#include <asm/arch/bast-irq.h>
#include <asm/arch/bast-cpld.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

//#include <asm/debug-ll.h>
#include <asm/plat-s3c/regs-serial.h>
#include <asm/arch/regs-gpio.h>
#include <asm/arch/regs-mem.h>
#include <asm/arch/regs-lcd.h>

#include <asm/plat-s3c/nand.h>
#include <asm/plat-s3c/iic.h>
#include <asm/arch/fb.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <linux/serial_8250.h>

#include <asm/plat-s3c24xx/clock.h>
#include <asm/plat-s3c24xx/devs.h>
#include <asm/plat-s3c24xx/cpu.h>
#include "usb-simtec.h"

#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"

/* macros for virtual address mods for the io space entries */
#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)

/* macros to modify the physical addresses for io space */

#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))

static struct map_desc bast_iodesc[] __initdata = {
  /* ISA IO areas */
  {
	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	  .pfn		= PA_CS2(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,
	  .pfn		= PA_CS3(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  },
  /* bast CPLD control registers, and external interrupt controls */
  {
	  .virtual	= (u32)BAST_VA_CTRL1,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL1),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL2,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL2),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL3,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL3),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL4,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL4),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },
  /* PC104 IRQ mux */
  {
	  .virtual	= (u32)BAST_VA_PC104_IRQREQ,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQRAW,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQMASK,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },

  /* peripheral space... one for each of fast/slow/byte/16bit */
  /* note, ide is only decoded in word space, even though some registers
   * are only 8bit */

  /* slow, byte */
  { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
  { VA_C2(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
  { VA_C2(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
  { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },

  /* slow, word */
  { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
  { VA_C3(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
  { VA_C3(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
  { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },

  /* fast, byte */
  { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
  { VA_C4(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
  { VA_C4(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
  { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },

  /* fast, word */
  { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
  { VA_C5(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
  { VA_C5(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
  { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};


static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	},
	/* port 2 is not actually used */
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	}
};

/* NOR Flash on BAST board */

static struct resource bast_nor_resource[] = {
	[0] = {
		.start = S3C2410_CS1 + 0x4000000,
		.end   = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
		.flags = IORESOURCE_MEM,
	}
};

static struct platform_device bast_device_nor = {
	.name		= "bast-nor",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(bast_nor_resource),
	.resource	= bast_nor_resource,
};

/* NAND Flash on BAST board */

#ifdef CONFIG_PM
static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
{
	/* ensure that an nRESET is not generated on resume. */
	s3c2410_gpio_setpin(S3C2410_GPA21, 1);
	s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);

	return 0;
}

static int bast_pm_resume(struct sys_device *sd)
{
	s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
	return 0;
}

#else
#define bast_pm_suspend NULL
#define bast_pm_resume NULL
#endif

static struct sysdev_class bast_pm_sysclass = {
	.name		= "mach-bast",
	.suspend	= bast_pm_suspend,
	.resume		= bast_pm_resume,
};

static struct sys_device bast_pm_sysdev = {
	.cls		= &bast_pm_sysclass,
};

static int smartmedia_map[] = { 0 };
static int chip0_map[] = { 1 };
static int chip1_map[] = { 2 };
static int chip2_map[] = { 3 };

static struct mtd_partition bast_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user",
		.offset	= SZ_4M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the bast has 4 selectable slots for nand-flash, the three
 * on-board chip areas, as well as the external SmartMedia
 * slot.
 *
 * Note, there is no current hot-plug support for the SmartMedia
 * socket.
*/

static struct s3c2410_nand_set bast_nand_sets[] = {
	[0] = {
		.name		= "SmartMedia",
		.nr_chips	= 1,
		.nr_map		= smartmedia_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[1] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[3] = {
		.name		= "chip2",
		.nr_chips	= 1,
		.nr_map		= chip2_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	}
};

static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(BAST_VA_CTRL2);
	tmp &= BAST_CPLD_CTLR2_IDERST;
	tmp |= slot;
	tmp |= BAST_CPLD_CTRL2_WNAND;

	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);

	__raw_writeb(tmp, BAST_VA_CTRL2);
}

static struct s3c2410_platform_nand bast_nand_info = {
	.tacls		= 30,
	.twrph0		= 60,
	.twrph1		= 60,
	.nr_sets	= ARRAY_SIZE(bast_nand_sets),
	.sets		= bast_nand_sets,
	.select_chip	= bast_nand_select,
};

/* DM9000 */

static struct resource bast_dm9k_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_DM9000,
		.end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
		.end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = IRQ_DM9000,
		.end   = IRQ_DM9000,
		.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
	}

};

/* for the moment we limit ourselves to 16bit IO until some
 * better IO routines can be written and tested
*/

static struct dm9000_plat_data bast_dm9k_platdata = {
	.flags		= DM9000_PLATF_16BITONLY,
};

static struct platform_device bast_device_dm9k = {
	.name		= "dm9000",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_dm9k_resource),
	.resource	= bast_dm9k_resource,
	.dev		= {
		.platform_data = &bast_dm9k_platdata,
	}
};

/* serial devices */

#define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
#define SERIAL_CLK   (1843200)

static struct plat_serial8250_port bast_sio_data[] = {
	[0] = {
		.mapbase	= SERIAL_BASE + 0x2f8,
		.irq		= IRQ_PCSERIAL1,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	[1] = {
		.mapbase	= SERIAL_BASE + 0x3f8,
		.irq		= IRQ_PCSERIAL2,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	{ }
};

static struct platform_device bast_sio = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= &bast_sio_data,
	},
};

/* we have devices on the bus which cannot work much over the
 * standard 100KHz i2c bus frequency
*/

static struct s3c2410_platform_i2c bast_i2c_info = {
	.flags		= 0,
	.slave_addr	= 0x10,
	.bus_freq	= 100*1000,
	.max_freq	= 130*1000,
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data bast_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource bast_asix_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET,
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = IRQ_ASIX,
		.end   = IRQ_ASIX,
		.flags = IORESOURCE_IRQ
	}
};

static struct platform_device bast_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asix_resource),
	.resource	= bast_asix_resource,
	.dev		= {
		.platform_data = &bast_asix_platdata
	}
};

/* Asix AX88796 10/100 ethernet controller parallel port */

static struct resource bast_asixpp_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
		.flags = IORESOURCE_MEM,
	}
};

static struct platform_device bast_device_axpp = {
	.name		= "ax88796-pp",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asixpp_resource),
	.resource	= bast_asixpp_resource,
};

/* LCD/VGA controller */

static struct s3c2410fb_display __initdata bast_lcd_info[] = {
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 4,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 8,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 16,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
};

/* LCD/VGA controller */

static struct s3c2410fb_mach_info __initdata bast_fb_info = {

	.displays = bast_lcd_info,
	.num_displays = ARRAY_SIZE(bast_lcd_info),
	.default_display = 1,
};

/* Standard BAST devices */

static struct platform_device *bast_devices[] __initdata = {
	&s3c_device_usb,
	&s3c_device_lcd,
	&s3c_device_wdt,
	&s3c_device_i2c,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&bast_device_nor,
	&bast_device_dm9k,
	&bast_device_asix,
	&bast_device_axpp,
	&bast_sio,
};

static struct clk *bast_clocks[] = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static void __init bast_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));

	s3c_device_nand.dev.platform_data = &bast_nand_info;
	s3c_device_i2c.dev.platform_data = &bast_i2c_info;

	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));

	usb_simtec_init();
}

static void __init bast_init(void)
{
	sysdev_class_register(&bast_pm_sysclass);
	sysdev_register(&bast_pm_sysdev);

	s3c24xx_fb_set_platdata(&bast_fb_info);
	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
}

MACHINE_START(BAST, "Simtec-BAST")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= bast_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= bast_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/* linux/arch/arm/mach-s3c2410/mach-bast.c
	2	*
	3	* Copyright (c) 2003-2005 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* http://www.simtec.co.uk/products/EB2410ITX/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
1da177e4 LT	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/list.h>
	17	#include <linux/timer.h>
	18	#include <linux/init.h>
6ddc4b07	19	#include <linux/sysdev.h>
b6d1f542	20	#include <linux/serial_core.h>
d052d1be	21	#include <linux/platform_device.h>
d97a666f	22	#include <linux/dm9000.h>
1da177e4	23
5ce4b1fe BD	24	#include <net/ax88796.h>
5ce4b1fe BD	25
1da177e4 LT	26	#include <asm/mach/arch.h>
	27	#include <asm/mach/map.h>
	28	#include <asm/mach/irq.h>
	29
	30	#include <asm/arch/bast-map.h>
	31	#include <asm/arch/bast-irq.h>
	32	#include <asm/arch/bast-cpld.h>
	33
	34	#include <asm/hardware.h>
	35	#include <asm/io.h>
	36	#include <asm/irq.h>
	37	#include <asm/mach-types.h>
	38
	39	//#include <asm/debug-ll.h>
531b617c	40	#include <asm/plat-s3c/regs-serial.h>
1da177e4 LT	41	#include <asm/arch/regs-gpio.h>
1da177e4 LT	42	#include <asm/arch/regs-mem.h>
d97a666f	43	#include <asm/arch/regs-lcd.h>
58c8d570	44
531b617c BD	45	#include <asm/plat-s3c/nand.h>
531b617c BD	46	#include <asm/plat-s3c/iic.h>
58c8d570	47	#include <asm/arch/fb.h>
1da177e4 LT	48
	49	#include <linux/mtd/mtd.h>
	50	#include <linux/mtd/nand.h>
	51	#include <linux/mtd/nand_ecc.h>
	52	#include <linux/mtd/partitions.h>
	53
65cc3370 BD	54	#include <linux/serial_8250.h>
65cc3370 BD	55
a21765a7 BD	56	#include <asm/plat-s3c24xx/clock.h>
	57	#include <asm/plat-s3c24xx/devs.h>
	58	#include <asm/plat-s3c24xx/cpu.h>
1da177e4	59	#include "usb-simtec.h"
1da177e4 LT	60
	61	#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
	62
	63	/* macros for virtual address mods for the io space entries */
	64	#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
	65	#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
	66	#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
	67	#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
	68
	69	/* macros to modify the physical addresses for io space */
	70
1d23b65d BD	71	#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
	72	#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
	73	#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
	74	#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
1da177e4 LT	75
	76	static struct map_desc bast_iodesc[] __initdata = {
	77	/* ISA IO areas */
1d23b65d BD	78	{
	79	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	80	.pfn = PA_CS2(BAST_PA_ISAIO),
	81	.length = SZ_16M,
	82	.type = MT_DEVICE,
	83	}, {
	84	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	85	.pfn = PA_CS3(BAST_PA_ISAIO),
	86	.length = SZ_16M,
	87	.type = MT_DEVICE,
	88	},
1da177e4	89	/* bast CPLD control registers, and external interrupt controls */
1d23b65d BD	90	{
	91	.virtual = (u32)BAST_VA_CTRL1,
	92	.pfn = __phys_to_pfn(BAST_PA_CTRL1),
	93	.length = SZ_1M,
	94	.type = MT_DEVICE,
	95	}, {
	96	.virtual = (u32)BAST_VA_CTRL2,
	97	.pfn = __phys_to_pfn(BAST_PA_CTRL2),
	98	.length = SZ_1M,
	99	.type = MT_DEVICE,
	100	}, {
	101	.virtual = (u32)BAST_VA_CTRL3,
	102	.pfn = __phys_to_pfn(BAST_PA_CTRL3),
	103	.length = SZ_1M,
	104	.type = MT_DEVICE,
	105	}, {
	106	.virtual = (u32)BAST_VA_CTRL4,
	107	.pfn = __phys_to_pfn(BAST_PA_CTRL4),
	108	.length = SZ_1M,
	109	.type = MT_DEVICE,
	110	},
1da177e4	111	/* PC104 IRQ mux */
1d23b65d BD	112	{
	113	.virtual = (u32)BAST_VA_PC104_IRQREQ,
	114	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	115	.length = SZ_1M,
	116	.type = MT_DEVICE,
	117	}, {
	118	.virtual = (u32)BAST_VA_PC104_IRQRAW,
	119	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	120	.length = SZ_1M,
	121	.type = MT_DEVICE,
	122	}, {
	123	.virtual = (u32)BAST_VA_PC104_IRQMASK,
	124	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	125	.length = SZ_1M,
	126	.type = MT_DEVICE,
	127	},
1da177e4 LT	128
	129	/* peripheral space... one for each of fast/slow/byte/16bit */
	130	/* note, ide is only decoded in word space, even though some registers
	131	* are only 8bit */
	132
	133	/* slow, byte */
	134	{ VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	135	{ VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	136	{ VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	137	{ VA_C2(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
	138	{ VA_C2(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
	139	{ VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
	140	{ VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
	141
	142	/* slow, word */
	143	{ VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	144	{ VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	145	{ VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	146	{ VA_C3(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
	147	{ VA_C3(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
	148	{ VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
	149	{ VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
	150
	151	/* fast, byte */
	152	{ VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	153	{ VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	154	{ VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	155	{ VA_C4(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
	156	{ VA_C4(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
	157	{ VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
	158	{ VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
	159
	160	/* fast, word */
	161	{ VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	162	{ VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	163	{ VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	164	{ VA_C5(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
	165	{ VA_C5(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
	166	{ VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
	167	{ VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
	168	};
	169
	170	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	171	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	172	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	173
	174	static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
	175	[0] = {
	176	.name = "uclk",
	177	.divisor = 1,
	178	.min_baud = 0,
	179	.max_baud = 0,
	180	},
	181	[1] = {
	182	.name = "pclk",
	183	.divisor = 1,
	184	.min_baud = 0,
b526bf23	185	.max_baud = 0,
1da177e4 LT	186	}
	187	};
	188
	189
66a9b49a	190	static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
1da177e4 LT	191	[0] = {
	192	.hwport = 0,
	193	.flags = 0,
	194	.ucon = UCON,
	195	.ulcon = ULCON,
	196	.ufcon = UFCON,
	197	.clocks = bast_serial_clocks,
b526bf23	198	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	199	},
	200	[1] = {
	201	.hwport = 1,
	202	.flags = 0,
	203	.ucon = UCON,
	204	.ulcon = ULCON,
	205	.ufcon = UFCON,
	206	.clocks = bast_serial_clocks,
b526bf23	207	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	208	},
	209	/* port 2 is not actually used */
	210	[2] = {
	211	.hwport = 2,
	212	.flags = 0,
	213	.ucon = UCON,
	214	.ulcon = ULCON,
	215	.ufcon = UFCON,
	216	.clocks = bast_serial_clocks,
b526bf23	217	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	218	}
	219	};
	220
	221	/* NOR Flash on BAST board */
	222
	223	static struct resource bast_nor_resource[] = {
	224	[0] = {
	225	.start = S3C2410_CS1 + 0x4000000,
	226	.end = S3C2410_CS1 + 0x4000000 + (3210241024) - 1,
	227	.flags = IORESOURCE_MEM,
	228	}
	229	};
	230
	231	static struct platform_device bast_device_nor = {
	232	.name = "bast-nor",
	233	.id = -1,
	234	.num_resources = ARRAY_SIZE(bast_nor_resource),
	235	.resource = bast_nor_resource,
	236	};
	237
	238	/* NAND Flash on BAST board */
	239
6ddc4b07 BD	240	#ifdef CONFIG_PM
	241	static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
	242	{
	243	/* ensure that an nRESET is not generated on resume. */
	244	s3c2410_gpio_setpin(S3C2410_GPA21, 1);
	245	s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
	246
	247	return 0;
	248	}
	249
	250	static int bast_pm_resume(struct sys_device *sd)
	251	{
	252	s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
	253	return 0;
	254	}
	255
	256	#else
	257	#define bast_pm_suspend NULL
	258	#define bast_pm_resume NULL
	259	#endif
	260
	261	static struct sysdev_class bast_pm_sysclass = {
140749e2	262	.name = "mach-bast",
6ddc4b07 BD	263	.suspend = bast_pm_suspend,
	264	.resume = bast_pm_resume,
	265	};
	266
	267	static struct sys_device bast_pm_sysdev = {
	268	.cls = &bast_pm_sysclass,
	269	};
1da177e4 LT	270
	271	static int smartmedia_map[] = { 0 };
	272	static int chip0_map[] = { 1 };
	273	static int chip1_map[] = { 2 };
	274	static int chip2_map[] = { 3 };
	275
9f693d7b	276	static struct mtd_partition bast_default_nand_part[] = {
1da177e4 LT	277	[0] = {
	278	.name = "Boot Agent",
	279	.size = SZ_16K,
b526bf23	280	.offset = 0,
1da177e4 LT	281	},
	282	[1] = {
	283	.name = "/boot",
	284	.size = SZ_4M - SZ_16K,
	285	.offset = SZ_16K,
	286	},
	287	[2] = {
	288	.name = "user",
	289	.offset = SZ_4M,
	290	.size = MTDPART_SIZ_FULL,
	291	}
	292	};
	293
	294	/* the bast has 4 selectable slots for nand-flash, the three
	295	* on-board chip areas, as well as the external SmartMedia
	296	* slot.
	297	*
	298	* Note, there is no current hot-plug support for the SmartMedia
	299	* socket.
	300	*/
	301
	302	static struct s3c2410_nand_set bast_nand_sets[] = {
	303	[0] = {
	304	.name = "SmartMedia",
	305	.nr_chips = 1,
	306	.nr_map = smartmedia_map,
	307	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	308	.partitions = bast_default_nand_part,
1da177e4 LT	309	},
	310	[1] = {
	311	.name = "chip0",
	312	.nr_chips = 1,
	313	.nr_map = chip0_map,
	314	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	315	.partitions = bast_default_nand_part,
1da177e4 LT	316	},
	317	[2] = {
	318	.name = "chip1",
	319	.nr_chips = 1,
	320	.nr_map = chip1_map,
	321	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	322	.partitions = bast_default_nand_part,
1da177e4 LT	323	},
	324	[3] = {
	325	.name = "chip2",
	326	.nr_chips = 1,
	327	.nr_map = chip2_map,
	328	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	329	.partitions = bast_default_nand_part,
1da177e4 LT	330	}
	331	};
	332
	333	static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
	334	{
	335	unsigned int tmp;
	336
	337	slot = set->nr_map[slot] & 3;
	338
	339	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
	340	slot, set, set->nr_map);
	341
	342	tmp = __raw_readb(BAST_VA_CTRL2);
	343	tmp &= BAST_CPLD_CTLR2_IDERST;
	344	tmp \|= slot;
	345	tmp \|= BAST_CPLD_CTRL2_WNAND;
	346
	347	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
	348
	349	__raw_writeb(tmp, BAST_VA_CTRL2);
	350	}
	351
	352	static struct s3c2410_platform_nand bast_nand_info = {
b048dbf4 BD	353	.tacls = 30,
	354	.twrph0 = 60,
	355	.twrph1 = 60,
1da177e4 LT	356	.nr_sets = ARRAY_SIZE(bast_nand_sets),
	357	.sets = bast_nand_sets,
	358	.select_chip = bast_nand_select,
	359	};
	360
d97a666f BD	361	/* DM9000 */
	362
	363	static struct resource bast_dm9k_resource[] = {
	364	[0] = {
	365	.start = S3C2410_CS5 + BAST_PA_DM9000,
	366	.end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
b526bf23	367	.flags = IORESOURCE_MEM,
d97a666f BD	368	},
	369	[1] = {
	370	.start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
	371	.end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
b526bf23	372	.flags = IORESOURCE_MEM,
d97a666f BD	373	},
	374	[2] = {
	375	.start = IRQ_DM9000,
	376	.end = IRQ_DM9000,
ace94f9e	377	.flags = IORESOURCE_IRQ \| IRQF_TRIGGER_HIGH,
d97a666f BD	378	}
	379
	380	};
	381
	382	/* for the moment we limit ourselves to 16bit IO until some
	383	* better IO routines can be written and tested
	384	*/
	385
9f693d7b	386	static struct dm9000_plat_data bast_dm9k_platdata = {
b526bf23	387	.flags = DM9000_PLATF_16BITONLY,
d97a666f BD	388	};
	389
	390	static struct platform_device bast_device_dm9k = {
	391	.name = "dm9000",
	392	.id = 0,
	393	.num_resources = ARRAY_SIZE(bast_dm9k_resource),
	394	.resource = bast_dm9k_resource,
	395	.dev = {
	396	.platform_data = &bast_dm9k_platdata,
	397	}
	398	};
	399
65cc3370 BD	400	/* serial devices */
	401
	402	#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
	403	#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF \| UPF_IOREMAP \| UPF_SHARE_IRQ)
	404	#define SERIAL_CLK (1843200)
	405
	406	static struct plat_serial8250_port bast_sio_data[] = {
	407	[0] = {
	408	.mapbase = SERIAL_BASE + 0x2f8,
	409	.irq = IRQ_PCSERIAL1,
	410	.flags = SERIAL_FLAGS,
	411	.iotype = UPIO_MEM,
	412	.regshift = 0,
	413	.uartclk = SERIAL_CLK,
	414	},
	415	[1] = {
	416	.mapbase = SERIAL_BASE + 0x3f8,
	417	.irq = IRQ_PCSERIAL2,
	418	.flags = SERIAL_FLAGS,
	419	.iotype = UPIO_MEM,
	420	.regshift = 0,
	421	.uartclk = SERIAL_CLK,
	422	},
	423	{ }
	424	};
	425
	426	static struct platform_device bast_sio = {
	427	.name = "serial8250",
6df29deb	428	.id = PLAT8250_DEV_PLATFORM,
65cc3370 BD	429	.dev = {
	430	.platform_data = &bast_sio_data,
	431	},
	432	};
1da177e4	433
1fcf8448 BD	434	/* we have devices on the bus which cannot work much over the
	435	* standard 100KHz i2c bus frequency
	436	*/
	437
	438	static struct s3c2410_platform_i2c bast_i2c_info = {
	439	.flags = 0,
	440	.slave_addr = 0x10,
	441	.bus_freq = 100*1000,
	442	.max_freq = 130*1000,
	443	};
	444
5ce4b1fe BD	445	/* Asix AX88796 10/100 ethernet controller */
	446
	447	static struct ax_plat_data bast_asix_platdata = {
	448	.flags = AXFLG_MAC_FROMDEV,
	449	.wordlength = 2,
	450	.dcr_val = 0x48,
	451	.rcr_val = 0x40,
	452	};
	453
	454	static struct resource bast_asix_resource[] = {
	455	[0] = {
	456	.start = S3C2410_CS5 + BAST_PA_ASIXNET,
	457	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
	458	.flags = IORESOURCE_MEM,
	459	},
	460	[1] = {
	461	.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
	462	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
	463	.flags = IORESOURCE_MEM,
	464	},
	465	[2] = {
	466	.start = IRQ_ASIX,
	467	.end = IRQ_ASIX,
	468	.flags = IORESOURCE_IRQ
	469	}
	470	};
	471
	472	static struct platform_device bast_device_asix = {
	473	.name = "ax88796",
	474	.id = 0,
	475	.num_resources = ARRAY_SIZE(bast_asix_resource),
	476	.resource = bast_asix_resource,
	477	.dev = {
	478	.platform_data = &bast_asix_platdata
	479	}
	480	};
	481
	482	/* Asix AX88796 10/100 ethernet controller parallel port */
	483
	484	static struct resource bast_asixpp_resource[] = {
	485	[0] = {
	486	.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
	487	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
	488	.flags = IORESOURCE_MEM,
	489	}
	490	};
	491
	492	static struct platform_device bast_device_axpp = {
	493	.name = "ax88796-pp",
	494	.id = 0,
	495	.num_resources = ARRAY_SIZE(bast_asixpp_resource),
	496	.resource = bast_asixpp_resource,
	497	};
	498
	499	/* LCD/VGA controller */
58c8d570	500
09fe75f6 KH	501	static struct s3c2410fb_display __initdata bast_lcd_info[] = {
09fe75f6 KH	502	{
1f411537	503	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	504	.width = 640,
09fe75f6 KH	505	.height = 480,
5f20f69b	506
69816699	507	.pixclock = 33333,
09fe75f6 KH	508	.xres = 640,
	509	.yres = 480,
	510	.bpp = 4,
1f411537 KH	511	.left_margin = 40,
1f411537 KH	512	.right_margin = 20,
93d11f5a	513	.hsync_len = 88,
5f20f69b KH	514	.upper_margin = 30,
5f20f69b KH	515	.lower_margin = 32,
93d11f5a	516	.vsync_len = 3,
09fe75f6	517
f28ef573	518	.lcdcon5 = 0x00014b02,
58c8d570	519	},
09fe75f6	520	{
1f411537	521	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	522	.width = 640,
	523	.height = 480,
	524
69816699	525	.pixclock = 33333,
09fe75f6 KH	526	.xres = 640,
	527	.yres = 480,
	528	.bpp = 8,
1f411537 KH	529	.left_margin = 40,
1f411537 KH	530	.right_margin = 20,
93d11f5a	531	.hsync_len = 88,
5f20f69b KH	532	.upper_margin = 30,
5f20f69b KH	533	.lower_margin = 32,
93d11f5a	534	.vsync_len = 3,
09fe75f6	535
f28ef573	536	.lcdcon5 = 0x00014b02,
09fe75f6 KH	537	},
09fe75f6 KH	538	{
1f411537	539	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	540	.width = 640,
	541	.height = 480,
	542
69816699	543	.pixclock = 33333,
09fe75f6 KH	544	.xres = 640,
	545	.yres = 480,
	546	.bpp = 16,
1f411537 KH	547	.left_margin = 40,
1f411537 KH	548	.right_margin = 20,
93d11f5a	549	.hsync_len = 88,
5f20f69b KH	550	.upper_margin = 30,
5f20f69b KH	551	.lower_margin = 32,
93d11f5a	552	.vsync_len = 3,
09fe75f6	553
f28ef573	554	.lcdcon5 = 0x00014b02,
09fe75f6 KH	555	},
09fe75f6 KH	556	};
58c8d570	557
09fe75f6 KH	558	/* LCD/VGA controller */
	559
	560	static struct s3c2410fb_mach_info __initdata bast_fb_info = {
	561
	562	.displays = bast_lcd_info,
	563	.num_displays = ARRAY_SIZE(bast_lcd_info),
9cbae12c	564	.default_display = 1,
58c8d570 BD	565	};
58c8d570 BD	566
1da177e4 LT	567	/* Standard BAST devices */
	568
	569	static struct platform_device *bast_devices[] __initdata = {
	570	&s3c_device_usb,
	571	&s3c_device_lcd,
	572	&s3c_device_wdt,
	573	&s3c_device_i2c,
1da177e4 LT	574	&s3c_device_rtc,
1da177e4 LT	575	&s3c_device_nand,
d97a666f BD	576	&bast_device_nor,
d97a666f BD	577	&bast_device_dm9k,
5ce4b1fe BD	578	&bast_device_asix,
5ce4b1fe BD	579	&bast_device_axpp,
65cc3370	580	&bast_sio,
1da177e4 LT	581	};
	582
	583	static struct clk *bast_clocks[] = {
	584	&s3c24xx_dclk0,
	585	&s3c24xx_dclk1,
	586	&s3c24xx_clkout0,
	587	&s3c24xx_clkout1,
	588	&s3c24xx_uclk,
	589	};
	590
5fe10ab1	591	static void __init bast_map_io(void)
1da177e4 LT	592	{
	593	/* initialise the clocks */
	594
d96a9804	595	s3c24xx_dclk0.parent = &clk_upll;
1da177e4 LT	596	s3c24xx_dclk0.rate = 1210001000;
1da177e4 LT	597
d96a9804	598	s3c24xx_dclk1.parent = &clk_upll;
1da177e4 LT	599	s3c24xx_dclk1.rate = 2410001000;
	600
	601	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	602	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	603
	604	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	605
ce89c206 BD	606	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
ce89c206 BD	607
1da177e4	608	s3c_device_nand.dev.platform_data = &bast_nand_info;
1fcf8448	609	s3c_device_i2c.dev.platform_data = &bast_i2c_info;
1da177e4 LT	610
	611	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	612	s3c24xx_init_clocks(0);
	613	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
57e5171c	614
1da177e4 LT	615	usb_simtec_init();
	616	}
	617
58c8d570 BD	618	static void __init bast_init(void)
58c8d570 BD	619	{
6ddc4b07 BD	620	sysdev_class_register(&bast_pm_sysclass);
	621	sysdev_register(&bast_pm_sysdev);
	622
09fe75f6	623	s3c24xx_fb_set_platdata(&bast_fb_info);
57e5171c	624	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
58c8d570	625	}
1da177e4 LT	626
1da177e4 LT	627	MACHINE_START(BAST, "Simtec-BAST")
e9dea0c6	628	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
e9dea0c6 RK	629	.phys_io = S3C2410_PA_UART,
	630	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	631	.boot_params = S3C2410_SDRAM_PA + 0x100,
f705b1ae BD	632	.map_io = bast_map_io,
f705b1ae BD	633	.init_irq = s3c24xx_init_irq,
58c8d570	634	.init_machine = bast_init,
1da177e4 LT	635	.timer = &s3c24xx_timer,
1da177e4 LT	636	MACHINE_END