[ARM] mm: enable sparsemem on clps7500 and RiscPC
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-rpc / include / mach / memory.h
CommitLineData
1da177e4 1/*
a09e64fb 2 * arch/arm/mach-rpc/include/mach/memory.h
1da177e4
LT
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Changelog:
11 * 20-Oct-1996 RMK Created
12 * 31-Dec-1997 RMK Fixed definitions to reduce warnings
13 * 11-Jan-1998 RMK Uninlined to reduce hits on cache
14 * 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt
15 * 21-Mar-1999 RMK Renamed to memory.h
16 * RMK Added TASK_SIZE and PAGE_OFFSET
17 */
18#ifndef __ASM_ARCH_MEMORY_H
19#define __ASM_ARCH_MEMORY_H
20
21/*
22 * Physical DRAM offset.
23 */
f09b9979 24#define PHYS_OFFSET UL(0x10000000)
1da177e4
LT
25
26/*
27 * These are exactly the same on the RiscPC as the
28 * physical memory view.
29 */
30#define __virt_to_bus(x) __virt_to_phys(x)
31#define __bus_to_virt(x) __phys_to_virt(x)
32
74d02fb9
RK
33/*
34 * Cache flushing area - ROM
35 */
36#define FLUSH_BASE_PHYS 0x00000000
37#define FLUSH_BASE 0xdf000000
38
07f841b7
RK
39/*
40 * Sparsemem support. Each section is a maximum of 64MB. The sections
41 * are offset by 128MB and can cover 128MB, so that gives us a maximum
42 * of 29 physmem bits.
43 */
44#define MAX_PHYSMEM_BITS 29
45#define SECTION_SIZE_BITS 26
46
1da177e4 47#endif