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ARM: 5957/1: ARM: RealView SD/MMC Card detection and write-protect using GPIOLIB
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-realview / core.c
CommitLineData
8ad68bbf
CM		 1/*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
8ad68bbf 21#include <linux/init.h>
1be7228d 22#include <linux/platform_device.h>
8ad68bbf
CM		 23#include <linux/dma-mapping.h>
24#include <linux/sysdev.h>
25#include <linux/interrupt.h>
a62c80e5
RK		 26#include <linux/amba/bus.h>
27#include <linux/amba/clcd.h>
85802afe 28#include <linux/clocksource.h>
ae30ceac 29#include <linux/clockchips.h>
fced80c7 30#include <linux/io.h>
c5142e84 31#include <linux/smsc911x.h>
6be62ba2 32#include <linux/ata_platform.h>
6ef297f8 33#include <linux/amba/mmci.h>
5a0e3ad6 34#include <linux/gfp.h>
8ad68bbf 35
cf30fb4a 36#include <asm/clkdev.h>
8ad68bbf 37#include <asm/system.h>
a09e64fb 38#include <mach/hardware.h>
8ad68bbf
CM		 39#include <asm/irq.h>
40#include <asm/leds.h>
68c3d935 41#include <asm/mach-types.h>
8ad68bbf
CM		 42#include <asm/hardware/arm_timer.h>
43#include <asm/hardware/icst307.h>
44
45#include <asm/mach/arch.h>
46#include <asm/mach/flash.h>
47#include <asm/mach/irq.h>
8ad68bbf 48#include <asm/mach/map.h>
8ad68bbf
CM		 49
50#include <asm/hardware/gic.h>
51
ee8c9571
CM		 52#include <mach/platform.h>
53#include <mach/irqs.h>
54
8ad68bbf
CM		 55#include "core.h"
56#include "clock.h"
57
58#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
59
1bbdf637 60/* used by entry-macro.S and platsmp.c */
c4057f52
CM		 61void __iomem *gic_cpu_base_addr;
62
c97c5aa8
CM		 63#ifdef CONFIG_ZONE_DMA
64/*
65 * Adjust the zones if there are restrictions for DMA access.
66 */
67void __init realview_adjust_zones(int node, unsigned long *size,
68 unsigned long *hole)
69{
70 unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
71
72 if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
73 return;
74
75 size[ZONE_NORMAL] = size[0] - dma_size;
76 size[ZONE_DMA] = dma_size;
77 hole[ZONE_NORMAL] = hole[0];
78 hole[ZONE_DMA] = 0;
79}
80#endif
81
8ad68bbf
CM		 82/*
83 * This is the RealView sched_clock implementation. This has
84 * a resolution of 41.7ns, and a maximum value of about 179s.
85 */
86unsigned long long sched_clock(void)
87{
88 unsigned long long v;
89
90 v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
91 do_div(v, 3);
92
93 return v;
94}
95
96
97#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
98
99static int realview_flash_init(void)
100{
101 u32 val;
102
103 val = __raw_readl(REALVIEW_FLASHCTRL);
104 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
105 __raw_writel(val, REALVIEW_FLASHCTRL);
106
107 return 0;
108}
109
110static void realview_flash_exit(void)
111{
112 u32 val;
113
114 val = __raw_readl(REALVIEW_FLASHCTRL);
115 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
116 __raw_writel(val, REALVIEW_FLASHCTRL);
117}
118
119static void realview_flash_set_vpp(int on)
120{
121 u32 val;
122
123 val = __raw_readl(REALVIEW_FLASHCTRL);
124 if (on)
125 val |= REALVIEW_FLASHPROG_FLVPPEN;
126 else
127 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
128 __raw_writel(val, REALVIEW_FLASHCTRL);
129}
130
131static struct flash_platform_data realview_flash_data = {
132 .map_name = "cfi_probe",
133 .width = 4,
134 .init = realview_flash_init,
135 .exit = realview_flash_exit,
136 .set_vpp = realview_flash_set_vpp,
137};
138
8ad68bbf
CM		 139struct platform_device realview_flash_device = {
140 .name = "armflash",
141 .id = 0,
142 .dev = {
143 .platform_data = &realview_flash_data,
144 },
8ad68bbf
CM		 145};
146
a44ddfd5
CM		 147int realview_flash_register(struct resource *res, u32 num)
148{
149 realview_flash_device.resource = res;
150 realview_flash_device.num_resources = num;
151 return platform_device_register(&realview_flash_device);
152}
153
c5142e84
SG		 154static struct smsc911x_platform_config smsc911x_config = {
155 .flags = SMSC911X_USE_32BIT,
156 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
157 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
158 .phy_interface = PHY_INTERFACE_MODE_MII,
0a5b2f6b
CM		 159};
160
0a381330 161static struct platform_device realview_eth_device = {
c5142e84 162 .name = "smsc911x",
0a381330
CM		 163 .id = 0,
164 .num_resources = 2,
165};
166
167int realview_eth_register(const char *name, struct resource *res)
168{
169 if (name)
170 realview_eth_device.name = name;
171 realview_eth_device.resource = res;
c5142e84
SG		 172 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
173 realview_eth_device.dev.platform_data = &smsc911x_config;
0a381330
CM		 174
175 return platform_device_register(&realview_eth_device);
7db21712
CM		 176}
177
178struct platform_device realview_usb_device = {
179 .name = "isp1760",
180 .num_resources = 2,
181};
182
183int realview_usb_register(struct resource *res)
184{
185 realview_usb_device.resource = res;
186 return platform_device_register(&realview_usb_device);
0a381330
CM		 187}
188
6be62ba2
CM		 189static struct pata_platform_info pata_platform_data = {
190 .ioport_shift = 1,
191};
192
193static struct resource pata_resources[] = {
194 [0] = {
195 .start = REALVIEW_CF_BASE,
196 .end = REALVIEW_CF_BASE + 0xff,
197 .flags = IORESOURCE_MEM,
198 },
199 [1] = {
200 .start = REALVIEW_CF_BASE + 0x100,
201 .end = REALVIEW_CF_BASE + SZ_4K - 1,
202 .flags = IORESOURCE_MEM,
203 },
204};
205
206struct platform_device realview_cf_device = {
207 .name = "pata_platform",
208 .id = -1,
209 .num_resources = ARRAY_SIZE(pata_resources),
210 .resource = pata_resources,
211 .dev = {
212 .platform_data = &pata_platform_data,
213 },
214};
215
6b65cd74
RK		 216static struct resource realview_i2c_resource = {
217 .start = REALVIEW_I2C_BASE,
218 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
219 .flags = IORESOURCE_MEM,
220};
221
222struct platform_device realview_i2c_device = {
223 .name = "versatile-i2c",
533ad5e6 224 .id = 0,
6b65cd74
RK		 225 .num_resources = 1,
226 .resource = &realview_i2c_resource,
227};
228
533ad5e6
CM		 229static struct i2c_board_info realview_i2c_board_info[] = {
230 {
64e8be6e 231 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
533ad5e6
CM		 232 },
233};
234
235static int __init realview_i2c_init(void)
236{
237 return i2c_register_board_info(0, realview_i2c_board_info,
238 ARRAY_SIZE(realview_i2c_board_info));
239}
240arch_initcall(realview_i2c_init);
241
8ad68bbf
CM		 242#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
243
98b0979f
RK		 244/*
245 * This is only used if GPIOLIB support is disabled
246 */
8ad68bbf
CM		 247static unsigned int realview_mmc_status(struct device *dev)
248{
249 struct amba_device *adev = container_of(dev, struct amba_device, dev);
250 u32 mask;
251
252 if (adev->res.start == REALVIEW_MMCI0_BASE)
253 mask = 1;
254 else
255 mask = 2;
256
b56ba8aa 257 return !(readl(REALVIEW_SYSMCI) & mask);
8ad68bbf
CM		 258}
259
6ef297f8 260struct mmci_platform_data realview_mmc0_plat_data = {
8ad68bbf
CM		 261 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
262 .status = realview_mmc_status,
98b0979f
RK		 263 .gpio_wp = 17,
264 .gpio_cd = 16,
8ad68bbf
CM		 265};
266
6ef297f8 267struct mmci_platform_data realview_mmc1_plat_data = {
8ad68bbf
CM		 268 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
269 .status = realview_mmc_status,
98b0979f
RK		 270 .gpio_wp = 19,
271 .gpio_cd = 18,
8ad68bbf
CM		 272};
273
274/*
275 * Clock handling
276 */
277static const struct icst307_params realview_oscvco_params = {
278 .ref = 24000,
279 .vco_max = 200000,
280 .vd_min = 4 + 8,
281 .vd_max = 511 + 8,
282 .rd_min = 1 + 2,
283 .rd_max = 127 + 2,
284};
285
286static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
287{
288 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
68c3d935 289 void __iomem *sys_osc;
8ad68bbf
CM		 290 u32 val;
291
68c3d935
CT		 292 if (machine_is_realview_pb1176())
293 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
294 else
295 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
296
8ad68bbf
CM		 297 val = readl(sys_osc) & ~0x7ffff;
298 val |= vco.v | (vco.r << 9) | (vco.s << 16);
299
300 writel(0xa05f, sys_lock);
301 writel(val, sys_osc);
302 writel(0, sys_lock);
303}
304
cf30fb4a 305static struct clk oscvco_clk = {
8ad68bbf
CM		 306 .params = &realview_oscvco_params,
307 .setvco = realview_oscvco_set,
308};
309
cf30fb4a
RK		 310/*
311 * These are fixed clocks.
312 */
313static struct clk ref24_clk = {
314 .rate = 24000000,
315};
316
317static struct clk_lookup lookups[] = {
318 { /* UART0 */
4321532c 319 .dev_id = "dev:uart0",
cf30fb4a
RK		 320 .clk = &ref24_clk,
321 }, { /* UART1 */
4321532c 322 .dev_id = "dev:uart1",
cf30fb4a
RK		 323 .clk = &ref24_clk,
324 }, { /* UART2 */
4321532c 325 .dev_id = "dev:uart2",
cf30fb4a
RK		 326 .clk = &ref24_clk,
327 }, { /* UART3 */
4321532c 328 .dev_id = "fpga:uart3",
cf30fb4a
RK		 329 .clk = &ref24_clk,
330 }, { /* KMI0 */
4321532c 331 .dev_id = "fpga:kmi0",
cf30fb4a
RK		 332 .clk = &ref24_clk,
333 }, { /* KMI1 */
4321532c 334 .dev_id = "fpga:kmi1",
cf30fb4a
RK		 335 .clk = &ref24_clk,
336 }, { /* MMC0 */
4321532c 337 .dev_id = "fpga:mmc0",
cf30fb4a
RK		 338 .clk = &ref24_clk,
339 }, { /* EB:CLCD */
4321532c 340 .dev_id = "dev:clcd",
cf30fb4a
RK		 341 .clk = &oscvco_clk,
342 }, { /* PB:CLCD */
4321532c 343 .dev_id = "issp:clcd",
cf30fb4a
RK		 344 .clk = &oscvco_clk,
345 }
346};
347
348static int __init clk_init(void)
349{
0a0300dc 350 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
cf30fb4a
RK		 351 return 0;
352}
353arch_initcall(clk_init);
354
8ad68bbf
CM		 355/*
356 * CLCD support.
357 */
8ad68bbf
CM		 358#define SYS_CLCD_NLCDIOON (1 << 2)
359#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
360#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
361#define SYS_CLCD_ID_MASK (0x1f << 8)
362#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
363#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
364#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
365#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
366#define SYS_CLCD_ID_VGA (0x1f << 8)
367
368static struct clcd_panel vga = {
369 .mode = {
370 .name = "VGA",
371 .refresh = 60,
372 .xres = 640,
373 .yres = 480,
374 .pixclock = 39721,
375 .left_margin = 40,
376 .right_margin = 24,
377 .upper_margin = 32,
378 .lower_margin = 11,
379 .hsync_len = 96,
380 .vsync_len = 2,
381 .sync = 0,
382 .vmode = FB_VMODE_NONINTERLACED,
383 },
384 .width = -1,
385 .height = -1,
386 .tim2 = TIM2_BCD | TIM2_IPC,
4eccca20 387 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
8ad68bbf
CM		 388 .bpp = 16,
389};
390
c34a1025
CT		 391static struct clcd_panel xvga = {
392 .mode = {
393 .name = "XVGA",
394 .refresh = 60,
395 .xres = 1024,
396 .yres = 768,
397 .pixclock = 15748,
398 .left_margin = 152,
399 .right_margin = 48,
400 .upper_margin = 23,
401 .lower_margin = 3,
402 .hsync_len = 104,
403 .vsync_len = 4,
404 .sync = 0,
405 .vmode = FB_VMODE_NONINTERLACED,
406 },
407 .width = -1,
408 .height = -1,
409 .tim2 = TIM2_BCD | TIM2_IPC,
4eccca20 410 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
8ad68bbf
CM		 411 .bpp = 16,
412};
413
414static struct clcd_panel sanyo_3_8_in = {
415 .mode = {
416 .name = "Sanyo QVGA",
417 .refresh = 116,
418 .xres = 320,
419 .yres = 240,
420 .pixclock = 100000,
421 .left_margin = 6,
422 .right_margin = 6,
423 .upper_margin = 5,
424 .lower_margin = 5,
425 .hsync_len = 6,
426 .vsync_len = 6,
427 .sync = 0,
428 .vmode = FB_VMODE_NONINTERLACED,
429 },
430 .width = -1,
431 .height = -1,
432 .tim2 = TIM2_BCD,
4eccca20 433 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
8ad68bbf
CM		 434 .bpp = 16,
435};
436
437static struct clcd_panel sanyo_2_5_in = {
438 .mode = {
439 .name = "Sanyo QVGA Portrait",
440 .refresh = 116,
441 .xres = 240,
442 .yres = 320,
443 .pixclock = 100000,
444 .left_margin = 20,
445 .right_margin = 10,
446 .upper_margin = 2,
447 .lower_margin = 2,
448 .hsync_len = 10,
449 .vsync_len = 2,
450 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
451 .vmode = FB_VMODE_NONINTERLACED,
452 },
453 .width = -1,
454 .height = -1,
455 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
4eccca20 456 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
8ad68bbf
CM		 457 .bpp = 16,
458};
459
460static struct clcd_panel epson_2_2_in = {
461 .mode = {
462 .name = "Epson QCIF",
463 .refresh = 390,
464 .xres = 176,
465 .yres = 220,
466 .pixclock = 62500,
467 .left_margin = 3,
468 .right_margin = 2,
469 .upper_margin = 1,
470 .lower_margin = 0,
471 .hsync_len = 3,
472 .vsync_len = 2,
473 .sync = 0,
474 .vmode = FB_VMODE_NONINTERLACED,
475 },
476 .width = -1,
477 .height = -1,
478 .tim2 = TIM2_BCD | TIM2_IPC,
4eccca20 479 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
8ad68bbf
CM		 480 .bpp = 16,
481};
482
483/*
484 * Detect which LCD panel is connected, and return the appropriate
485 * clcd_panel structure. Note: we do not have any information on
486 * the required timings for the 8.4in panel, so we presently assume
487 * VGA timings.
488 */
489static struct clcd_panel *realview_clcd_panel(void)
490{
491 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
c34a1025
CT		 492 struct clcd_panel *vga_panel;
493 struct clcd_panel *panel;
8ad68bbf
CM		 494 u32 val;
495
c34a1025
CT		 496 if (machine_is_realview_eb())
497 vga_panel = &vga;
498 else
499 vga_panel = &xvga;
500
8ad68bbf
CM		 501 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
502 if (val == SYS_CLCD_ID_SANYO_3_8)
503 panel = &sanyo_3_8_in;
504 else if (val == SYS_CLCD_ID_SANYO_2_5)
505 panel = &sanyo_2_5_in;
506 else if (val == SYS_CLCD_ID_EPSON_2_2)
507 panel = &epson_2_2_in;
508 else if (val == SYS_CLCD_ID_VGA)
c34a1025 509 panel = vga_panel;
8ad68bbf
CM		 510 else {
511 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
512 val);
c34a1025 513 panel = vga_panel;
8ad68bbf
CM		 514 }
515
516 return panel;
517}
518
519/*
520 * Disable all display connectors on the interface module.
521 */
522static void realview_clcd_disable(struct clcd_fb *fb)
523{
524 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
525 u32 val;
526
527 val = readl(sys_clcd);
528 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
529 writel(val, sys_clcd);
530}
531
532/*
533 * Enable the relevant connector on the interface module.
534 */
535static void realview_clcd_enable(struct clcd_fb *fb)
536{
537 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
538 u32 val;
539
8ad68bbf 540 /*
9e7714d0 541 * Enable the PSUs
8ad68bbf 542 */
9e7714d0 543 val = readl(sys_clcd);
8ad68bbf
CM		 544 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
545 writel(val, sys_clcd);
546}
547
8ad68bbf
CM		 548static int realview_clcd_setup(struct clcd_fb *fb)
549{
c34a1025 550 unsigned long framesize;
8ad68bbf
CM		 551 dma_addr_t dma;
552
c34a1025
CT		 553 if (machine_is_realview_eb())
554 /* VGA, 16bpp */
555 framesize = 640 * 480 * 2;
556 else
557 /* XVGA, 16bpp */
558 framesize = 1024 * 768 * 2;
559
8ad68bbf
CM		 560 fb->panel = realview_clcd_panel();
561
562 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
c97c5aa8 563 &dma, GFP_KERNEL | GFP_DMA);
8ad68bbf
CM		 564 if (!fb->fb.screen_base) {
565 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
566 return -ENOMEM;
567 }
568
569 fb->fb.fix.smem_start = dma;
570 fb->fb.fix.smem_len = framesize;
571
572 return 0;
573}
574
575static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
576{
577 return dma_mmap_writecombine(&fb->dev->dev, vma,
578 fb->fb.screen_base,
579 fb->fb.fix.smem_start,
580 fb->fb.fix.smem_len);
581}
582
583static void realview_clcd_remove(struct clcd_fb *fb)
584{
585 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
586 fb->fb.screen_base, fb->fb.fix.smem_start);
587}
588
589struct clcd_board clcd_plat_data = {
590 .name = "RealView",
591 .check = clcdfb_check,
592 .decode = clcdfb_decode,
593 .disable = realview_clcd_disable,
594 .enable = realview_clcd_enable,
595 .setup = realview_clcd_setup,
596 .mmap = realview_clcd_mmap,
597 .remove = realview_clcd_remove,
598};
599
600#ifdef CONFIG_LEDS
601#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
602
603void realview_leds_event(led_event_t ledevt)
604{
605 unsigned long flags;
606 u32 val;
da055eb5 607 u32 led = 1 << smp_processor_id();
8ad68bbf
CM		 608
609 local_irq_save(flags);
610 val = readl(VA_LEDS_BASE);
611
612 switch (ledevt) {
613 case led_idle_start:
da055eb5 614 val = val & ~led;
8ad68bbf
CM		 615 break;
616
617 case led_idle_end:
da055eb5 618 val = val | led;
8ad68bbf
CM		 619 break;
620
621 case led_timer:
da055eb5 622 val = val ^ REALVIEW_SYS_LED7;
8ad68bbf
CM		 623 break;
624
625 case led_halted:
626 val = 0;
627 break;
628
629 default:
630 break;
631 }
632
633 writel(val, VA_LEDS_BASE);
634 local_irq_restore(flags);
635}
636#endif /* CONFIG_LEDS */
637
638/*
639 * Where is the timer (VA)?
640 */
80192735
CM		 641void __iomem *timer0_va_base;
642void __iomem *timer1_va_base;
643void __iomem *timer2_va_base;
644void __iomem *timer3_va_base;
8ad68bbf
CM		 645
646/*
647 * How long is the timer interval?
648 */
649#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
650#if TIMER_INTERVAL >= 0x100000
651#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
652#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
653#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
654#elif TIMER_INTERVAL >= 0x10000
655#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
656#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
657#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
658#else
659#define TIMER_RELOAD (TIMER_INTERVAL)
660#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
661#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
662#endif
663
ae30ceac
CM		 664static void timer_set_mode(enum clock_event_mode mode,
665 struct clock_event_device *clk)
666{
667 unsigned long ctrl;
668
669 switch(mode) {
670 case CLOCK_EVT_MODE_PERIODIC:
80192735 671 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
ae30ceac
CM		 672
673 ctrl = TIMER_CTRL_PERIODIC;
674 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
675 break;
676 case CLOCK_EVT_MODE_ONESHOT:
677 /* period set, and timer enabled in 'next_event' hook */
678 ctrl = TIMER_CTRL_ONESHOT;
679 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
680 break;
681 case CLOCK_EVT_MODE_UNUSED:
682 case CLOCK_EVT_MODE_SHUTDOWN:
683 default:
684 ctrl = 0;
685 }
686
80192735 687 writel(ctrl, timer0_va_base + TIMER_CTRL);
ae30ceac
CM		 688}
689
690static int timer_set_next_event(unsigned long evt,
691 struct clock_event_device *unused)
692{
80192735 693 unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
ae30ceac 694
80192735
CM		 695 writel(evt, timer0_va_base + TIMER_LOAD);
696 writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
ae30ceac
CM		 697
698 return 0;
699}
700
701static struct clock_event_device timer0_clockevent = {
702 .name = "timer0",
703 .shift = 32,
704 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
705 .set_mode = timer_set_mode,
706 .set_next_event = timer_set_next_event,
707 .rating = 300,
320ab2b0 708 .cpumask = cpu_all_mask,
ae30ceac
CM		 709};
710
8cc4c548 711static void __init realview_clockevents_init(unsigned int timer_irq)
ae30ceac 712{
8cc4c548 713 timer0_clockevent.irq = timer_irq;
ae30ceac
CM		 714 timer0_clockevent.mult =
715 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
716 timer0_clockevent.max_delta_ns =
717 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
718 timer0_clockevent.min_delta_ns =
719 clockevent_delta2ns(0xf, &timer0_clockevent);
720
721 clockevents_register_device(&timer0_clockevent);
722}
723
8ad68bbf
CM		 724/*
725 * IRQ handler for the timer
726 */
0cd61b68 727static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
8ad68bbf 728{
ae30ceac 729 struct clock_event_device *evt = &timer0_clockevent;
8ad68bbf 730
ae30ceac 731 /* clear the interrupt */
80192735 732 writel(1, timer0_va_base + TIMER_INTCLR);
8ad68bbf 733
ae30ceac 734 evt->event_handler(evt);
dbebb4cb 735
8ad68bbf
CM		 736 return IRQ_HANDLED;
737}
738
739static struct irqaction realview_timer_irq = {
740 .name = "RealView Timer Tick",
b30fabad 741 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
8ad68bbf
CM		 742 .handler = realview_timer_interrupt,
743};
744
8e19608e 745static cycle_t realview_get_cycles(struct clocksource *cs)
85802afe 746{
80192735 747 return ~readl(timer3_va_base + TIMER_VALUE);
85802afe
CM		 748}
749
750static struct clocksource clocksource_realview = {
751 .name = "timer3",
752 .rating = 200,
753 .read = realview_get_cycles,
754 .mask = CLOCKSOURCE_MASK(32),
755 .shift = 20,
756 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
757};
758
759static void __init realview_clocksource_init(void)
760{
761 /* setup timer 0 as free-running clocksource */
80192735
CM		 762 writel(0, timer3_va_base + TIMER_CTRL);
763 writel(0xffffffff, timer3_va_base + TIMER_LOAD);
764 writel(0xffffffff, timer3_va_base + TIMER_VALUE);
85802afe 765 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
80192735 766 timer3_va_base + TIMER_CTRL);
85802afe
CM		 767
768 clocksource_realview.mult =
769 clocksource_khz2mult(1000, clocksource_realview.shift);
770 clocksource_register(&clocksource_realview);
771}
772
8ad68bbf 773/*
a8655e83 774 * Set up the clock source and clock events devices
8ad68bbf 775 */
8cc4c548 776void __init realview_timer_init(unsigned int timer_irq)
8ad68bbf
CM		 777{
778 u32 val;
779
780 /*
781 * set clock frequency:
782 * REALVIEW_REFCLK is 32KHz
783 * REALVIEW_TIMCLK is 1MHz
784 */
785 val = readl(__io_address(REALVIEW_SCTL_BASE));
786 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
787 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
788 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
789 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
790 __io_address(REALVIEW_SCTL_BASE));
791
792 /*
793 * Initialise to a known state (all timers off)
794 */
80192735
CM		 795 writel(0, timer0_va_base + TIMER_CTRL);
796 writel(0, timer1_va_base + TIMER_CTRL);
797 writel(0, timer2_va_base + TIMER_CTRL);
798 writel(0, timer3_va_base + TIMER_CTRL);
8ad68bbf 799
8ad68bbf
CM		 800 /*
801 * Make irqs happen for the system timer
802 */
8cc4c548 803 setup_irq(timer_irq, &realview_timer_irq);
85802afe
CM		 804
805 realview_clocksource_init();
8cc4c548 806 realview_clockevents_init(timer_irq);
8ad68bbf 807}
5b39d154
CM		 808
809/*
810 * Setup the memory banks.
811 */
812void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
813 struct meminfo *meminfo)
814{
815 /*
816 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
817 * Half of this is mirrored at 0.
818 */
819#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
820 meminfo->bank[0].start = 0x70000000;
821 meminfo->bank[0].size = SZ_512M;
822 meminfo->nr_banks = 1;
823#else
824 meminfo->bank[0].start = 0;
825 meminfo->bank[0].size = SZ_256M;
826 meminfo->nr_banks = 1;
827#endif
828}
kernel source for telekom puls (alcatel/mediatek)