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1da177e4 | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-pxa/include/mach/hardware.h |
1da177e4 LT |
3 | * |
4 | * Author: Nicolas Pitre | |
5 | * Created: Jun 15, 2001 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_ARCH_HARDWARE_H | |
14 | #define __ASM_ARCH_HARDWARE_H | |
15 | ||
16 | /* | |
17 | * We requires absolute addresses. | |
18 | */ | |
19 | #define PCIO_BASE 0 | |
20 | ||
21 | /* | |
22 | * Workarounds for at least 2 errata so far require this. | |
23 | * The mapping is set in mach-pxa/generic.c. | |
24 | */ | |
25 | #define UNCACHED_PHYS_0 0xff000000 | |
26 | #define UNCACHED_ADDR UNCACHED_PHYS_0 | |
27 | ||
28 | /* | |
29 | * Intel PXA2xx internal register mapping: | |
30 | * | |
31 | * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff | |
32 | * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff | |
33 | * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff | |
34 | * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff | |
35 | * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff | |
36 | * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff | |
37 | * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff | |
38 | * | |
39 | * Note that not all PXA2xx chips implement all those addresses, and the | |
40 | * kernel only maps the minimum needed range of this mapping. | |
41 | */ | |
42 | #define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) | |
43 | #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) | |
44 | ||
45 | #ifndef __ASSEMBLY__ | |
46 | ||
63a4b52c | 47 | # define __REG(x) (*((volatile u32 *)io_p2v(x))) |
1da177e4 LT |
48 | |
49 | /* With indexed regs we don't want to feed the index through io_p2v() | |
50 | especially if it is a variable, otherwise horrible code will result. */ | |
61c8c158 | 51 | # define __REG2(x,y) \ |
63a4b52c | 52 | (*(volatile u32 *)((u32)&__REG(x) + (y))) |
1da177e4 LT |
53 | |
54 | # define __PREG(x) (io_v2p((u32)&(x))) | |
55 | ||
56 | #else | |
57 | ||
58 | # define __REG(x) io_p2v(x) | |
59 | # define __PREG(x) io_v2p(x) | |
60 | ||
61 | #endif | |
62 | ||
63 | #ifndef __ASSEMBLY__ | |
64 | ||
0ba8b9b2 RK |
65 | #include <asm/cputype.h> |
66 | ||
36d8b17b | 67 | #ifdef CONFIG_PXA25x |
b23170c0 RK |
68 | #define __cpu_is_pxa21x(id) \ |
69 | ({ \ | |
70 | unsigned int _id = (id) >> 4 & 0xf3f; \ | |
71 | _id == 0x212; \ | |
72 | }) | |
73 | ||
aa9ae8eb IM |
74 | #define __cpu_is_pxa255(id) \ |
75 | ({ \ | |
76 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
77 | _id == 0x2d0; \ | |
78 | }) | |
79 | ||
b23170c0 RK |
80 | #define __cpu_is_pxa25x(id) \ |
81 | ({ \ | |
82 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
83 | _id == 0x2d0 || _id == 0x290; \ | |
84 | }) | |
36d8b17b RK |
85 | #else |
86 | #define __cpu_is_pxa21x(id) (0) | |
aa9ae8eb | 87 | #define __cpu_is_pxa255(id) (0) |
36d8b17b RK |
88 | #define __cpu_is_pxa25x(id) (0) |
89 | #endif | |
b23170c0 | 90 | |
36d8b17b | 91 | #ifdef CONFIG_PXA27x |
b23170c0 RK |
92 | #define __cpu_is_pxa27x(id) \ |
93 | ({ \ | |
94 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
95 | _id == 0x411; \ | |
96 | }) | |
36d8b17b RK |
97 | #else |
98 | #define __cpu_is_pxa27x(id) (0) | |
99 | #endif | |
b23170c0 | 100 | |
36d8b17b | 101 | #ifdef CONFIG_CPU_PXA300 |
cd272ab0 | 102 | #define __cpu_is_pxa300(id) \ |
103 | ({ \ | |
104 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
105 | _id == 0x688; \ | |
106 | }) | |
36d8b17b RK |
107 | #else |
108 | #define __cpu_is_pxa300(id) (0) | |
109 | #endif | |
cd272ab0 | 110 | |
36d8b17b | 111 | #ifdef CONFIG_CPU_PXA310 |
cd272ab0 | 112 | #define __cpu_is_pxa310(id) \ |
113 | ({ \ | |
114 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
115 | _id == 0x689; \ | |
116 | }) | |
36d8b17b RK |
117 | #else |
118 | #define __cpu_is_pxa310(id) (0) | |
119 | #endif | |
cd272ab0 | 120 | |
36d8b17b | 121 | #ifdef CONFIG_CPU_PXA320 |
cd272ab0 | 122 | #define __cpu_is_pxa320(id) \ |
123 | ({ \ | |
124 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
125 | _id == 0x603 || _id == 0x682; \ | |
126 | }) | |
36d8b17b RK |
127 | #else |
128 | #define __cpu_is_pxa320(id) (0) | |
129 | #endif | |
cd272ab0 | 130 | |
5d31e435 EM |
131 | #ifdef CONFIG_CPU_PXA930 |
132 | #define __cpu_is_pxa930(id) \ | |
133 | ({ \ | |
134 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
135 | _id == 0x683; \ | |
136 | }) | |
137 | #else | |
138 | #define __cpu_is_pxa930(id) (0) | |
139 | #endif | |
140 | ||
b23170c0 RK |
141 | #define cpu_is_pxa21x() \ |
142 | ({ \ | |
198a6d5a | 143 | __cpu_is_pxa21x(read_cpuid_id()); \ |
b23170c0 RK |
144 | }) |
145 | ||
aa9ae8eb IM |
146 | #define cpu_is_pxa255() \ |
147 | ({ \ | |
148 | __cpu_is_pxa255(read_cpuid_id()); \ | |
149 | }) | |
150 | ||
b23170c0 RK |
151 | #define cpu_is_pxa25x() \ |
152 | ({ \ | |
198a6d5a | 153 | __cpu_is_pxa25x(read_cpuid_id()); \ |
b23170c0 RK |
154 | }) |
155 | ||
156 | #define cpu_is_pxa27x() \ | |
157 | ({ \ | |
198a6d5a | 158 | __cpu_is_pxa27x(read_cpuid_id()); \ |
b23170c0 RK |
159 | }) |
160 | ||
cd272ab0 | 161 | #define cpu_is_pxa300() \ |
162 | ({ \ | |
198a6d5a | 163 | __cpu_is_pxa300(read_cpuid_id()); \ |
cd272ab0 | 164 | }) |
165 | ||
166 | #define cpu_is_pxa310() \ | |
167 | ({ \ | |
198a6d5a | 168 | __cpu_is_pxa310(read_cpuid_id()); \ |
cd272ab0 | 169 | }) |
170 | ||
171 | #define cpu_is_pxa320() \ | |
172 | ({ \ | |
198a6d5a | 173 | __cpu_is_pxa320(read_cpuid_id()); \ |
cd272ab0 | 174 | }) |
175 | ||
5d31e435 EM |
176 | #define cpu_is_pxa930() \ |
177 | ({ \ | |
178 | unsigned int id = read_cpuid(CPUID_ID); \ | |
179 | __cpu_is_pxa930(id); \ | |
180 | }) | |
181 | ||
cd272ab0 | 182 | /* |
183 | * CPUID Core Generation Bit | |
184 | * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x | |
185 | * == 0x3 for pxa300/pxa310/pxa320 | |
186 | */ | |
187 | #define __cpu_is_pxa2xx(id) \ | |
188 | ({ \ | |
189 | unsigned int _id = (id) >> 13 & 0x7; \ | |
190 | _id <= 0x2; \ | |
191 | }) | |
192 | ||
193 | #define __cpu_is_pxa3xx(id) \ | |
194 | ({ \ | |
195 | unsigned int _id = (id) >> 13 & 0x7; \ | |
196 | _id == 0x3; \ | |
197 | }) | |
198 | ||
199 | #define cpu_is_pxa2xx() \ | |
200 | ({ \ | |
198a6d5a | 201 | __cpu_is_pxa2xx(read_cpuid_id()); \ |
cd272ab0 | 202 | }) |
203 | ||
204 | #define cpu_is_pxa3xx() \ | |
205 | ({ \ | |
198a6d5a | 206 | __cpu_is_pxa3xx(read_cpuid_id()); \ |
cd272ab0 | 207 | }) |
208 | ||
1da177e4 LT |
209 | /* |
210 | * Handy routine to set GPIO alternate functions | |
211 | */ | |
3deac046 PZ |
212 | extern int pxa_gpio_mode( int gpio_mode ); |
213 | ||
214 | /* | |
215 | * Return GPIO level, nonzero means high, zero is low | |
216 | */ | |
217 | extern int pxa_gpio_get_value(unsigned gpio); | |
218 | ||
219 | /* | |
220 | * Set output GPIO level | |
221 | */ | |
222 | extern void pxa_gpio_set_value(unsigned gpio, int value); | |
1da177e4 | 223 | |
1da177e4 LT |
224 | /* |
225 | * return current memory and LCD clock frequency in units of 10kHz | |
226 | */ | |
227 | extern unsigned int get_memclk_frequency_10khz(void); | |
1da177e4 LT |
228 | |
229 | #endif | |
230 | ||
3696a8a4 MR |
231 | #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) |
232 | #define PCIBIOS_MIN_IO 0 | |
233 | #define PCIBIOS_MIN_MEM 0 | |
234 | #define pcibios_assign_all_busses() 1 | |
235 | #endif | |
236 | ||
1da177e4 | 237 | #endif /* _ASM_ARCH_HARDWARE_H */ |