[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-orion5x / pci.c

/*
 * arch/arm/mach-orion5x/pci.c
 *
 * PCI and PCIe functions for Marvell Orion System On Chip
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/mbus.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include "common.h"

/*****************************************************************************
 * Orion has one PCIe controller and one PCI controller.
 *
 * Note1: The local PCIe bus number is '0'. The local PCI bus number
 * follows the scanned PCIe bridged busses, if any.
 *
 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
 * device bus, Orion registers, etc. However this code only enable the
 * access to DDR banks.
 ****************************************************************************/


/*****************************************************************************
 * PCIe controller
 ****************************************************************************/
#define PCIE_BASE	((void __iomem *)ORION5X_PCIE_VIRT_BASE)

void __init orion5x_pcie_id(u32 *dev, u32 *rev)
{
	*dev = orion_pcie_dev_id(PCIE_BASE);
	*rev = orion_pcie_rev(PCIE_BASE);
}

static int pcie_valid_config(int bus, int dev)
{
	/*
	 * Don't go out when trying to access --
	 * 1. nonexisting device on local bus
	 * 2. where there's no device connected (no link)
	 */
	if (bus == 0 && dev == 0)
		return 1;

	if (!orion_pcie_link_up(PCIE_BASE))
		return 0;

	if (bus == 0 && dev != 1)
		return 0;

	return 1;
}


/*
 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
 * and then reading the PCIE_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
static DEFINE_SPINLOCK(orion5x_pcie_lock);

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
	unsigned long flags;
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&orion5x_pcie_lock, flags);
	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);

	return ret;
}

static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
			   int where, int size, u32 *val)
{
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	/*
	 * We only support access to the non-extended configuration
	 * space when using the WA access method (or we would have to
	 * sacrifice 256M of CPU virtual address space.)
	 */
	if (where >= 0x100) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
				    bus, devfn, where, size, val);

	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
	unsigned long flags;
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&orion5x_pcie_lock, flags);
	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);

	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};


static int __init pcie_setup(struct pci_sys_data *sys)
{
	struct resource *res;
	int dev;

	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);

	/*
	 * Check whether to apply Orion-1/Orion-NAS PCIe config
	 * read transaction workaround.
	 */
	dev = orion_pcie_dev_id(PCIE_BASE);
	if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
		printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
				   "read transaction workaround\n");
		orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
					  ORION5X_PCIE_WA_SIZE);
		pcie_ops.read = pcie_rd_conf_wa;
	}

	/*
	 * Request resources.
	 */
	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	if (!res)
		panic("pcie_setup unable to alloc resources");

	/*
	 * IORESOURCE_IO
	 */
	res[0].name = "PCIe I/O Space";
	res[0].flags = IORESOURCE_IO;
	res[0].start = ORION5X_PCIE_IO_BUS_BASE;
	res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
	if (request_resource(&ioport_resource, &res[0]))
		panic("Request PCIe IO resource failed\n");
	sys->resource[0] = &res[0];

	/*
	 * IORESOURCE_MEM
	 */
	res[1].name = "PCIe Memory Space";
	res[1].flags = IORESOURCE_MEM;
	res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
	res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
	if (request_resource(&iomem_resource, &res[1]))
		panic("Request PCIe Memory resource failed\n");
	sys->resource[1] = &res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}

/*****************************************************************************
 * PCI controller
 ****************************************************************************/
#define ORION5X_PCI_REG(x)	(ORION5X_PCI_VIRT_BASE | (x))
#define PCI_MODE		ORION5X_PCI_REG(0xd00)
#define PCI_CMD			ORION5X_PCI_REG(0xc00)
#define PCI_P2P_CONF		ORION5X_PCI_REG(0x1d14)
#define PCI_CONF_ADDR		ORION5X_PCI_REG(0xc78)
#define PCI_CONF_DATA		ORION5X_PCI_REG(0xc7c)

/*
 * PCI_MODE bits
 */
#define PCI_MODE_64BIT			(1 << 2)
#define PCI_MODE_PCIX			((1 << 4) | (1 << 5))

/*
 * PCI_CMD bits
 */
#define PCI_CMD_HOST_REORDER		(1 << 29)

/*
 * PCI_P2P_CONF bits
 */
#define PCI_P2P_BUS_OFFS		16
#define PCI_P2P_BUS_MASK		(0xff << PCI_P2P_BUS_OFFS)
#define PCI_P2P_DEV_OFFS		24
#define PCI_P2P_DEV_MASK		(0x1f << PCI_P2P_DEV_OFFS)

/*
 * PCI_CONF_ADDR bits
 */
#define PCI_CONF_REG(reg)		((reg) & 0xfc)
#define PCI_CONF_FUNC(func)		(((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev)		(((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus)		(((bus) & 0xff) << 16)
#define PCI_CONF_ADDR_EN		(1 << 31)

/*
 * Internal configuration space
 */
#define PCI_CONF_FUNC_STAT_CMD		0
#define PCI_CONF_REG_STAT_CMD		4
#define PCIX_STAT			0x64
#define PCIX_STAT_BUS_OFFS		8
#define PCIX_STAT_BUS_MASK		(0xff << PCIX_STAT_BUS_OFFS)

/*
 * PCI Address Decode Windows registers
 */
#define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
				 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
				 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
				 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
#define PCI_BAR_REMAP_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
				 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
				 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
				 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
#define PCI_BAR_ENABLE		ORION5X_PCI_REG(0xc3c)
#define PCI_ADDR_DECODE_CTRL	ORION5X_PCI_REG(0xd3c)

/*
 * PCI configuration helpers for BAR settings
 */
#define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
#define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
#define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)

/*
 * PCI config cycles are done by programming the PCI_CONF_ADDR register
 * and then reading the PCI_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
static DEFINE_SPINLOCK(orion5x_pci_lock);

static int orion5x_pci_cardbus_mode;

static int orion5x_pci_local_bus_nr(void)
{
	u32 conf = readl(PCI_P2P_CONF);
	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
}

static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
					u32 where, u32 size, u32 *val)
{
	unsigned long flags;
	spin_lock_irqsave(&orion5x_pci_lock, flags);

	writel(PCI_CONF_BUS(bus) |
		PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
		PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);

	*val = readl(PCI_CONF_DATA);

	if (size == 1)
		*val = (*val >> (8*(where & 0x3))) & 0xff;
	else if (size == 2)
		*val = (*val >> (8*(where & 0x3))) & 0xffff;

	spin_unlock_irqrestore(&orion5x_pci_lock, flags);

	return PCIBIOS_SUCCESSFUL;
}

static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
					u32 where, u32 size, u32 val)
{
	unsigned long flags;
	int ret = PCIBIOS_SUCCESSFUL;

	spin_lock_irqsave(&orion5x_pci_lock, flags);

	writel(PCI_CONF_BUS(bus) |
		PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
		PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);

	if (size == 4) {
		__raw_writel(val, PCI_CONF_DATA);
	} else if (size == 2) {
		__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
	} else if (size == 1) {
		__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
	} else {
		ret = PCIBIOS_BAD_REGISTER_NUMBER;
	}

	spin_unlock_irqrestore(&orion5x_pci_lock, flags);

	return ret;
}

static int orion5x_pci_valid_config(int bus, u32 devfn)
{
	if (bus == orion5x_pci_local_bus_nr()) {
		/*
		 * Don't go out for local device
		 */
		if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
			return 0;

		/*
		 * When the PCI signals are directly connected to a
		 * Cardbus slot, ignore all but device IDs 0 and 1.
		 */
		if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
			return 0;
	}

	return 1;
}

static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
				int where, int size, u32 *val)
{
	if (!orion5x_pci_valid_config(bus->number, devfn)) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
					PCI_FUNC(devfn), where, size, val);
}

static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
				int where, int size, u32 val)
{
	if (!orion5x_pci_valid_config(bus->number, devfn))
		return PCIBIOS_DEVICE_NOT_FOUND;

	return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
					PCI_FUNC(devfn), where, size, val);
}

static struct pci_ops pci_ops = {
	.read = orion5x_pci_rd_conf,
	.write = orion5x_pci_wr_conf,
};

static void __init orion5x_pci_set_bus_nr(int nr)
{
	u32 p2p = readl(PCI_P2P_CONF);

	if (readl(PCI_MODE) & PCI_MODE_PCIX) {
		/*
		 * PCI-X mode
		 */
		u32 pcix_status, bus, dev;
		bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
		dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
		orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
		pcix_status &= ~PCIX_STAT_BUS_MASK;
		pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
		orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
	} else {
		/*
		 * PCI Conventional mode
		 */
		p2p &= ~PCI_P2P_BUS_MASK;
		p2p |= (nr << PCI_P2P_BUS_OFFS);
		writel(p2p, PCI_P2P_CONF);
	}
}

static void __init orion5x_pci_master_slave_enable(void)
{
	int bus_nr, func, reg;
	u32 val;

	bus_nr = orion5x_pci_local_bus_nr();
	func = PCI_CONF_FUNC_STAT_CMD;
	reg = PCI_CONF_REG_STAT_CMD;
	orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
	val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
	orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
}

static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
{
	u32 win_enable;
	int bus;
	int i;

	/*
	 * First, disable windows.
	 */
	win_enable = 0xffffffff;
	writel(win_enable, PCI_BAR_ENABLE);

	/*
	 * Setup windows for DDR banks.
	 */
	bus = orion5x_pci_local_bus_nr();

	for (i = 0; i < dram->num_cs; i++) {
		struct mbus_dram_window *cs = dram->cs + i;
		u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
		u32 reg;
		u32 val;

		/*
		 * Write DRAM bank base address register.
		 */
		reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
		orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
		val = (cs->base & 0xfffff000) | (val & 0xfff);
		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);

		/*
		 * Write DRAM bank size register.
		 */
		reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
		writel((cs->size - 1) & 0xfffff000,
			PCI_BAR_SIZE_DDR_CS(cs->cs_index));
		writel(cs->base & 0xfffff000,
			PCI_BAR_REMAP_DDR_CS(cs->cs_index));

		/*
		 * Enable decode window for this chip select.
		 */
		win_enable &= ~(1 << cs->cs_index);
	}

	/*
	 * Re-enable decode windows.
	 */
	writel(win_enable, PCI_BAR_ENABLE);

	/*
	 * Disable automatic update of address remapping when writing to BARs.
	 */
	orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
}

static int __init pci_setup(struct pci_sys_data *sys)
{
	struct resource *res;

	/*
	 * Point PCI unit MBUS decode windows to DRAM space.
	 */
	orion5x_setup_pci_wins(&orion5x_mbus_dram_info);

	/*
	 * Master + Slave enable
	 */
	orion5x_pci_master_slave_enable();

	/*
	 * Force ordering
	 */
	orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);

	/*
	 * Request resources
	 */
	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	if (!res)
		panic("pci_setup unable to alloc resources");

	/*
	 * IORESOURCE_IO
	 */
	res[0].name = "PCI I/O Space";
	res[0].flags = IORESOURCE_IO;
	res[0].start = ORION5X_PCI_IO_BUS_BASE;
	res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
	if (request_resource(&ioport_resource, &res[0]))
		panic("Request PCI IO resource failed\n");
	sys->resource[0] = &res[0];

	/*
	 * IORESOURCE_MEM
	 */
	res[1].name = "PCI Memory Space";
	res[1].flags = IORESOURCE_MEM;
	res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
	res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
	if (request_resource(&iomem_resource, &res[1]))
		panic("Request PCI Memory resource failed\n");
	sys->resource[1] = &res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}


/*****************************************************************************
 * General PCIe + PCI
 ****************************************************************************/
static void __devinit rc_pci_fixup(struct pci_dev *dev)
{
	/*
	 * Prevent enumeration of root complex.
	 */
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

static int orion5x_pci_disabled __initdata;

void __init orion5x_pci_disable(void)
{
	orion5x_pci_disabled = 1;
}

void __init orion5x_pci_set_cardbus_mode(void)
{
	orion5x_pci_cardbus_mode = 1;
}

int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
{
	int ret = 0;

	if (nr == 0) {
		orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
		ret = pcie_setup(sys);
	} else if (nr == 1 && !orion5x_pci_disabled) {
		orion5x_pci_set_bus_nr(sys->busnr);
		ret = pci_setup(sys);
	}

	return ret;
}

struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
{
	struct pci_bus *bus;

	if (nr == 0) {
		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
	} else if (nr == 1 && !orion5x_pci_disabled) {
		bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
	} else {
		bus = NULL;
		BUG();
	}

	return bus;
}

int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	int bus = dev->bus->number;

	/*
	 * PCIe endpoint?
	 */
	if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
		return IRQ_ORION5X_PCIE0_INT;

	return -1;
}
Commit	Line	Data
038ee083	1	/*
9dd0b194	2	* arch/arm/mach-orion5x/pci.c
038ee083	3	*
159ffb3a	4	* PCI and PCIe functions for Marvell Orion System On Chip
038ee083 TP	5	*
	6	* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
	7	*
159ffb3a LB	8	* This file is licensed under the terms of the GNU General Public
159ffb3a LB	9	* License version 2. This program is licensed "as is" without any
038ee083 TP	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
5a0e3ad6	15	#include <linux/slab.h>
1f2223b1	16	#include <linux/mbus.h>
ff89c462	17	#include <asm/irq.h>
038ee083	18	#include <asm/mach/pci.h>
6f088f1d	19	#include <plat/pcie.h>
038ee083 TP	20	#include "common.h"
	21
	22	/*****************************************************************************
159ffb3a	23	* Orion has one PCIe controller and one PCI controller.
038ee083	24	*
159ffb3a LB	25	* Note1: The local PCIe bus number is '0'. The local PCI bus number
159ffb3a LB	26	* follows the scanned PCIe bridged busses, if any.
038ee083	27	*
159ffb3a	28	* Note2: It is possible for PCI/PCIe agents to access many subsystem's
038ee083 TP	29	* space, by configuring BARs and Address Decode Windows, e.g. flashes on
	30	* device bus, Orion registers, etc. However this code only enable the
	31	* access to DDR banks.
	32	****************************************************************************/
	33
	34
	35	/*****************************************************************************
159ffb3a	36	* PCIe controller
038ee083	37	****************************************************************************/
9dd0b194	38	#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
038ee083	39
9dd0b194	40	void __init orion5x_pcie_id(u32 dev, u32 rev)
038ee083	41	{
abc0197d LB	42	*dev = orion_pcie_dev_id(PCIE_BASE);
abc0197d LB	43	*rev = orion_pcie_rev(PCIE_BASE);
038ee083 TP	44	}
038ee083 TP	45
abc0197d	46	static int pcie_valid_config(int bus, int dev)
038ee083 TP	47	{
	48	/*
	49	* Don't go out when trying to access --
d50c60a8	50	* 1. nonexisting device on local bus
038ee083	51	* 2. where there's no device connected (no link)
038ee083	52	*/
d50c60a8 LB	53	if (bus == 0 && dev == 0)
d50c60a8 LB	54	return 1;
038ee083	55
abc0197d	56	if (!orion_pcie_link_up(PCIE_BASE))
038ee083 TP	57	return 0;
038ee083 TP	58
d50c60a8 LB	59	if (bus == 0 && dev != 1)
	60	return 0;
	61
038ee083 TP	62	return 1;
	63	}
	64
abc0197d LB	65
abc0197d LB	66	/*
159ffb3a	67	* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
abc0197d LB	68	* and then reading the PCIE_CONF_DATA register. Need to make sure these
	69	* transactions are atomic.
	70	*/
9dd0b194	71	static DEFINE_SPINLOCK(orion5x_pcie_lock);
abc0197d LB	72
	73	static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
	74	int size, u32 *val)
038ee083 TP	75	{
038ee083 TP	76	unsigned long flags;
abc0197d	77	int ret;
038ee083	78
abc0197d	79	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
038ee083 TP	80	*val = 0xffffffff;
	81	return PCIBIOS_DEVICE_NOT_FOUND;
	82	}
	83
9dd0b194	84	spin_lock_irqsave(&orion5x_pcie_lock, flags);
abc0197d	85	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
9dd0b194	86	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
038ee083	87
abc0197d LB	88	return ret;
abc0197d LB	89	}
038ee083	90
abc0197d LB	91	static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
	92	int where, int size, u32 *val)
	93	{
	94	int ret;
038ee083	95
abc0197d LB	96	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
	97	*val = 0xffffffff;
	98	return PCIBIOS_DEVICE_NOT_FOUND;
	99	}
038ee083	100
abc0197d LB	101	/*
	102	* We only support access to the non-extended configuration
	103	* space when using the WA access method (or we would have to
	104	* sacrifice 256M of CPU virtual address space.)
	105	*/
	106	if (where >= 0x100) {
	107	*val = 0xffffffff;
	108	return PCIBIOS_DEVICE_NOT_FOUND;
	109	}
038ee083	110
9dd0b194	111	ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
abc0197d	112	bus, devfn, where, size, val);
038ee083	113
abc0197d LB	114	return ret;
abc0197d LB	115	}
038ee083	116
abc0197d LB	117	static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
abc0197d LB	118	int where, int size, u32 val)
038ee083 TP	119	{
	120	unsigned long flags;
	121	int ret;
	122
abc0197d	123	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
038ee083 TP	124	return PCIBIOS_DEVICE_NOT_FOUND;
038ee083 TP	125
9dd0b194	126	spin_lock_irqsave(&orion5x_pcie_lock, flags);
abc0197d	127	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
9dd0b194	128	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
038ee083 TP	129
	130	return ret;
	131	}
	132
159ffb3a	133	static struct pci_ops pcie_ops = {
abc0197d LB	134	.read = pcie_rd_conf,
abc0197d LB	135	.write = pcie_wr_conf,
038ee083 TP	136	};
	137
	138
a9984270	139	static int __init pcie_setup(struct pci_sys_data *sys)
038ee083 TP	140	{
038ee083 TP	141	struct resource *res;
abc0197d	142	int dev;
038ee083	143
1f2223b1	144	/*
abc0197d	145	* Generic PCIe unit setup.
038ee083	146	*/
9dd0b194	147	orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
038ee083 TP	148
038ee083 TP	149	/*
abc0197d LB	150	* Check whether to apply Orion-1/Orion-NAS PCIe config
abc0197d LB	151	* read transaction workaround.
038ee083	152	*/
abc0197d LB	153	dev = orion_pcie_dev_id(PCIE_BASE);
	154	if (dev == MV88F5181_DEV_ID \|\| dev == MV88F5182_DEV_ID) {
	155	printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
	156	"read transaction workaround\n");
386a048a LB	157	orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
386a048a LB	158	ORION5X_PCIE_WA_SIZE);
abc0197d LB	159	pcie_ops.read = pcie_rd_conf_wa;
abc0197d LB	160	}
038ee083 TP	161
038ee083 TP	162	/*
abc0197d	163	* Request resources.
038ee083 TP	164	*/
	165	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	166	if (!res)
abc0197d	167	panic("pcie_setup unable to alloc resources");
038ee083 TP	168
	169	/*
	170	* IORESOURCE_IO
	171	*/
159ffb3a	172	res[0].name = "PCIe I/O Space";
038ee083	173	res[0].flags = IORESOURCE_IO;
9dd0b194 LB	174	res[0].start = ORION5X_PCIE_IO_BUS_BASE;
9dd0b194 LB	175	res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
038ee083	176	if (request_resource(&ioport_resource, &res[0]))
159ffb3a	177	panic("Request PCIe IO resource failed\n");
038ee083 TP	178	sys->resource[0] = &res[0];
	179
	180	/*
	181	* IORESOURCE_MEM
	182	*/
159ffb3a	183	res[1].name = "PCIe Memory Space";
038ee083	184	res[1].flags = IORESOURCE_MEM;
9dd0b194 LB	185	res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
9dd0b194 LB	186	res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
038ee083	187	if (request_resource(&iomem_resource, &res[1]))
159ffb3a	188	panic("Request PCIe Memory resource failed\n");
038ee083 TP	189	sys->resource[1] = &res[1];
	190
	191	sys->resource[2] = NULL;
	192	sys->io_offset = 0;
	193
	194	return 1;
	195	}
	196
	197	/*****************************************************************************
	198	* PCI controller
	199	****************************************************************************/
fdd8b079	200	#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE \| (x))
9dd0b194 LB	201	#define PCI_MODE ORION5X_PCI_REG(0xd00)
	202	#define PCI_CMD ORION5X_PCI_REG(0xc00)
	203	#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
	204	#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
	205	#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
038ee083 TP	206
	207	/*
	208	* PCI_MODE bits
	209	*/
	210	#define PCI_MODE_64BIT (1 << 2)
	211	#define PCI_MODE_PCIX ((1 << 4) \| (1 << 5))
	212
	213	/*
	214	* PCI_CMD bits
	215	*/
	216	#define PCI_CMD_HOST_REORDER (1 << 29)
	217
	218	/*
	219	* PCI_P2P_CONF bits
	220	*/
	221	#define PCI_P2P_BUS_OFFS 16
	222	#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
	223	#define PCI_P2P_DEV_OFFS 24
	224	#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
	225
	226	/*
	227	* PCI_CONF_ADDR bits
	228	*/
	229	#define PCI_CONF_REG(reg) ((reg) & 0xfc)
	230	#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
	231	#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
	232	#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
	233	#define PCI_CONF_ADDR_EN (1 << 31)
	234
	235	/*
	236	* Internal configuration space
	237	*/
	238	#define PCI_CONF_FUNC_STAT_CMD 0
	239	#define PCI_CONF_REG_STAT_CMD 4
	240	#define PCIX_STAT 0x64
	241	#define PCIX_STAT_BUS_OFFS 8
	242	#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
	243
1f2223b1 LB	244	/*
	245	* PCI Address Decode Windows registers
	246	*/
9dd0b194	247	#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
e7068ad3 LB	248	((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
	249	((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
	250	((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
	251	#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
	252	((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
	253	((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
	254	((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
9dd0b194 LB	255	#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
9dd0b194 LB	256	#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
1f2223b1 LB	257
	258	/*
	259	* PCI configuration helpers for BAR settings
	260	*/
	261	#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
	262	#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
	263	#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
	264
038ee083 TP	265	/*
	266	* PCI config cycles are done by programming the PCI_CONF_ADDR register
	267	* and then reading the PCI_CONF_DATA register. Need to make sure these
	268	* transactions are atomic.
	269	*/
9dd0b194	270	static DEFINE_SPINLOCK(orion5x_pci_lock);
038ee083	271
da01bba3 LB	272	static int orion5x_pci_cardbus_mode;
da01bba3 LB	273
92b913b0	274	static int orion5x_pci_local_bus_nr(void)
038ee083	275	{
79e90dd5	276	u32 conf = readl(PCI_P2P_CONF);
038ee083 TP	277	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
	278	}
	279
9dd0b194	280	static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
038ee083 TP	281	u32 where, u32 size, u32 *val)
	282	{
	283	unsigned long flags;
9dd0b194	284	spin_lock_irqsave(&orion5x_pci_lock, flags);
038ee083	285
79e90dd5 LB	286	writel(PCI_CONF_BUS(bus) \|
	287	PCI_CONF_DEV(dev) \| PCI_CONF_REG(where) \|
	288	PCI_CONF_FUNC(func) \| PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
038ee083	289
79e90dd5	290	*val = readl(PCI_CONF_DATA);
038ee083 TP	291
	292	if (size == 1)
	293	val = (val >> (8*(where & 0x3))) & 0xff;
	294	else if (size == 2)
	295	val = (val >> (8*(where & 0x3))) & 0xffff;
	296
9dd0b194	297	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
038ee083 TP	298
	299	return PCIBIOS_SUCCESSFUL;
	300	}
	301
9dd0b194	302	static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
038ee083 TP	303	u32 where, u32 size, u32 val)
	304	{
	305	unsigned long flags;
	306	int ret = PCIBIOS_SUCCESSFUL;
	307
9dd0b194	308	spin_lock_irqsave(&orion5x_pci_lock, flags);
038ee083	309
79e90dd5 LB	310	writel(PCI_CONF_BUS(bus) \|
	311	PCI_CONF_DEV(dev) \| PCI_CONF_REG(where) \|
	312	PCI_CONF_FUNC(func) \| PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
038ee083 TP	313
	314	if (size == 4) {
	315	__raw_writel(val, PCI_CONF_DATA);
	316	} else if (size == 2) {
	317	__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
	318	} else if (size == 1) {
	319	__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
	320	} else {
	321	ret = PCIBIOS_BAD_REGISTER_NUMBER;
	322	}
	323
9dd0b194	324	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
038ee083 TP	325
	326	return ret;
	327	}
	328
da01bba3 LB	329	static int orion5x_pci_valid_config(int bus, u32 devfn)
	330	{
	331	if (bus == orion5x_pci_local_bus_nr()) {
	332	/*
	333	* Don't go out for local device
	334	*/
	335	if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
	336	return 0;
	337
	338	/*
	339	* When the PCI signals are directly connected to a
	340	* Cardbus slot, ignore all but device IDs 0 and 1.
	341	*/
	342	if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
	343	return 0;
	344	}
	345
	346	return 1;
	347	}
	348
9dd0b194	349	static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
038ee083 TP	350	int where, int size, u32 *val)
038ee083 TP	351	{
da01bba3	352	if (!orion5x_pci_valid_config(bus->number, devfn)) {
038ee083 TP	353	*val = 0xffffffff;
	354	return PCIBIOS_DEVICE_NOT_FOUND;
	355	}
	356
9dd0b194	357	return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
038ee083 TP	358	PCI_FUNC(devfn), where, size, val);
	359	}
	360
9dd0b194	361	static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
038ee083 TP	362	int where, int size, u32 val)
038ee083 TP	363	{
da01bba3	364	if (!orion5x_pci_valid_config(bus->number, devfn))
038ee083 TP	365	return PCIBIOS_DEVICE_NOT_FOUND;
038ee083 TP	366
9dd0b194	367	return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
038ee083 TP	368	PCI_FUNC(devfn), where, size, val);
	369	}
	370
159ffb3a	371	static struct pci_ops pci_ops = {
9dd0b194 LB	372	.read = orion5x_pci_rd_conf,
9dd0b194 LB	373	.write = orion5x_pci_wr_conf,
038ee083 TP	374	};
038ee083 TP	375
9dd0b194	376	static void __init orion5x_pci_set_bus_nr(int nr)
038ee083	377	{
79e90dd5	378	u32 p2p = readl(PCI_P2P_CONF);
038ee083	379
79e90dd5	380	if (readl(PCI_MODE) & PCI_MODE_PCIX) {
038ee083 TP	381	/*
	382	* PCI-X mode
	383	*/
	384	u32 pcix_status, bus, dev;
	385	bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
	386	dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
9dd0b194	387	orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
038ee083 TP	388	pcix_status &= ~PCIX_STAT_BUS_MASK;
038ee083 TP	389	pcix_status \|= (nr << PCIX_STAT_BUS_OFFS);
9dd0b194	390	orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
038ee083 TP	391	} else {
	392	/*
	393	* PCI Conventional mode
	394	*/
	395	p2p &= ~PCI_P2P_BUS_MASK;
	396	p2p \|= (nr << PCI_P2P_BUS_OFFS);
79e90dd5	397	writel(p2p, PCI_P2P_CONF);
038ee083 TP	398	}
	399	}
	400
9dd0b194	401	static void __init orion5x_pci_master_slave_enable(void)
038ee083	402	{
d50c60a8	403	int bus_nr, func, reg;
abc0197d	404	u32 val;
038ee083	405
9dd0b194	406	bus_nr = orion5x_pci_local_bus_nr();
038ee083 TP	407	func = PCI_CONF_FUNC_STAT_CMD;
038ee083 TP	408	reg = PCI_CONF_REG_STAT_CMD;
9dd0b194	409	orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
038ee083	410	val \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
9dd0b194	411	orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val \| 0x7);
038ee083 TP	412	}
038ee083 TP	413
9dd0b194	414	static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
1f2223b1 LB	415	{
1f2223b1 LB	416	u32 win_enable;
abc0197d	417	int bus;
1f2223b1 LB	418	int i;
	419
	420	/*
	421	* First, disable windows.
	422	*/
	423	win_enable = 0xffffffff;
79e90dd5	424	writel(win_enable, PCI_BAR_ENABLE);
1f2223b1 LB	425
	426	/*
	427	* Setup windows for DDR banks.
	428	*/
9dd0b194	429	bus = orion5x_pci_local_bus_nr();
1f2223b1 LB	430
	431	for (i = 0; i < dram->num_cs; i++) {
	432	struct mbus_dram_window *cs = dram->cs + i;
	433	u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
	434	u32 reg;
	435	u32 val;
	436
	437	/*
	438	* Write DRAM bank base address register.
	439	*/
	440	reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
9dd0b194	441	orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
1f2223b1	442	val = (cs->base & 0xfffff000) \| (val & 0xfff);
9dd0b194	443	orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
1f2223b1 LB	444
	445	/*
	446	* Write DRAM bank size register.
	447	*/
	448	reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
9dd0b194	449	orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
79e90dd5 LB	450	writel((cs->size - 1) & 0xfffff000,
	451	PCI_BAR_SIZE_DDR_CS(cs->cs_index));
	452	writel(cs->base & 0xfffff000,
	453	PCI_BAR_REMAP_DDR_CS(cs->cs_index));
1f2223b1 LB	454
	455	/*
	456	* Enable decode window for this chip select.
	457	*/
	458	win_enable &= ~(1 << cs->cs_index);
	459	}
	460
	461	/*
	462	* Re-enable decode windows.
	463	*/
79e90dd5	464	writel(win_enable, PCI_BAR_ENABLE);
1f2223b1 LB	465
1f2223b1 LB	466	/*
af901ca1	467	* Disable automatic update of address remapping when writing to BARs.
1f2223b1	468	*/
9dd0b194	469	orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
1f2223b1 LB	470	}
1f2223b1 LB	471
a9984270	472	static int __init pci_setup(struct pci_sys_data *sys)
038ee083 TP	473	{
	474	struct resource *res;
	475
1f2223b1 LB	476	/*
	477	* Point PCI unit MBUS decode windows to DRAM space.
	478	*/
9dd0b194	479	orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
1f2223b1	480
038ee083 TP	481	/*
	482	* Master + Slave enable
	483	*/
9dd0b194	484	orion5x_pci_master_slave_enable();
038ee083 TP	485
	486	/*
	487	* Force ordering
	488	*/
9dd0b194	489	orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
038ee083 TP	490
	491	/*
	492	* Request resources
	493	*/
	494	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	495	if (!res)
abc0197d	496	panic("pci_setup unable to alloc resources");
038ee083 TP	497
	498	/*
	499	* IORESOURCE_IO
	500	*/
	501	res[0].name = "PCI I/O Space";
	502	res[0].flags = IORESOURCE_IO;
9dd0b194 LB	503	res[0].start = ORION5X_PCI_IO_BUS_BASE;
9dd0b194 LB	504	res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
038ee083 TP	505	if (request_resource(&ioport_resource, &res[0]))
	506	panic("Request PCI IO resource failed\n");
	507	sys->resource[0] = &res[0];
	508
	509	/*
	510	* IORESOURCE_MEM
	511	*/
	512	res[1].name = "PCI Memory Space";
	513	res[1].flags = IORESOURCE_MEM;
9dd0b194 LB	514	res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
9dd0b194 LB	515	res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
038ee083 TP	516	if (request_resource(&iomem_resource, &res[1]))
	517	panic("Request PCI Memory resource failed\n");
	518	sys->resource[1] = &res[1];
	519
	520	sys->resource[2] = NULL;
	521	sys->io_offset = 0;
	522
	523	return 1;
	524	}
	525
	526
	527	/*****************************************************************************
159ffb3a	528	* General PCIe + PCI
038ee083	529	****************************************************************************/
d50c60a8 LB	530	static void __devinit rc_pci_fixup(struct pci_dev *dev)
	531	{
	532	/*
	533	* Prevent enumeration of root complex.
	534	*/
	535	if (dev->bus->parent == NULL && dev->devfn == 0) {
	536	int i;
	537
	538	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
	539	dev->resource[i].start = 0;
	540	dev->resource[i].end = 0;
	541	dev->resource[i].flags = 0;
	542	}
	543	}
	544	}
	545	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
	546
7a6bb262 PA	547	static int orion5x_pci_disabled __initdata;
	548
	549	void __init orion5x_pci_disable(void)
	550	{
	551	orion5x_pci_disabled = 1;
	552	}
	553
da01bba3 LB	554	void __init orion5x_pci_set_cardbus_mode(void)
	555	{
	556	orion5x_pci_cardbus_mode = 1;
	557	}
	558
9dd0b194	559	int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
038ee083 TP	560	{
	561	int ret = 0;
	562
	563	if (nr == 0) {
abc0197d LB	564	orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
abc0197d LB	565	ret = pcie_setup(sys);
7a6bb262	566	} else if (nr == 1 && !orion5x_pci_disabled) {
9dd0b194	567	orion5x_pci_set_bus_nr(sys->busnr);
abc0197d	568	ret = pci_setup(sys);
038ee083 TP	569	}
	570
	571	return ret;
	572	}
	573
9dd0b194	574	struct pci_bus __init orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data sys)
038ee083	575	{
038ee083 TP	576	struct pci_bus *bus;
038ee083 TP	577
038ee083	578	if (nr == 0) {
abc0197d	579	bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
7a6bb262	580	} else if (nr == 1 && !orion5x_pci_disabled) {
abc0197d	581	bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
038ee083	582	} else {
038ee083	583	bus = NULL;
abc0197d	584	BUG();
038ee083 TP	585	}
	586
	587	return bus;
	588	}
92b913b0 LB	589
	590	int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	591	{
	592	int bus = dev->bus->number;
	593
	594	/*
	595	* PCIe endpoint?
	596	*/
7a6bb262	597	if (orion5x_pci_disabled \|\| bus < orion5x_pci_local_bus_nr())
92b913b0 LB	598	return IRQ_ORION5X_PCIE0_INT;
	599
	600	return -1;
	601	}