[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / pm44xx.c

/*
 * OMAP4 Power Management Routines
 *
 * Copyright (C) 2010-2011 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 * Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <asm/system_misc.h>

#include "common.h"
#include "clockdomain.h"
#include "powerdomain.h"
#include "pm.h"

struct power_state {
	struct powerdomain *pwrdm;
	u32 next_state;
#ifdef CONFIG_SUSPEND
	u32 saved_state;
	u32 saved_logic_state;
#endif
	struct list_head node;
};

static LIST_HEAD(pwrst_list);

#ifdef CONFIG_SUSPEND
static int omap4_pm_suspend(void)
{
	struct power_state *pwrst;
	int state, ret = 0;
	u32 cpu_id = smp_processor_id();

	/* Save current powerdomain state */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
		pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
	}

	/* Set targeted power domain states by suspend */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
		pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
	}

	/*
	 * For MPUSS to hit power domain retention(CSWR or OSWR),
	 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
	 * since CPU power domain CSWR is not supported by hardware
	 * Only master CPU follows suspend path. All other CPUs follow
	 * CPU hotplug path in system wide suspend. On OMAP4, CPU power
	 * domain CSWR is not supported by hardware.
	 * More details can be found in OMAP4430 TRM section 4.3.4.2.
	 */
	omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);

	/* Restore next powerdomain state */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
		if (state > pwrst->next_state) {
			pr_info("Powerdomain (%s) didn't enter "
			       "target state %d\n",
			       pwrst->pwrdm->name, pwrst->next_state);
			ret = -1;
		}
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
		pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
	}
	if (ret)
		pr_crit("Could not enter target state in pm_suspend\n");
	else
		pr_info("Successfully put all powerdomains to target state\n");

	return 0;
}

static int omap4_pm_enter(suspend_state_t suspend_state)
{
	int ret = 0;

	switch (suspend_state) {
	case PM_SUSPEND_STANDBY:
	case PM_SUSPEND_MEM:
		ret = omap4_pm_suspend();
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static int omap4_pm_begin(suspend_state_t state)
{
	disable_hlt();
	return 0;
}

static void omap4_pm_end(void)
{
	enable_hlt();
	return;
}

static const struct platform_suspend_ops omap_pm_ops = {
	.begin		= omap4_pm_begin,
	.end		= omap4_pm_end,
	.enter		= omap4_pm_enter,
	.valid		= suspend_valid_only_mem,
};
#endif /* CONFIG_SUSPEND */

/*
 * Enable hardware supervised mode for all clockdomains if it's
 * supported. Initiate sleep transition for other clockdomains, if
 * they are not used
 */
static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
{
	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
		clkdm_allow_idle(clkdm);
	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
			atomic_read(&clkdm->usecount) == 0)
		clkdm_sleep(clkdm);
	return 0;
}


static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
{
	struct power_state *pwrst;

	if (!pwrdm->pwrsts)
		return 0;

	/*
	 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
	 * through hotplug path and CPU0 explicitly programmed
	 * further down in the code path
	 */
	if (!strncmp(pwrdm->name, "cpu", 3))
		return 0;

	/*
	 * FIXME: Remove this check when core retention is supported
	 * Only MPUSS power domain is added in the list.
	 */
	if (strcmp(pwrdm->name, "mpu_pwrdm"))
		return 0;

	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	if (!pwrst)
		return -ENOMEM;

	pwrst->pwrdm = pwrdm;
	pwrst->next_state = PWRDM_POWER_RET;
	list_add(&pwrst->node, &pwrst_list);

	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
}

/**
 * omap_default_idle - OMAP4 default ilde routine.'
 *
 * Implements OMAP4 memory, IO ordering requirements which can't be addressed
 * with default arch_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
 * by secondary CPU with CONFIG_CPUIDLE.
 */
static void omap_default_idle(void)
{
	local_irq_disable();
	local_fiq_disable();

	omap_do_wfi();

	local_fiq_enable();
	local_irq_enable();
}

/**
 * omap4_pm_init - Init routine for OMAP4 PM
 *
 * Initializes all powerdomain and clockdomain target states
 * and all PRCM settings.
 */
static int __init omap4_pm_init(void)
{
	int ret;
	struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
	struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;

	if (!cpu_is_omap44xx())
		return -ENODEV;

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
		return -ENODEV;
	}

	pr_err("Power Management for TI OMAP4.\n");

	ret = pwrdm_for_each(pwrdms_setup, NULL);
	if (ret) {
		pr_err("Failed to setup powerdomains\n");
		goto err2;
	}

	/*
	 * The dynamic dependency between MPUSS -> MEMIF and
	 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
	 * expected. The hardware recommendation is to enable static
	 * dependencies for these to avoid system lock ups or random crashes.
	 */
	mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
	emif_clkdm = clkdm_lookup("l3_emif_clkdm");
	l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
	l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
	l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
	ducati_clkdm = clkdm_lookup("ducati_clkdm");
	if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
		(!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
		goto err2;

	ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
	ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
	ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
	ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
	if (ret) {
		pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
				"wakeup dependency\n");
		goto err2;
	}

	ret = omap4_mpuss_init();
	if (ret) {
		pr_err("Failed to initialise OMAP4 MPUSS\n");
		goto err2;
	}

	(void) clkdm_for_each(clkdms_setup, NULL);

#ifdef CONFIG_SUSPEND
	suspend_set_ops(&omap_pm_ops);
#endif /* CONFIG_SUSPEND */

	/* Overwrite the default arch_idle() */
	pm_idle = omap_default_idle;

	omap4_idle_init();

err2:
	return ret;
}
late_initcall(omap4_pm_init);
Commit	Line	Data
5643aebb RN	1	/*
	2	* OMAP4 Power Management Routines
	3	*
e44f9a77	4	* Copyright (C) 2010-2011 Texas Instruments, Inc.
5643aebb	5	* Rajendra Nayak <rnayak@ti.com>
e44f9a77	6	* Santosh Shilimkar <santosh.shilimkar@ti.com>
5643aebb RN	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/pm.h>
	14	#include <linux/suspend.h>
	15	#include <linux/module.h>
	16	#include <linux/list.h>
	17	#include <linux/err.h>
	18	#include <linux/slab.h>
9f97da78	19	#include <asm/system_misc.h>
5643aebb	20
4e65331c	21	#include "common.h"
3c50729b	22	#include "clockdomain.h"
72e06d08	23	#include "powerdomain.h"
e44f9a77	24	#include "pm.h"
5643aebb RN	25
	26	struct power_state {
	27	struct powerdomain *pwrdm;
	28	u32 next_state;
	29	#ifdef CONFIG_SUSPEND
	30	u32 saved_state;
3ba2a739	31	u32 saved_logic_state;
5643aebb RN	32	#endif
	33	struct list_head node;
	34	};
	35
	36	static LIST_HEAD(pwrst_list);
	37
	38	#ifdef CONFIG_SUSPEND
5643aebb RN	39	static int omap4_pm_suspend(void)
5643aebb RN	40	{
e44f9a77 SS	41	struct power_state *pwrst;
	42	int state, ret = 0;
	43	u32 cpu_id = smp_processor_id();
	44
	45	/* Save current powerdomain state */
	46	list_for_each_entry(pwrst, &pwrst_list, node) {
	47	pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
3ba2a739	48	pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
e44f9a77 SS	49	}
	50
	51	/* Set targeted power domain states by suspend */
	52	list_for_each_entry(pwrst, &pwrst_list, node) {
	53	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
3ba2a739	54	pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
e44f9a77 SS	55	}
	56
	57	/*
	58	* For MPUSS to hit power domain retention(CSWR or OSWR),
	59	* CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
	60	* since CPU power domain CSWR is not supported by hardware
	61	* Only master CPU follows suspend path. All other CPUs follow
	62	* CPU hotplug path in system wide suspend. On OMAP4, CPU power
	63	* domain CSWR is not supported by hardware.
	64	* More details can be found in OMAP4430 TRM section 4.3.4.2.
	65	*/
	66	omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
	67
	68	/* Restore next powerdomain state */
	69	list_for_each_entry(pwrst, &pwrst_list, node) {
	70	state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
	71	if (state > pwrst->next_state) {
	72	pr_info("Powerdomain (%s) didn't enter "
	73	"target state %d\n",
	74	pwrst->pwrdm->name, pwrst->next_state);
	75	ret = -1;
	76	}
	77	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
3ba2a739	78	pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
e44f9a77 SS	79	}
	80	if (ret)
	81	pr_crit("Could not enter target state in pm_suspend\n");
	82	else
	83	pr_info("Successfully put all powerdomains to target state\n");
	84
5643aebb RN	85	return 0;
	86	}
	87
	88	static int omap4_pm_enter(suspend_state_t suspend_state)
	89	{
	90	int ret = 0;
	91
	92	switch (suspend_state) {
	93	case PM_SUSPEND_STANDBY:
	94	case PM_SUSPEND_MEM:
	95	ret = omap4_pm_suspend();
	96	break;
	97	default:
	98	ret = -EINVAL;
	99	}
	100
	101	return ret;
	102	}
	103
5643aebb RN	104	static int omap4_pm_begin(suspend_state_t state)
5643aebb RN	105	{
c166381d	106	disable_hlt();
5643aebb RN	107	return 0;
	108	}
	109
	110	static void omap4_pm_end(void)
	111	{
c166381d	112	enable_hlt();
5643aebb RN	113	return;
	114	}
	115
2f55ac07	116	static const struct platform_suspend_ops omap_pm_ops = {
5643aebb RN	117	.begin = omap4_pm_begin,
5643aebb RN	118	.end = omap4_pm_end,
5643aebb	119	.enter = omap4_pm_enter,
5643aebb RN	120	.valid = suspend_valid_only_mem,
	121	};
	122	#endif /* CONFIG_SUSPEND */
	123
3c50729b SS	124	/*
	125	* Enable hardware supervised mode for all clockdomains if it's
	126	* supported. Initiate sleep transition for other clockdomains, if
	127	* they are not used
	128	*/
	129	static int __init clkdms_setup(struct clockdomain clkdm, void unused)
	130	{
	131	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
	132	clkdm_allow_idle(clkdm);
	133	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
	134	atomic_read(&clkdm->usecount) == 0)
	135	clkdm_sleep(clkdm);
	136	return 0;
	137	}
	138
	139
5643aebb RN	140	static int __init pwrdms_setup(struct powerdomain pwrdm, void unused)
	141	{
	142	struct power_state *pwrst;
	143
	144	if (!pwrdm->pwrsts)
	145	return 0;
	146
e44f9a77 SS	147	/*
	148	* Skip CPU0 and CPU1 power domains. CPU1 is programmed
	149	* through hotplug path and CPU0 explicitly programmed
	150	* further down in the code path
	151	*/
	152	if (!strncmp(pwrdm->name, "cpu", 3))
	153	return 0;
	154
	155	/*
	156	* FIXME: Remove this check when core retention is supported
	157	* Only MPUSS power domain is added in the list.
	158	*/
	159	if (strcmp(pwrdm->name, "mpu_pwrdm"))
	160	return 0;
	161
5643aebb RN	162	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	163	if (!pwrst)
	164	return -ENOMEM;
e44f9a77	165
5643aebb	166	pwrst->pwrdm = pwrdm;
e44f9a77	167	pwrst->next_state = PWRDM_POWER_RET;
5643aebb RN	168	list_add(&pwrst->node, &pwrst_list);
5643aebb RN	169
e44f9a77	170	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
5643aebb RN	171	}
5643aebb RN	172
72826b9f SS	173	/**
	174	* omap_default_idle - OMAP4 default ilde routine.'
	175	*
	176	* Implements OMAP4 memory, IO ordering requirements which can't be addressed
	177	* with default arch_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
	178	* by secondary CPU with CONFIG_CPUIDLE.
	179	*/
	180	static void omap_default_idle(void)
	181	{
	182	local_irq_disable();
	183	local_fiq_disable();
	184
	185	omap_do_wfi();
	186
	187	local_fiq_enable();
	188	local_irq_enable();
	189	}
	190
5643aebb RN	191	/**
	192	* omap4_pm_init - Init routine for OMAP4 PM
	193	*
	194	* Initializes all powerdomain and clockdomain target states
	195	* and all PRCM settings.
	196	*/
	197	static int __init omap4_pm_init(void)
	198	{
	199	int ret;
12f27826 SS	200	struct clockdomain emif_clkdm, mpuss_clkdm, *l3_1_clkdm;
12f27826 SS	201	struct clockdomain ducati_clkdm, l3_2_clkdm, *l4_per_clkdm;
5643aebb RN	202
	203	if (!cpu_is_omap44xx())
	204	return -ENODEV;
	205
361b02f3 SS	206	if (omap_rev() == OMAP4430_REV_ES1_0) {
	207	WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
	208	return -ENODEV;
	209	}
	210
5643aebb RN	211	pr_err("Power Management for TI OMAP4.\n");
5643aebb RN	212
5643aebb RN	213	ret = pwrdm_for_each(pwrdms_setup, NULL);
	214	if (ret) {
	215	pr_err("Failed to setup powerdomains\n");
	216	goto err2;
	217	}
5643aebb	218
12f27826 SS	219	/*
	220	* The dynamic dependency between MPUSS -> MEMIF and
	221	* MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
	222	* expected. The hardware recommendation is to enable static
	223	* dependencies for these to avoid system lock ups or random crashes.
	224	*/
	225	mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
	226	emif_clkdm = clkdm_lookup("l3_emif_clkdm");
	227	l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
	228	l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
	229	l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
	230	ducati_clkdm = clkdm_lookup("ducati_clkdm");
	231	if ((!mpuss_clkdm) \|\| (!emif_clkdm) \|\| (!l3_1_clkdm) \|\|
	232	(!l3_2_clkdm) \|\| (!ducati_clkdm) \|\| (!l4_per_clkdm))
	233	goto err2;
	234
	235	ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
	236	ret \|= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
	237	ret \|= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
	238	ret \|= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
	239	ret \|= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
	240	ret \|= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
	241	if (ret) {
	242	pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
	243	"wakeup dependency\n");
	244	goto err2;
	245	}
	246
b2b9762f SS	247	ret = omap4_mpuss_init();
	248	if (ret) {
	249	pr_err("Failed to initialise OMAP4 MPUSS\n");
	250	goto err2;
	251	}
	252
3c50729b SS	253	(void) clkdm_for_each(clkdms_setup, NULL);
3c50729b SS	254
5643aebb RN	255	#ifdef CONFIG_SUSPEND
	256	suspend_set_ops(&omap_pm_ops);
	257	#endif /* CONFIG_SUSPEND */
	258
72826b9f SS	259	/* Overwrite the default arch_idle() */
	260	pm_idle = omap_default_idle;
	261
98272660 SS	262	omap4_idle_init();
98272660 SS	263
5643aebb RN	264	err2:
	265	return ret;
	266	}
	267	late_initcall(omap4_pm_init);