[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / mcbsp.c

/*
 * linux/arch/arm/mach-omap2/mcbsp.c
 *
 * Copyright (C) 2008 Instituto Nokia de Tecnologia
 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Multichannel mode not supported.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <mach/irqs.h>
#include <plat/dma.h>
#include <plat/mux.h>
#include <plat/cpu.h>
#include <plat/mcbsp.h>

static void omap2_mcbsp2_mux_setup(void)
{
	omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
	omap_cfg_reg(R14_24XX_MCBSP2_FSX);
	omap_cfg_reg(W15_24XX_MCBSP2_DR);
	omap_cfg_reg(V15_24XX_MCBSP2_DX);
	omap_cfg_reg(V14_24XX_GPIO117);
	/*
	 * TODO: Need to add MUX settings for OMAP 2430 SDP
	 */
}

static void omap2_mcbsp_request(unsigned int id)
{
	if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
		omap2_mcbsp2_mux_setup();
}

static struct omap_mcbsp_ops omap2_mcbsp_ops = {
	.request	= omap2_mcbsp_request,
};

#ifdef CONFIG_ARCH_OMAP2420
static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
	{
		.phys_base	= OMAP24XX_MCBSP1_BASE,
		.dma_rx_sync	= OMAP24XX_DMA_MCBSP1_RX,
		.dma_tx_sync	= OMAP24XX_DMA_MCBSP1_TX,
		.rx_irq		= INT_24XX_MCBSP1_IRQ_RX,
		.tx_irq		= INT_24XX_MCBSP1_IRQ_TX,
		.ops		= &omap2_mcbsp_ops,
	},
	{
		.phys_base	= OMAP24XX_MCBSP2_BASE,
		.dma_rx_sync	= OMAP24XX_DMA_MCBSP2_RX,
		.dma_tx_sync	= OMAP24XX_DMA_MCBSP2_TX,
		.rx_irq		= INT_24XX_MCBSP2_IRQ_RX,
		.tx_irq		= INT_24XX_MCBSP2_IRQ_TX,
		.ops		= &omap2_mcbsp_ops,
	},
};
#define OMAP2420_MCBSP_PDATA_SZ		ARRAY_SIZE(omap2420_mcbsp_pdata)
#define OMAP2420_MCBSP_REG_NUM		(OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
#else
#define omap2420_mcbsp_pdata		NULL
#define OMAP2420_MCBSP_PDATA_SZ		0
#define OMAP2420_MCBSP_REG_NUM		0
#endif

#ifdef CONFIG_ARCH_OMAP2430
static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
	{
		.phys_base	= OMAP24XX_MCBSP1_BASE,
		.dma_rx_sync	= OMAP24XX_DMA_MCBSP1_RX,
		.dma_tx_sync	= OMAP24XX_DMA_MCBSP1_TX,
		.rx_irq		= INT_24XX_MCBSP1_IRQ_RX,
		.tx_irq		= INT_24XX_MCBSP1_IRQ_TX,
		.ops		= &omap2_mcbsp_ops,
	},
	{
		.phys_base	= OMAP24XX_MCBSP2_BASE,
		.dma_rx_sync	= OMAP24XX_DMA_MCBSP2_RX,
		.dma_tx_sync	= OMAP24XX_DMA_MCBSP2_TX,
		.rx_irq		= INT_24XX_MCBSP2_IRQ_RX,
		.tx_irq		= INT_24XX_MCBSP2_IRQ_TX,
		.ops		= &omap2_mcbsp_ops,
	},
	{
		.phys_base	= OMAP2430_MCBSP3_BASE,
		.dma_rx_sync	= OMAP24XX_DMA_MCBSP3_RX,
		.dma_tx_sync	= OMAP24XX_DMA_MCBSP3_TX,
		.rx_irq		= INT_24XX_MCBSP3_IRQ_RX,
		.tx_irq		= INT_24XX_MCBSP3_IRQ_TX,
		.ops		= &omap2_mcbsp_ops,
	},
	{
		.phys_base	= OMAP2430_MCBSP4_BASE,
		.dma_rx_sync	= OMAP24XX_DMA_MCBSP4_RX,
		.dma_tx_sync	= OMAP24XX_DMA_MCBSP4_TX,
		.rx_irq		= INT_24XX_MCBSP4_IRQ_RX,
		.tx_irq		= INT_24XX_MCBSP4_IRQ_TX,
		.ops		= &omap2_mcbsp_ops,
	},
	{
		.phys_base	= OMAP2430_MCBSP5_BASE,
		.dma_rx_sync	= OMAP24XX_DMA_MCBSP5_RX,
		.dma_tx_sync	= OMAP24XX_DMA_MCBSP5_TX,
		.rx_irq		= INT_24XX_MCBSP5_IRQ_RX,
		.tx_irq		= INT_24XX_MCBSP5_IRQ_TX,
		.ops		= &omap2_mcbsp_ops,
	},
};
#define OMAP2430_MCBSP_PDATA_SZ		ARRAY_SIZE(omap2430_mcbsp_pdata)
#define OMAP2430_MCBSP_REG_NUM		(OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
#else
#define omap2430_mcbsp_pdata		NULL
#define OMAP2430_MCBSP_PDATA_SZ		0
#define OMAP2430_MCBSP_REG_NUM		0
#endif

#ifdef CONFIG_ARCH_OMAP3
static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
	{
		.phys_base	= OMAP34XX_MCBSP1_BASE,
		.dma_rx_sync	= OMAP24XX_DMA_MCBSP1_RX,
		.dma_tx_sync	= OMAP24XX_DMA_MCBSP1_TX,
		.rx_irq		= INT_24XX_MCBSP1_IRQ_RX,
		.tx_irq		= INT_24XX_MCBSP1_IRQ_TX,
		.ops		= &omap2_mcbsp_ops,
		.buffer_size	= 0x6F,
	},
	{
		.phys_base	= OMAP34XX_MCBSP2_BASE,
		.phys_base_st	= OMAP34XX_MCBSP2_ST_BASE,
		.dma_rx_sync	= OMAP24XX_DMA_MCBSP2_RX,
		.dma_tx_sync	= OMAP24XX_DMA_MCBSP2_TX,
		.rx_irq		= INT_24XX_MCBSP2_IRQ_RX,
		.tx_irq		= INT_24XX_MCBSP2_IRQ_TX,
		.ops		= &omap2_mcbsp_ops,
		.buffer_size	= 0x3FF,
	},
	{
		.phys_base	= OMAP34XX_MCBSP3_BASE,
		.phys_base_st	= OMAP34XX_MCBSP3_ST_BASE,
		.dma_rx_sync	= OMAP24XX_DMA_MCBSP3_RX,
		.dma_tx_sync	= OMAP24XX_DMA_MCBSP3_TX,
		.rx_irq		= INT_24XX_MCBSP3_IRQ_RX,
		.tx_irq		= INT_24XX_MCBSP3_IRQ_TX,
		.ops		= &omap2_mcbsp_ops,
		.buffer_size	= 0x6F,
	},
	{
		.phys_base	= OMAP34XX_MCBSP4_BASE,
		.dma_rx_sync	= OMAP24XX_DMA_MCBSP4_RX,
		.dma_tx_sync	= OMAP24XX_DMA_MCBSP4_TX,
		.rx_irq		= INT_24XX_MCBSP4_IRQ_RX,
		.tx_irq		= INT_24XX_MCBSP4_IRQ_TX,
		.ops		= &omap2_mcbsp_ops,
		.buffer_size	= 0x6F,
	},
	{
		.phys_base	= OMAP34XX_MCBSP5_BASE,
		.dma_rx_sync	= OMAP24XX_DMA_MCBSP5_RX,
		.dma_tx_sync	= OMAP24XX_DMA_MCBSP5_TX,
		.rx_irq		= INT_24XX_MCBSP5_IRQ_RX,
		.tx_irq		= INT_24XX_MCBSP5_IRQ_TX,
		.ops		= &omap2_mcbsp_ops,
		.buffer_size	= 0x6F,
	},
};
#define OMAP34XX_MCBSP_PDATA_SZ		ARRAY_SIZE(omap34xx_mcbsp_pdata)
#define OMAP34XX_MCBSP_REG_NUM		(OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
#else
#define omap34xx_mcbsp_pdata		NULL
#define OMAP34XX_MCBSP_PDATA_SZ		0
#define OMAP34XX_MCBSP_REG_NUM		0
#endif

static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
	{
		.phys_base      = OMAP44XX_MCBSP1_BASE,
		.dma_rx_sync    = OMAP44XX_DMA_MCBSP1_RX,
		.dma_tx_sync    = OMAP44XX_DMA_MCBSP1_TX,
		.rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
		.tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
		.ops            = &omap2_mcbsp_ops,
	},
	{
		.phys_base      = OMAP44XX_MCBSP2_BASE,
		.dma_rx_sync    = OMAP44XX_DMA_MCBSP2_RX,
		.dma_tx_sync    = OMAP44XX_DMA_MCBSP2_TX,
		.rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
		.tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
		.ops            = &omap2_mcbsp_ops,
	},
	{
		.phys_base      = OMAP44XX_MCBSP3_BASE,
		.dma_rx_sync    = OMAP44XX_DMA_MCBSP3_RX,
		.dma_tx_sync    = OMAP44XX_DMA_MCBSP3_TX,
		.rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
		.tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
		.ops            = &omap2_mcbsp_ops,
	},
	{
		.phys_base      = OMAP44XX_MCBSP4_BASE,
		.dma_rx_sync    = OMAP44XX_DMA_MCBSP4_RX,
		.dma_tx_sync    = OMAP44XX_DMA_MCBSP4_TX,
		.rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
		.tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
		.ops            = &omap2_mcbsp_ops,
	},
};
#define OMAP44XX_MCBSP_PDATA_SZ		ARRAY_SIZE(omap44xx_mcbsp_pdata)
#define OMAP44XX_MCBSP_REG_NUM		(OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)

static int __init omap2_mcbsp_init(void)
{
	if (cpu_is_omap2420()) {
		omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
		omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
	} else if (cpu_is_omap2430()) {
		omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
		omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
	} else if (cpu_is_omap34xx()) {
		omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
		omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
	} else if (cpu_is_omap44xx()) {
		omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
		omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
	}

	mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
								GFP_KERNEL);
	if (!mcbsp_ptr)
		return -ENOMEM;

	if (cpu_is_omap2420())
		omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
						OMAP2420_MCBSP_PDATA_SZ);
	if (cpu_is_omap2430())
		omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
						OMAP2430_MCBSP_PDATA_SZ);
	if (cpu_is_omap34xx())
		omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
						OMAP34XX_MCBSP_PDATA_SZ);
	if (cpu_is_omap44xx())
		omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
						OMAP44XX_MCBSP_PDATA_SZ);

	return omap_mcbsp_init();
}
arch_initcall(omap2_mcbsp_init);
Commit	Line	Data
78673bc8 EV	1	/*
	2	* linux/arch/arm/mach-omap2/mcbsp.c
	3	*
	4	* Copyright (C) 2008 Instituto Nokia de Tecnologia
	5	* Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* Multichannel mode not supported.
	12	*/
	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18	#include <linux/platform_device.h>
5a0e3ad6	19	#include <linux/slab.h>
78673bc8	20
dd7667aa	21	#include <mach/irqs.h>
ce491cf8 TL	22	#include <plat/dma.h>
	23	#include <plat/mux.h>
	24	#include <plat/cpu.h>
	25	#include <plat/mcbsp.h>
78673bc8	26
78673bc8 EV	27	static void omap2_mcbsp2_mux_setup(void)
	28	{
	29	omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
	30	omap_cfg_reg(R14_24XX_MCBSP2_FSX);
	31	omap_cfg_reg(W15_24XX_MCBSP2_DR);
	32	omap_cfg_reg(V15_24XX_MCBSP2_DX);
	33	omap_cfg_reg(V14_24XX_GPIO117);
	34	/*
	35	* TODO: Need to add MUX settings for OMAP 2430 SDP
	36	*/
	37	}
	38
	39	static void omap2_mcbsp_request(unsigned int id)
	40	{
	41	if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
	42	omap2_mcbsp2_mux_setup();
	43	}
	44
78673bc8 EV	45	static struct omap_mcbsp_ops omap2_mcbsp_ops = {
78673bc8 EV	46	.request = omap2_mcbsp_request,
78673bc8 EV	47	};
78673bc8 EV	48
05228c35 JN	49	#ifdef CONFIG_ARCH_OMAP2420
05228c35 JN	50	static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
78673bc8	51	{
65846909	52	.phys_base = OMAP24XX_MCBSP1_BASE,
78673bc8 EV	53	.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
	54	.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
	55	.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
	56	.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
	57	.ops = &omap2_mcbsp_ops,
78673bc8 EV	58	},
78673bc8 EV	59	{
65846909	60	.phys_base = OMAP24XX_MCBSP2_BASE,
78673bc8 EV	61	.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
	62	.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
	63	.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
	64	.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
	65	.ops = &omap2_mcbsp_ops,
78673bc8 EV	66	},
78673bc8 EV	67	};
05228c35	68	#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
c8c99699	69	#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
78673bc8	70	#else
05228c35 JN	71	#define omap2420_mcbsp_pdata NULL
05228c35 JN	72	#define OMAP2420_MCBSP_PDATA_SZ 0
c8c99699	73	#define OMAP2420_MCBSP_REG_NUM 0
05228c35 JN	74	#endif
	75
	76	#ifdef CONFIG_ARCH_OMAP2430
	77	static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
	78	{
	79	.phys_base = OMAP24XX_MCBSP1_BASE,
	80	.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
	81	.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
	82	.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
	83	.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
	84	.ops = &omap2_mcbsp_ops,
05228c35 JN	85	},
	86	{
	87	.phys_base = OMAP24XX_MCBSP2_BASE,
	88	.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
	89	.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
	90	.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
	91	.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
	92	.ops = &omap2_mcbsp_ops,
05228c35 JN	93	},
	94	{
	95	.phys_base = OMAP2430_MCBSP3_BASE,
	96	.dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
	97	.dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
	98	.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
	99	.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
	100	.ops = &omap2_mcbsp_ops,
05228c35 JN	101	},
	102	{
	103	.phys_base = OMAP2430_MCBSP4_BASE,
	104	.dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
	105	.dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
	106	.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
	107	.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
	108	.ops = &omap2_mcbsp_ops,
05228c35 JN	109	},
	110	{
	111	.phys_base = OMAP2430_MCBSP5_BASE,
	112	.dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
	113	.dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
	114	.rx_irq = INT_24XX_MCBSP5_IRQ_RX,
	115	.tx_irq = INT_24XX_MCBSP5_IRQ_TX,
	116	.ops = &omap2_mcbsp_ops,
05228c35 JN	117	},
	118	};
	119	#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
c8c99699	120	#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
05228c35 JN	121	#else
	122	#define omap2430_mcbsp_pdata NULL
	123	#define OMAP2430_MCBSP_PDATA_SZ 0
c8c99699	124	#define OMAP2430_MCBSP_REG_NUM 0
78673bc8 EV	125	#endif
78673bc8 EV	126
a8eb7ca0	127	#ifdef CONFIG_ARCH_OMAP3
78673bc8 EV	128	static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
78673bc8 EV	129	{
65846909	130	.phys_base = OMAP34XX_MCBSP1_BASE,
78673bc8 EV	131	.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
	132	.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
	133	.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
	134	.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
	135	.ops = &omap2_mcbsp_ops,
7e4f943b	136	.buffer_size = 0x6F,
78673bc8 EV	137	},
78673bc8 EV	138	{
65846909	139	.phys_base = OMAP34XX_MCBSP2_BASE,
d912fa92	140	.phys_base_st = OMAP34XX_MCBSP2_ST_BASE,
78673bc8 EV	141	.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
	142	.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
	143	.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
	144	.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
	145	.ops = &omap2_mcbsp_ops,
a1a56f5f	146	.buffer_size = 0x3FF,
78673bc8	147	},
9c8e3a0f CS	148	{
9c8e3a0f CS	149	.phys_base = OMAP34XX_MCBSP3_BASE,
d912fa92	150	.phys_base_st = OMAP34XX_MCBSP3_ST_BASE,
9c8e3a0f CS	151	.dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
	152	.dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
	153	.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
	154	.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
	155	.ops = &omap2_mcbsp_ops,
7e4f943b	156	.buffer_size = 0x6F,
9c8e3a0f CS	157	},
	158	{
	159	.phys_base = OMAP34XX_MCBSP4_BASE,
	160	.dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
	161	.dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
	162	.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
	163	.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
	164	.ops = &omap2_mcbsp_ops,
7e4f943b	165	.buffer_size = 0x6F,
9c8e3a0f CS	166	},
	167	{
	168	.phys_base = OMAP34XX_MCBSP5_BASE,
	169	.dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
	170	.dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
	171	.rx_irq = INT_24XX_MCBSP5_IRQ_RX,
	172	.tx_irq = INT_24XX_MCBSP5_IRQ_TX,
	173	.ops = &omap2_mcbsp_ops,
7e4f943b	174	.buffer_size = 0x6F,
9c8e3a0f	175	},
78673bc8 EV	176	};
78673bc8 EV	177	#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
c8c99699	178	#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
78673bc8 EV	179	#else
	180	#define omap34xx_mcbsp_pdata NULL
	181	#define OMAP34XX_MCBSP_PDATA_SZ 0
c8c99699	182	#define OMAP34XX_MCBSP_REG_NUM 0
78673bc8 EV	183	#endif
78673bc8 EV	184
a5b92cc3 SR	185	static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
	186	{
	187	.phys_base = OMAP44XX_MCBSP1_BASE,
	188	.dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX,
	189	.dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX,
	190	.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
	191	.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
	192	.ops = &omap2_mcbsp_ops,
	193	},
	194	{
	195	.phys_base = OMAP44XX_MCBSP2_BASE,
	196	.dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX,
	197	.dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX,
	198	.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
	199	.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
	200	.ops = &omap2_mcbsp_ops,
	201	},
	202	{
	203	.phys_base = OMAP44XX_MCBSP3_BASE,
	204	.dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX,
	205	.dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX,
	206	.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
	207	.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
	208	.ops = &omap2_mcbsp_ops,
	209	},
	210	{
	211	.phys_base = OMAP44XX_MCBSP4_BASE,
	212	.dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX,
	213	.dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX,
	214	.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
	215	.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
	216	.ops = &omap2_mcbsp_ops,
	217	},
	218	};
	219	#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata)
c8c99699	220	#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
a5b92cc3	221
b4b58f58	222	static int __init omap2_mcbsp_init(void)
78673bc8	223	{
c8c99699	224	if (cpu_is_omap2420()) {
05228c35	225	omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
c8c99699 JK	226	omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
c8c99699 JK	227	} else if (cpu_is_omap2430()) {
05228c35	228	omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
c8c99699 JK	229	omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
c8c99699 JK	230	} else if (cpu_is_omap34xx()) {
b4b58f58	231	omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
c8c99699 JK	232	omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
c8c99699 JK	233	} else if (cpu_is_omap44xx()) {
a5b92cc3	234	omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
c8c99699 JK	235	omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
c8c99699 JK	236	}
b4b58f58 CS	237
	238	mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
	239	GFP_KERNEL);
	240	if (!mcbsp_ptr)
	241	return -ENOMEM;
	242
05228c35 JN	243	if (cpu_is_omap2420())
	244	omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
	245	OMAP2420_MCBSP_PDATA_SZ);
	246	if (cpu_is_omap2430())
	247	omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
	248	OMAP2430_MCBSP_PDATA_SZ);
9c8e3a0f CS	249	if (cpu_is_omap34xx())
	250	omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
	251	OMAP34XX_MCBSP_PDATA_SZ);
a5b92cc3 SR	252	if (cpu_is_omap44xx())
	253	omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
	254	OMAP44XX_MCBSP_PDATA_SZ);
78673bc8	255
78673bc8 EV	256	return omap_mcbsp_init();
	257	}
	258	arch_initcall(omap2_mcbsp_init);