[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-mt8127 / include / mach / upmu_hw_mt6397.h

#ifndef _MT6397_PMIC_UPMU_HW_H_
#define _MT6397_PMIC_UPMU_HW_H_

//register number
#define CHR_CON0        0x0000
#define CHR_CON1        0x0002
#define CHR_CON2        0x0004
#define CHR_CON3        0x0006
#define CHR_CON4        0x0008
#define CHR_CON5        0x000A
#define CHR_CON6        0x000C
#define CHR_CON7        0x000E
#define CHR_CON8        0x0010
#define CHR_CON9        0x0012
#define CHR_CON10       0x0014
#define CHR_CON11       0x0016
#define CHR_CON12       0x0018
#define CHR_CON13       0x001A
#define CHR_CON14       0x001C
#define CHR_CON15       0x001E
#define CHR_CON16       0x0020
#define CHR_CON17       0x0022
#define CHR_CON18       0x0024
#define CHR_CON19       0x0026
#define CHR_CON20       0x0028
#define CHR_CON21       0x002A
#define CHR_CON22       0x002C
#define CHR_CON23       0x002E
#define CHR_CON24       0x0030
#define CHR_CON25       0x0032
#define CHR_CON26       0x0034
#define CHR_CON27       0x0036
#define CHR_CON28       0x0038
#define CHR_CON29       0x003A
#define CID             0x0100
#define TOP_CKPDN       0x0102
#define TOP_CKPDN_SET   0x0104
#define TOP_CKPDN_CLR   0x0106
#define TOP_CKPDN2      0x0108
#define TOP_CKPDN2_SET  0x010A
#define TOP_CKPDN2_CLR  0x010C
#define TOP_GPIO_CKPDN  0x010E
#define TOP_RST_CON     0x0114
#define WRP_CKPDN       0x011A
#define WRP_RST_CON     0x0120
#define TOP_RST_MISC    0x0126
#define TOP_CKCON1      0x0128
#define TOP_CKCON2      0x012A
#define TOP_CKTST1      0x012C
#define TOP_CKTST2      0x012E
#define OC_DEG_EN       0x0130
#define OC_CTL0         0x0132
#define OC_CTL1         0x0134
#define OC_CTL2         0x0136
#define INT_RSV         0x0138
#define TEST_CON0       0x013A
#define TEST_CON1       0x013C
#define STATUS0         0x013E
#define STATUS1         0x0140
#define PGSTATUS        0x0142
#define CHRSTATUS       0x0144
#define OCSTATUS0       0x0146
#define OCSTATUS1       0x0148
#define OCSTATUS2       0x014A
#define HDMI_PAD_IE     0x014C
#define TEST_OUT_L      0x014E
#define TEST_OUT_H      0x0150
#define TDSEL_CON       0x0152
#define RDSEL_CON       0x0154
#define GPIO_SMT_CON0   0x0156
#define GPIO_SMT_CON1   0x0158
#define GPIO_SMT_CON2   0x015A
#define GPIO_SMT_CON3   0x015C
#define DRV_CON0        0x015E
#define DRV_CON1        0x0160
#define DRV_CON2        0x0162
#define DRV_CON3        0x0164
#define DRV_CON4        0x0166
#define DRV_CON5        0x0168
#define DRV_CON6        0x016A
#define DRV_CON7        0x016C
#define DRV_CON8        0x016E
#define DRV_CON9        0x0170
#define DRV_CON10       0x0172
#define DRV_CON11       0x0174
#define DRV_CON12       0x0176
#define INT_CON0        0x0178
#define INT_CON1        0x017E
#define INT_STATUS0     0x0184
#define INT_STATUS1     0x0186
#define FQMTR_CON0      0x0188
#define FQMTR_CON1      0x018A
#define FQMTR_CON2      0x018C
#define EFUSE_CON0      0x018E
#define EFUSE_CON1      0x0190
#define EFUSE_CON2      0x0192
#define EFUSE_CON3      0x0194
#define EFUSE_CON4      0x0196
#define EFUSE_CON5      0x0198
#define EFUSE_CON6      0x019A
#define EFUSE_VAL_0_15  0x019C
#define EFUSE_VAL_16_31 0x019E
#define EFUSE_VAL_32_47 0x01A0
#define EFUSE_VAL_48_63 0x01A2
#define EFUSE_VAL_64_79 0x01A4
#define EFUSE_VAL_80_95 0x01A6
#define EFUSE_VAL_96_111 0x01A8
#define EFUSE_VAL_112_127 0x01AA
#define EFUSE_VAL_128_143 0x01AC
#define EFUSE_VAL_144_159 0x01AE
#define EFUSE_VAL_160_175 0x01B0
#define EFUSE_VAL_176_191 0x01B2
#define EFUSE_VAL_192_207 0x01B4
#define EFUSE_VAL_208_223 0x01B6
#define EFUSE_VAL_224_239 0x01B8
#define EFUSE_VAL_240_255 0x01BA
#define EFUSE_VAL_256_271 0x01BC
#define EFUSE_VAL_272_287 0x01BE
#define EFUSE_VAL_288_303 0x01C0
#define EFUSE_VAL_304_319 0x01C2
#define EFUSE_DOUT_0_15 0x01C4
#define EFUSE_DOUT_16_31 0x01C6
#define EFUSE_DOUT_32_47 0x01C8
#define EFUSE_DOUT_48_63 0x01CA
#define SPI_CON         0x01CC
#define TOP_CKPDN3      0x01CE
#define TOP_CKCON3      0x01D4
#define EFUSE_DOUT_64_79 0x01D6
#define EFUSE_DOUT_80_95 0x01D8
#define EFUSE_DOUT_96_111 0x01DA
#define EFUSE_DOUT_112_127 0x01DC
#define EFUSE_DOUT_128_143 0x01DE
#define EFUSE_DOUT_144_159 0x01E0
#define EFUSE_DOUT_160_175 0x01E2
#define EFUSE_DOUT_176_191 0x01E4
#define EFUSE_DOUT_192_207 0x01E6
#define EFUSE_DOUT_208_223 0x01E8
#define EFUSE_DOUT_224_239 0x01EA
#define EFUSE_DOUT_240_255 0x01EC
#define EFUSE_DOUT_256_271 0x01EE
#define EFUSE_DOUT_272_287 0x01F0
#define EFUSE_DOUT_288_303 0x01F2
#define EFUSE_DOUT_304_319 0x01F4
#define BUCK_CON0       0x0200
#define BUCK_CON1       0x0202
#define BUCK_CON2       0x0204
#define BUCK_CON3       0x0206
#define BUCK_CON4       0x0208
#define BUCK_CON5       0x020A
#define BUCK_CON6       0x020C
#define BUCK_CON7       0x020E
#define BUCK_CON8       0x0210
#define BUCK_CON9       0x0212
#define VCA15_CON0      0x0214
#define VCA15_CON1      0x0216
#define VCA15_CON2      0x0218
#define VCA15_CON3      0x021A
#define VCA15_CON4      0x021C
#define VCA15_CON5      0x021E
#define VCA15_CON6      0x0220
#define VCA15_CON7      0x0222
#define VCA15_CON8      0x0224
#define VCA15_CON9      0x0226
#define VCA15_CON10     0x0228
#define VCA15_CON11     0x022A
#define VCA15_CON12     0x022C
#define VCA15_CON13     0x022E
#define VCA15_CON14     0x0230
#define VCA15_CON15     0x0232
#define VCA15_CON16     0x0234
#define VCA15_CON17     0x0236
#define VCA15_CON18     0x0238
#define VSRMCA15_CON0   0x023A
#define VSRMCA15_CON1   0x023C
#define VSRMCA15_CON2   0x023E
#define VSRMCA15_CON3   0x0240
#define VSRMCA15_CON4   0x0242
#define VSRMCA15_CON5   0x0244
#define VSRMCA15_CON6   0x0246
#define VSRMCA15_CON7   0x0248
#define VSRMCA15_CON8   0x024A
#define VSRMCA15_CON9   0x024C
#define VSRMCA15_CON10  0x024E
#define VSRMCA15_CON11  0x0250
#define VSRMCA15_CON12  0x0252
#define VSRMCA15_CON13  0x0254
#define VSRMCA15_CON14  0x0256
#define VSRMCA15_CON15  0x0258
#define VSRMCA15_CON16  0x025A
#define VSRMCA15_CON17  0x025C
#define VSRMCA15_CON18  0x025E
#define VSRMCA15_CON19  0x0260
#define VSRMCA15_CON20  0x0262
#define VSRMCA15_CON21  0x0264
#define VCORE_CON0      0x0266
#define VCORE_CON1      0x0268
#define VCORE_CON2      0x026A
#define VCORE_CON3      0x026C
#define VCORE_CON4      0x026E
#define VCORE_CON5      0x0270
#define VCORE_CON6      0x0272
#define VCORE_CON7      0x0274
#define VCORE_CON8      0x0276
#define VCORE_CON9      0x0278
#define VCORE_CON10     0x027A
#define VCORE_CON11     0x027C
#define VCORE_CON12     0x027E
#define VCORE_CON13     0x0280
#define VCORE_CON14     0x0282
#define VCORE_CON15     0x0284
#define VCORE_CON16     0x0286
#define VCORE_CON17     0x0288
#define VCORE_CON18     0x028A
#define VGPU_CON0       0x028C
#define VGPU_CON1       0x028E
#define VGPU_CON2       0x0290
#define VGPU_CON3       0x0292
#define VGPU_CON4       0x0294
#define VGPU_CON5       0x0296
#define VGPU_CON6       0x0298
#define VGPU_CON7       0x029A
#define VGPU_CON8       0x029C
#define VGPU_CON9       0x029E
#define VGPU_CON10      0x02A0
#define VGPU_CON11      0x02A2
#define VGPU_CON12      0x02A4
#define VGPU_CON13      0x02A6
#define VGPU_CON14      0x02A8
#define VGPU_CON15      0x02AA
#define VGPU_CON16      0x02AC
#define VGPU_CON17      0x02AE
#define VGPU_CON18      0x02B0
#define VIO18_CON0      0x0300
#define VIO18_CON1      0x0302
#define VIO18_CON2      0x0304
#define VIO18_CON3      0x0306
#define VIO18_CON4      0x0308
#define VIO18_CON5      0x030A
#define VIO18_CON6      0x030C
#define VIO18_CON7      0x030E
#define VIO18_CON8      0x0310
#define VIO18_CON9      0x0312
#define VIO18_CON10     0x0314
#define VIO18_CON11     0x0316
#define VIO18_CON12     0x0318
#define VIO18_CON13     0x031A
#define VIO18_CON14     0x031C
#define VIO18_CON15     0x031E
#define VIO18_CON16     0x0320
#define VIO18_CON17     0x0322
#define VIO18_CON18     0x0324
#define VPCA7_CON0      0x0326
#define VPCA7_CON1      0x0328
#define VPCA7_CON2      0x032A
#define VPCA7_CON3      0x032C
#define VPCA7_CON4      0x032E
#define VPCA7_CON5      0x0330
#define VPCA7_CON6      0x0332
#define VPCA7_CON7      0x0334
#define VPCA7_CON8      0x0336
#define VPCA7_CON9      0x0338
#define VPCA7_CON10     0x033A
#define VPCA7_CON11     0x033C
#define VPCA7_CON12     0x033E
#define VPCA7_CON13     0x0340
#define VPCA7_CON14     0x0342
#define VPCA7_CON15     0x0344
#define VPCA7_CON16     0x0346
#define VPCA7_CON17     0x0348
#define VPCA7_CON18     0x034A
#define VSRMCA7_CON0    0x034C
#define VSRMCA7_CON1    0x034E
#define VSRMCA7_CON2    0x0350
#define VSRMCA7_CON3    0x0352
#define VSRMCA7_CON4    0x0354
#define VSRMCA7_CON5    0x0356
#define VSRMCA7_CON6    0x0358
#define VSRMCA7_CON7    0x035A
#define VSRMCA7_CON8    0x035C
#define VSRMCA7_CON9    0x035E
#define VSRMCA7_CON10   0x0360
#define VSRMCA7_CON11   0x0362
#define VSRMCA7_CON12   0x0364
#define VSRMCA7_CON13   0x0366
#define VSRMCA7_CON14   0x0368
#define VSRMCA7_CON15   0x036A
#define VSRMCA7_CON16   0x036C
#define VSRMCA7_CON17   0x036E
#define VSRMCA7_CON18   0x0370
#define VSRMCA7_CON19   0x0372
#define VSRMCA7_CON20   0x0374
#define VSRMCA7_CON21   0x0376
#define VDRM_CON0       0x0378
#define VDRM_CON1       0x037A
#define VDRM_CON2       0x037C
#define VDRM_CON3       0x037E
#define VDRM_CON4       0x0380
#define VDRM_CON5       0x0382
#define VDRM_CON6       0x0384
#define VDRM_CON7       0x0386
#define VDRM_CON8       0x0388
#define VDRM_CON9       0x038A
#define VDRM_CON10      0x038C
#define VDRM_CON11      0x038E
#define VDRM_CON12      0x0390
#define VDRM_CON13      0x0392
#define VDRM_CON14      0x0394
#define VDRM_CON15      0x0396
#define VDRM_CON16      0x0398
#define VDRM_CON17      0x039A
#define VDRM_CON18      0x039C
#define BUCK_K_CON0     0x039E
#define BUCK_K_CON1     0x03A0
#define ANALDO_CON0     0x0400
#define ANALDO_CON1     0x0402
#define ANALDO_CON2     0x0404
#define ANALDO_CON3     0x0406
#define ANALDO_CON4     0x0408
#define ANALDO_CON5     0x040A
#define ANALDO_CON6     0x040C
#define ANALDO_CON7     0x040E
#define DIGLDO_CON0     0x0410
#define DIGLDO_CON1     0x0412
#define DIGLDO_CON2     0x0414
#define DIGLDO_CON3     0x0416
#define DIGLDO_CON4     0x0418
#define DIGLDO_CON5     0x041A
#define DIGLDO_CON6     0x041C
#define DIGLDO_CON7     0x041E
#define DIGLDO_CON8     0x0420
#define DIGLDO_CON9     0x0422
#define DIGLDO_CON10    0x0424
#define DIGLDO_CON11    0x0426
#define DIGLDO_CON12    0x0428
#define DIGLDO_CON13    0x042A
#define DIGLDO_CON14    0x042C
#define DIGLDO_CON15    0x042E
#define DIGLDO_CON16    0x0430
#define DIGLDO_CON17    0x0432
#define DIGLDO_CON18    0x0434
#define DIGLDO_CON19    0x0436
#define DIGLDO_CON20    0x0438
#define DIGLDO_CON21    0x043A
#define DIGLDO_CON22    0x043C
#define DIGLDO_CON23    0x043E
#define DIGLDO_CON24    0x0440
#define DIGLDO_CON25    0x0442
#define DIGLDO_CON26    0x0444
#define DIGLDO_CON27    0x0446
#define DIGLDO_CON28    0x0448
#define DIGLDO_CON29    0x044A
#define DIGLDO_CON30    0x044C
#define DIGLDO_CON31    0x044E
#define DIGLDO_CON32    0x0450
#define DIGLDO_CON33    0x45A
#define STRUP_CON0      0x0500
#define STRUP_CON2      0x0502
#define STRUP_CON3      0x0504
#define STRUP_CON4      0x0506
#define STRUP_CON5      0x0508
#define STRUP_CON6      0x050A
#define STRUP_CON7      0x050C
#define STRUP_CON8      0x050E
#define STRUP_CON9      0x0510
#define STRUP_CON10     0x0512
#define AUXADC_ADC0     0x0514
#define AUXADC_ADC1     0x0516
#define AUXADC_ADC2     0x0518
#define AUXADC_ADC3     0x051A
#define AUXADC_ADC4     0x051C
#define AUXADC_ADC5     0x051E
#define AUXADC_ADC6     0x0520
#define AUXADC_ADC7     0x0522
#define AUXADC_ADC8     0x0524
#define AUXADC_ADC9     0x0526
#define AUXADC_ADC10    0x0528
#define AUXADC_ADC11    0x052A
#define AUXADC_ADC12    0x052C
#define AUXADC_ADC13    0x052E
#define AUXADC_ADC14    0x0530
#define AUXADC_ADC15    0x0532
#define AUXADC_ADC16    0x0534
#define AUXADC_ADC17    0x0536
#define AUXADC_ADC18    0x0538
#define AUXADC_ADC19    0x053A
#define AUXADC_ADC20    0x053C
#define AUXADC_ADC21    0x053E
#define AUXADC_ADC22    0x0540
#define AUXADC_CON0     0x0542
#define AUXADC_CON1     0x0544
#define AUXADC_CON2     0x0546
#define AUXADC_CON3     0x0548
#define AUXADC_CON4     0x054A
#define AUXADC_CON5     0x054C
#define AUXADC_CON6     0x054E
#define AUXADC_CON7     0x0550
#define AUXADC_CON8     0x0552
#define AUXADC_CON9     0x0554
#define AUXADC_CON10    0x0556
#define AUXADC_CON11    0x0558
#define AUXADC_CON12    0x055A
#define AUXADC_CON13    0x055C
#define AUXADC_CON14    0x055E
#define FLASH_CON0      0x0560
#define FLASH_CON1      0x0562
#define FLASH_CON2      0x0564
#define KPLED_CON0      0x0566
#define KPLED_CON1      0x0568
#define KPLED_CON2      0x056A
#define ISINKS_CON0     0x056C
#define ISINKS_CON1     0x056E
#define ISINKS_CON2     0x0570
#define ISINKS_CON3     0x0572
#define ISINKS_CON4     0x0574
#define ISINKS_CON5     0x0576
#define ISINKS_CON6     0x0578
#define ISINKS_CON7     0x057A
#define ISINKS_CON8     0x057C
#define ISINKS_CON9     0x057E
#define ISINKS_CON10    0x0580
#define ISINKS_CON11    0x0582
#define ACCDET_CON0     0x0584
#define ACCDET_CON1     0x0586
#define ACCDET_CON2     0x0588
#define ACCDET_CON3     0x058A
#define ACCDET_CON4     0x058C
#define ACCDET_CON5     0x058E
#define ACCDET_CON6     0x0590
#define ACCDET_CON7     0x0592
#define ACCDET_CON8     0x0594
#define ACCDET_CON9     0x0596
#define ACCDET_CON10    0x0598
#define ACCDET_CON11    0x059A
#define ACCDET_CON12    0x059C
#define ACCDET_CON13    0x059E
#define ACCDET_CON14    0x05A0
#define ACCDET_CON15    0x05A2
#define ACCDET_CON16    0x05A4
#define SPK_CON0        0x0600
#define SPK_CON1        0x0602
#define SPK_CON2        0x0604
#define SPK_CON3        0x0606
#define SPK_CON4        0x0608
#define SPK_CON5        0x060A
#define SPK_CON6        0x060C
#define SPK_CON7        0x060E
#define SPK_CON8        0x0610
#define SPK_CON9        0x0612
#define SPK_CON10       0x0614
#define SPK_CON11       0x0616
#define FGADC_CON0      0x0618
#define FGADC_CON1      0x061A
#define FGADC_CON2      0x061C
#define FGADC_CON3      0x061E
#define FGADC_CON4      0x0620
#define FGADC_CON5      0x0622
#define FGADC_CON6      0x0624
#define FGADC_CON7      0x0626
#define FGADC_CON8      0x0628
#define FGADC_CON9      0x062A
#define FGADC_CON10     0x062C
#define FGADC_CON11     0x062E
#define FGADC_CON12     0x0630
#define FGADC_CON13     0x0632
#define FGADC_CON14     0x0634
#define FGADC_CON15     0x0636
#define FGADC_CON16     0x0638
#define FGADC_CON17     0x063A
#define FGADC_CON18     0x063C
#define FGADC_CON19     0x063E
#define RTC_MIX_CON0    0x0640
#define RTC_MIX_CON1    0x0642
#define AUDDAC_CON0     0x0700
#define AUDBUF_CFG0     0x0702
#define AUDBUF_CFG1     0x0704
#define AUDBUF_CFG2     0x0706
#define AUDBUF_CFG3     0x0708
#define AUDBUF_CFG4     0x070A
#define IBIASDIST_CFG0  0x070C
#define AUDACCDEPOP_CFG0 0x070E
#define AUD_IV_CFG0     0x0710
#define AUDCLKGEN_CFG0  0x0712
#define AUDLDO_CFG0     0x0714
#define AUDLDO_CFG1     0x0716
#define AUDNVREGGLB_CFG0 0x0718
#define AUD_NCP0        0x071A
#define AUDPREAMP_CON0  0x071C
#define AUDADC_CON0     0x071E
#define AUDADC_CON1     0x0720
#define AUDADC_CON2     0x0722
#define AUDADC_CON3     0x0724
#define AUDADC_CON4     0x0726
#define AUDADC_CON5     0x0728
#define AUDADC_CON6     0x072A
#define AUDDIGMI_CON0   0x072C
#define AUDLSBUF_CON0   0x072E
#define AUDLSBUF_CON1   0x0730
#define AUDENCSPARE_CON0 0x0732
#define AUDENCCLKSQ_CON0 0x0734
#define AUDPREAMPGAIN_CON0 0x0736
#define ZCD_CON0        0x0738
#define ZCD_CON1        0x073A
#define ZCD_CON2        0x073C
#define ZCD_CON3        0x073E
#define ZCD_CON4        0x0740
#define ZCD_CON5        0x0742
#define NCP_CLKDIV_CON0 0x0744
#define NCP_CLKDIV_CON1 0x0746
#define RG_DCXO_S2A_CON0 0x800
#define RG_DCXO_S2A_TMP1_CON0 0x802
#define RG_DCXO_S2A_TMP1_CON1 0x804
#define RG_DCXO_S2A_TMP2_CON0 0x806
#define RG_DCXO_S2A_TMP2_CON1 0x808
#define RG_DCXO_S2A_TMP3_CON0 0x80a
#define RG_DCXO_S2A_TMP3_CON1 0x80c
#define RG_DCXO_S2A_FINAL_CON0 0x80e
#define RG_DCXO_S2A_FINAL_CON1 0x810
#define RG_DCXO_A2S_CON0 0x812
#define RG_DCXO_A2S_TMP1_CON0 0x814
#define RG_DCXO_A2S_TMP1_CON1 0x816
#define RG_DCXO_A2S_TMP2_CON0 0x818
#define RG_DCXO_A2S_TMP2_CON1 0x81a
#define RG_DCXO_A2S_TMP3_CON0 0x81c
#define RG_DCXO_A2S_TMP3_CON1 0x81e
#define RG_DCXO_A2S_FINAL_CON0 0x820
#define RG_DCXO_A2S_FINAL_CON1 0x822
#define RG_DCXO_POR2_CON0 0x824
#define RG_DCXO_POR2_CON1 0x826
#define RG_DCXO_POR2_CON2 0x828
#define RG_DCXO_POR2_TMP1_CON0 0x82a
#define RG_DCXO_POR2_TMP1_CON1 0x82c
#define RG_DCXO_POR2_TMP2_CON0 0x82e
#define RG_DCXO_POR2_TMP2_CON1 0x830
#define RG_DCXO_POR2_TMP3_CON0 0x832
#define RG_DCXO_POR2_TMP3_CON1 0x834
#define RG_DCXO_POR2_FINAL_CON0 0x836
#define RG_DCXO_POR2_FINAL_CON1 0x838
#define RG_DCXO_CON0    0x83a
#define RG_DCXO_CON1    0x83c
#define RG_DCXO_CON2    0x83e
#define RG_DCXO_CON3    0x840
#define RG_DCXO_MANUAL_CON3 0x842
#define RG_DCXO_MANUAL_CON1 0x844
#define RG_DCXO_MANUAL_CON2 0x846
#define RG_DCXO_ANALOG_CON0 0x848
#define RG_DCXO_ANALOG_CON1 0x84a
#define RG_DCXO_ANALOG_CON2 0x84c
#define RG_DCXO_ANALOG_CON3 0x84e
#define RG_DCXO_ANALOG_CON4 0x850
#define RG_DCXO_FORCE_MODE0 0x852
#define RG_DCXO_FORCE_MODE1 0x854
#define RG_DCXO_FORCE_MODE2 0x856
#define RG_DCXO_S2A_CON1 0x858
#define RG_DCXO_A2S_CON1 0x85a
#define RG_DCXO_POR2_CON3 0x85c
#define RG_DCXO_FORCE_MODE3 0x85e
#define RG_DCXO_ANALOG_RO0 0x860
#define RG_DCXO_TRIM_RO0 0x862
#define RG_DCXO_TRIM_RO1 0x864

//mask is HEX
//shift is Integer
#define PMIC_RGS_VCDT_HV_DET_MASK 0x1
#define PMIC_RGS_VCDT_HV_DET_SHIFT 7
#define PMIC_RGS_VCDT_LV_DET_MASK 0x1
#define PMIC_RGS_VCDT_LV_DET_SHIFT 6
#define PMIC_RGS_CHRDET_MASK 0x1
#define PMIC_RGS_CHRDET_SHIFT 5
#define PMIC_RG_CHR_EN_MASK 0x1
#define PMIC_RG_CHR_EN_SHIFT 4
#define PMIC_RG_CSDAC_EN_MASK 0x1
#define PMIC_RG_CSDAC_EN_SHIFT 3
#define PMIC_RG_PCHR_AUTOMODE_MASK 0x1
#define PMIC_RG_PCHR_AUTOMODE_SHIFT 2
#define PMIC_RGS_CHR_LDO_DET_MASK 0x1
#define PMIC_RGS_CHR_LDO_DET_SHIFT 1
#define PMIC_RG_VCDT_HV_EN_MASK 0x1
#define PMIC_RG_VCDT_HV_EN_SHIFT 0
#define PMIC_RG_VCDT_HV_VTH_MASK 0xF
#define PMIC_RG_VCDT_HV_VTH_SHIFT 4
#define PMIC_RG_VCDT_LV_VTH_MASK 0xF
#define PMIC_RG_VCDT_LV_VTH_SHIFT 0
#define PMIC_RGS_VBAT_CC_DET_MASK 0x1
#define PMIC_RGS_VBAT_CC_DET_SHIFT 7
#define PMIC_RGS_VBAT_CV_DET_MASK 0x1
#define PMIC_RGS_VBAT_CV_DET_SHIFT 6
#define PMIC_RGS_CS_DET_MASK 0x1
#define PMIC_RGS_CS_DET_SHIFT 5
#define PMIC_RG_CS_EN_MASK 0x1
#define PMIC_RG_CS_EN_SHIFT 3
#define PMIC_RG_VBAT_CC_EN_MASK 0x1
#define PMIC_RG_VBAT_CC_EN_SHIFT 2
#define PMIC_RG_VBAT_CV_EN_MASK 0x1
#define PMIC_RG_VBAT_CV_EN_SHIFT 1
#define PMIC_RG_VBAT_CC_VTH_MASK 0x3
#define PMIC_RG_VBAT_CC_VTH_SHIFT 6
#define PMIC_RG_VBAT_CV_VTH_MASK 0x1F
#define PMIC_RG_VBAT_CV_VTH_SHIFT 0
#define PMIC_RG_CS_VTH_MASK 0xF
#define PMIC_RG_CS_VTH_SHIFT 0
#define PMIC_RG_PCHR_TOLTC_MASK 0x7
#define PMIC_RG_PCHR_TOLTC_SHIFT 4
#define PMIC_RG_PCHR_TOHTC_MASK 0x7
#define PMIC_RG_PCHR_TOHTC_SHIFT 0
#define PMIC_RGS_VBAT_OV_DET_MASK 0x1
#define PMIC_RGS_VBAT_OV_DET_SHIFT 6
#define PMIC_RG_VBAT_OV_DEG_MASK 0x1
#define PMIC_RG_VBAT_OV_DEG_SHIFT 5
#define PMIC_RG_VBAT_OV_VTH_MASK 0x7
#define PMIC_RG_VBAT_OV_VTH_SHIFT 1
#define PMIC_RG_VBAT_OV_EN_MASK 0x1
#define PMIC_RG_VBAT_OV_EN_SHIFT 0
#define PMIC_RGS_BATON_UNDET_MASK 0x1
#define PMIC_RGS_BATON_UNDET_SHIFT 12
#define PMIC_RG_BATON_HT_TRIM_SET_MASK 0x1
#define PMIC_RG_BATON_HT_TRIM_SET_SHIFT 7
#define PMIC_RG_BATON_HT_TRIM_MASK 0x7
#define PMIC_RG_BATON_HT_TRIM_SHIFT 4
#define PMIC_BATON_TDET_EN_MASK 0x1
#define PMIC_BATON_TDET_EN_SHIFT 2
#define PMIC_RG_BATON_HT_EN_MASK 0x1
#define PMIC_RG_BATON_HT_EN_SHIFT 1
#define PMIC_RG_BATON_EN_MASK 0x1
#define PMIC_RG_BATON_EN_SHIFT 0
#define PMIC_RG_CSDAC_DATA_MASK 0x3FF
#define PMIC_RG_CSDAC_DATA_SHIFT 0
#define PMIC_RG_FRC_CSVTH_USBDL_MASK 0x1
#define PMIC_RG_FRC_CSVTH_USBDL_SHIFT 0
#define PMIC_RGS_OTG_BVALID_DET_MASK 0x1
#define PMIC_RGS_OTG_BVALID_DET_SHIFT 6
#define PMIC_RG_OTG_BVALID_EN_MASK 0x1
#define PMIC_RG_OTG_BVALID_EN_SHIFT 5
#define PMIC_RG_PCHR_FLAG_EN_MASK 0x1
#define PMIC_RG_PCHR_FLAG_EN_SHIFT 4
#define PMIC_RGS_PCHR_FLAG_OUT_MASK 0xF
#define PMIC_RGS_PCHR_FLAG_OUT_SHIFT 0
#define PMIC_RG_PCHR_FLAG_SEL_MASK 0x3F
#define PMIC_RG_PCHR_FLAG_SEL_SHIFT 0
#define PMIC_RG_PCHR_FT_CTRL_MASK 0x7
#define PMIC_RG_PCHR_FT_CTRL_SHIFT 4
#define PMIC_RG_PCHR_RST_MASK 0x1
#define PMIC_RG_PCHR_RST_SHIFT 2
#define PMIC_RG_CSDAC_TESTMODE_MASK 0x1
#define PMIC_RG_CSDAC_TESTMODE_SHIFT 1
#define PMIC_RG_PCHR_TESTMODE_MASK 0x1
#define PMIC_RG_PCHR_TESTMODE_SHIFT 0
#define PMIC_RG_CHRWDT_WR_MASK 0x1
#define PMIC_RG_CHRWDT_WR_SHIFT 8
#define PMIC_RG_CHRWDT_EN_MASK 0x1
#define PMIC_RG_CHRWDT_EN_SHIFT 4
#define PMIC_RG_CHRWDT_TD_MASK 0xF
#define PMIC_RG_CHRWDT_TD_SHIFT 0
#define PMIC_RG_PCHR_RV_MASK 0xFF
#define PMIC_RG_PCHR_RV_SHIFT 0
#define PMIC_RGS_CHRWDT_OUT_MASK 0x1
#define PMIC_RGS_CHRWDT_OUT_SHIFT 2
#define PMIC_RG_CHRWDT_FLAG_WR_MASK 0x1
#define PMIC_RG_CHRWDT_FLAG_WR_SHIFT 1
#define PMIC_RG_CHRWDT_INT_EN_MASK 0x1
#define PMIC_RG_CHRWDT_INT_EN_SHIFT 0
#define PMIC_ADCIN_VCHR_EN_MASK 0x1
#define PMIC_ADCIN_VCHR_EN_SHIFT 12
#define PMIC_ADCIN_VSEN_EN_MASK 0x1
#define PMIC_ADCIN_VSEN_EN_SHIFT 11
#define PMIC_ADCIN_VBAT_EN_MASK 0x1
#define PMIC_ADCIN_VBAT_EN_SHIFT 10
#define PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_MASK 0x1
#define PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_SHIFT 9
#define PMIC_ADCIN_VSEN_MUX_EN_MASK 0x1
#define PMIC_ADCIN_VSEN_MUX_EN_SHIFT 8
#define PMIC_RG_USBDL_SET_MASK 0x1
#define PMIC_RG_USBDL_SET_SHIFT 3
#define PMIC_RG_USBDL_RST_MASK 0x1
#define PMIC_RG_USBDL_RST_SHIFT 2
#define PMIC_RG_UVLO_VTHL_MASK 0x3
#define PMIC_RG_UVLO_VTHL_SHIFT 0
#define PMIC_RG_BGR_UNCHOP_MASK 0x1
#define PMIC_RG_BGR_UNCHOP_SHIFT 5
#define PMIC_RG_BGR_UNCHOP_PH_MASK 0x1
#define PMIC_RG_BGR_UNCHOP_PH_SHIFT 4
#define PMIC_RG_BGR_RSEL_MASK 0x7
#define PMIC_RG_BGR_RSEL_SHIFT 0
#define PMIC_RGS_BC11_CMP_OUT_MASK 0x1
#define PMIC_RGS_BC11_CMP_OUT_SHIFT 7
#define PMIC_RG_BC11_VSRC_EN_MASK 0x3
#define PMIC_RG_BC11_VSRC_EN_SHIFT 2
#define PMIC_RG_BC11_RST_MASK 0x1
#define PMIC_RG_BC11_RST_SHIFT 1
#define PMIC_RG_BC11_BB_CTRL_MASK 0x1
#define PMIC_RG_BC11_BB_CTRL_SHIFT 0
#define PMIC_RG_BC11_BIAS_EN_MASK 0x1
#define PMIC_RG_BC11_BIAS_EN_SHIFT 8
#define PMIC_RG_BC11_IPU_EN_MASK 0x3
#define PMIC_RG_BC11_IPU_EN_SHIFT 6
#define PMIC_RG_BC11_IPD_EN_MASK 0x3
#define PMIC_RG_BC11_IPD_EN_SHIFT 4
#define PMIC_RG_BC11_CMP_EN_MASK 0x3
#define PMIC_RG_BC11_CMP_EN_SHIFT 2
#define PMIC_RG_BC11_VREF_VTH_MASK 0x3
#define PMIC_RG_BC11_VREF_VTH_SHIFT 0
#define PMIC_RG_CSDAC_STP_DEC_MASK 0x7
#define PMIC_RG_CSDAC_STP_DEC_SHIFT 4
#define PMIC_RG_CSDAC_STP_INC_MASK 0x7
#define PMIC_RG_CSDAC_STP_INC_SHIFT 0
#define PMIC_RG_CSDAC_STP_MASK 0x7
#define PMIC_RG_CSDAC_STP_SHIFT 4
#define PMIC_RG_CSDAC_DLY_MASK 0x7
#define PMIC_RG_CSDAC_DLY_SHIFT 0
#define PMIC_RG_CHRIND_DIMMING_MASK 0x1
#define PMIC_RG_CHRIND_DIMMING_SHIFT 7
#define PMIC_RG_CHRIND_ON_MASK 0x1
#define PMIC_RG_CHRIND_ON_SHIFT 6
#define PMIC_RG_LOW_ICH_DB_MASK 0x3F
#define PMIC_RG_LOW_ICH_DB_SHIFT 0
#define PMIC_RG_ULC_DET_EN_MASK 0x1
#define PMIC_RG_ULC_DET_EN_SHIFT 7
#define PMIC_RG_HWCV_EN_MASK 0x1
#define PMIC_RG_HWCV_EN_SHIFT 6
#define PMIC_RG_TRACKING_EN_MASK 0x1
#define PMIC_RG_TRACKING_EN_SHIFT 4
#define PMIC_RG_CSDAC_MODE_MASK 0x1
#define PMIC_RG_CSDAC_MODE_SHIFT 2
#define PMIC_RG_VCDT_MODE_MASK 0x1
#define PMIC_RG_VCDT_MODE_SHIFT 1
#define PMIC_RG_CV_MODE_MASK 0x1
#define PMIC_RG_CV_MODE_SHIFT 0
#define PMIC_RG_ICHRG_TRIM_MASK 0xF
#define PMIC_RG_ICHRG_TRIM_SHIFT 4
#define PMIC_RG_BGR_TRIM_EN_MASK 0x1
#define PMIC_RG_BGR_TRIM_EN_SHIFT 0
#define PMIC_RG_BGR_TRIM_MASK 0x1F
#define PMIC_RG_BGR_TRIM_SHIFT 0
#define PMIC_RG_OVP_TRIM_MASK 0xF
#define PMIC_RG_OVP_TRIM_SHIFT 0
#define PMIC_RG_BGR_TEST_RSTB_MASK 0x1
#define PMIC_RG_BGR_TEST_RSTB_SHIFT 7
#define PMIC_RG_BGR_TEST_EN_MASK 0x1
#define PMIC_RG_BGR_TEST_EN_SHIFT 6
#define PMIC_QI_BGR_EXT_BUF_EN_MASK 0x1
#define PMIC_QI_BGR_EXT_BUF_EN_SHIFT 5
#define PMIC_CHR_OSC_TRIM_MASK 0x1F
#define PMIC_CHR_OSC_TRIM_SHIFT 0
#define PMIC_RG_DAC_USBDL_MAX_MASK 0x3FF
#define PMIC_RG_DAC_USBDL_MAX_SHIFT 0
#define PMIC_RG_PCHR_RSV_MASK 0xFF
#define PMIC_RG_PCHR_RSV_SHIFT 0
#define PMIC_CID_MASK 0xFFFF
#define PMIC_CID_SHIFT 0
#define PMIC_RG_STRUP_6M_PDN_MASK 0x1
#define PMIC_RG_STRUP_6M_PDN_SHIFT 15
#define PMIC_RG_ACCDET_CK_PDN_MASK 0x1
#define PMIC_RG_ACCDET_CK_PDN_SHIFT 14
#define PMIC_RG_AUXADC_CK_PDN_MASK 0x1
#define PMIC_RG_AUXADC_CK_PDN_SHIFT 13
#define PMIC_RG_SMPS_CK_DIV_PDN_MASK 0x1
#define PMIC_RG_SMPS_CK_DIV_PDN_SHIFT 12
#define PMIC_RG_SMPS_CK_DIV2_PDN_MASK 0x1
#define PMIC_RG_SMPS_CK_DIV2_PDN_SHIFT 11
#define PMIC_RG_SPK_DIV_PDN_MASK 0x1
#define PMIC_RG_SPK_DIV_PDN_SHIFT 10
#define PMIC_RG_SPK_PWM_DIV_PDN_MASK 0x1
#define PMIC_RG_SPK_PWM_DIV_PDN_SHIFT 9
#define PMIC_RG_RTC_MCLK_PDN_MASK 0x1
#define PMIC_RG_RTC_MCLK_PDN_SHIFT 8
#define PMIC_RG_BST_DRV_1M_CK_PDN_MASK 0x1
#define PMIC_RG_BST_DRV_1M_CK_PDN_SHIFT 7
#define PMIC_RG_FGADC_ANA_CK_PDN_MASK 0x1
#define PMIC_RG_FGADC_ANA_CK_PDN_SHIFT 6
#define PMIC_RG_FGADC_CK_PDN_MASK 0x1
#define PMIC_RG_FGADC_CK_PDN_SHIFT 5
#define PMIC_RG_EFUSE_CK_PDN_MASK 0x1
#define PMIC_RG_EFUSE_CK_PDN_SHIFT 4
#define PMIC_RG_PWMOC_CK_PDN_MASK 0x1
#define PMIC_RG_PWMOC_CK_PDN_SHIFT 3
#define PMIC_RG_SPK_CK_PDN_MASK 0x1
#define PMIC_RG_SPK_CK_PDN_SHIFT 2
#define PMIC_RG_AUD_13M_PDN_MASK 0x1
#define PMIC_RG_AUD_13M_PDN_SHIFT 1
#define PMIC_RG_AUD_26M_PDN_MASK 0x1
#define PMIC_RG_AUD_26M_PDN_SHIFT 0
#define PMIC_RG_TOP_CKPDN2_RSV_15_MASK 0x1
#define PMIC_RG_TOP_CKPDN2_RSV_15_SHIFT 15
#define PMIC_RG_RTC_75K_CK_PDN_MASK 0x1
#define PMIC_RG_RTC_75K_CK_PDN_SHIFT 14
#define PMIC_RG_STRUP_32K_CK_PDN_MASK 0x1
#define PMIC_RG_STRUP_32K_CK_PDN_SHIFT 13
#define PMIC_RG_BUCK_1M_CK_PDN_MASK 0x1
#define PMIC_RG_BUCK_1M_CK_PDN_SHIFT 12
#define PMIC_RG_BUCK32K_PDN_MASK 0x1
#define PMIC_RG_BUCK32K_PDN_SHIFT 11
#define PMIC_RG_BUCK_ANA_CK_PDN_MASK 0x1
#define PMIC_RG_BUCK_ANA_CK_PDN_SHIFT 10
#define PMIC_RG_BUCK_CK_PDN_MASK 0x1
#define PMIC_RG_BUCK_CK_PDN_SHIFT 9
#define PMIC_RG_CHR1M_CK_PDN_MASK 0x1
#define PMIC_RG_CHR1M_CK_PDN_SHIFT 8
#define PMIC_RG_DRV_32K_CK_PDN_MASK 0x1
#define PMIC_RG_DRV_32K_CK_PDN_SHIFT 7
#define PMIC_RG_INTRP_CK_PDN_MASK 0x1
#define PMIC_RG_INTRP_CK_PDN_SHIFT 6
#define PMIC_RG_LDOSTB_1M_CK_PDN_MASK 0x1
#define PMIC_RG_LDOSTB_1M_CK_PDN_SHIFT 5
#define PMIC_RG_PCHR_32K_CK_PDN_MASK 0x1
#define PMIC_RG_PCHR_32K_CK_PDN_SHIFT 4
#define PMIC_RG_RTC_32K_CK_PDN_MASK 0x1
#define PMIC_RG_RTC_32K_CK_PDN_SHIFT 3
#define PMIC_RG_STRUP_75K_CK_PDN_MASK 0x1
#define PMIC_RG_STRUP_75K_CK_PDN_SHIFT 2
#define PMIC_RG_FQMTR_PDN_MASK 0x1
#define PMIC_RG_FQMTR_PDN_SHIFT 1
#define PMIC_RG_RTC32K_1V8_PDN_MASK 0x1
#define PMIC_RG_RTC32K_1V8_PDN_SHIFT 0
#define PMIC_RG_TOP_GPIO_CKPDN_RSV_15_14_MASK 0x3
#define PMIC_RG_TOP_GPIO_CKPDN_RSV_15_14_SHIFT 14
#define PMIC_RG_GPIO32K_PDN_MASK 0x7F
#define PMIC_RG_GPIO32K_PDN_SHIFT 7
#define PMIC_RG_GPIO26M_PDN_MASK 0x7F
#define PMIC_RG_GPIO26M_PDN_SHIFT 0
#define PMIC_RG_TOP_RST_CON_RSV_15_9_MASK 0x7F
#define PMIC_RG_TOP_RST_CON_RSV_15_9_SHIFT 9
#define PMIC_RG_FQMTR_RST_MASK 0x1
#define PMIC_RG_FQMTR_RST_SHIFT 8
#define PMIC_RG_RTC_RST_MASK 0x1
#define PMIC_RG_RTC_RST_SHIFT 7
#define PMIC_RG_DRIVER_RST_MASK 0x1
#define PMIC_RG_DRIVER_RST_SHIFT 6
#define PMIC_RG_SPK_RST_MASK 0x1
#define PMIC_RG_SPK_RST_SHIFT 5
#define PMIC_RG_ACCDET_RST_MASK 0x1
#define PMIC_RG_ACCDET_RST_SHIFT 4
#define PMIC_RG_FGADC_RST_MASK 0x1
#define PMIC_RG_FGADC_RST_SHIFT 3
#define PMIC_RG_AUDIO_RST_MASK 0x1
#define PMIC_RG_AUDIO_RST_SHIFT 2
#define PMIC_RG_AUXADC_RST_MASK 0x1
#define PMIC_RG_AUXADC_RST_SHIFT 1
#define PMIC_RG_EFUSE_MAN_RST_MASK 0x1
#define PMIC_RG_EFUSE_MAN_RST_SHIFT 0
#define PMIC_RG_WRP_PDN_MASK 0x1
#define PMIC_RG_WRP_PDN_SHIFT 7
#define PMIC_RG_WRP_32K_PDN_MASK 0x1
#define PMIC_RG_WRP_32K_PDN_SHIFT 6
#define PMIC_RG_WRP_EINT_PDN_MASK 0x1
#define PMIC_RG_WRP_EINT_PDN_SHIFT 5
#define PMIC_RG_WRP_KP_PDN_MASK 0x1
#define PMIC_RG_WRP_KP_PDN_SHIFT 4
#define PMIC_RG_WRP_PWM_PDN_MASK 0x1
#define PMIC_RG_WRP_PWM_PDN_SHIFT 3
#define PMIC_RG_WRP_I2C2_PDN_MASK 0x1
#define PMIC_RG_WRP_I2C2_PDN_SHIFT 2
#define PMIC_RG_WRP_I2C1_PDN_MASK 0x1
#define PMIC_RG_WRP_I2C1_PDN_SHIFT 1
#define PMIC_RG_WRP_I2C0_PDN_MASK 0x1
#define PMIC_RG_WRP_I2C0_PDN_SHIFT 0
#define PMIC_RG_WRP_RST_MASK 0x1
#define PMIC_RG_WRP_RST_SHIFT 6
#define PMIC_RG_EINT_RST_MASK 0x1
#define PMIC_RG_EINT_RST_SHIFT 5
#define PMIC_RG_KP_RST_MASK 0x1
#define PMIC_RG_KP_RST_SHIFT 4
#define PMIC_RG_PWM_RST_MASK 0x1
#define PMIC_RG_PWM_RST_SHIFT 3
#define PMIC_RG_I2C2_RST_MASK 0x1
#define PMIC_RG_I2C2_RST_SHIFT 2
#define PMIC_RG_I2C1_RST_MASK 0x1
#define PMIC_RG_I2C1_RST_SHIFT 1
#define PMIC_RG_I2C0_RST_MASK 0x1
#define PMIC_RG_I2C0_RST_SHIFT 0
#define PMIC_RG_PWRKEY_RST_TD_MASK 0x3
#define PMIC_RG_PWRKEY_RST_TD_SHIFT 8
#define PMIC_RG_PWRRST_TMR_DIS_MASK 0x1
#define PMIC_RG_PWRRST_TMR_DIS_SHIFT 7
#define PMIC_RG_PWRKEY_RST_EN_MASK 0x1
#define PMIC_RG_PWRKEY_RST_EN_SHIFT 6
#define PMIC_RG_HOMEKEY_RST_EN_MASK 0x1
#define PMIC_RG_HOMEKEY_RST_EN_SHIFT 5
#define PMIC_RG_RST_PART_SEL_MASK 0x1
#define PMIC_RG_RST_PART_SEL_SHIFT 4
#define PMIC_RG_TOP_RST_MISC_RSV_3_MASK 0x1
#define PMIC_RG_TOP_RST_MISC_RSV_3_SHIFT 3
#define PMIC_RG_STRUP_MAN_RST_EN_MASK 0x1
#define PMIC_RG_STRUP_MAN_RST_EN_SHIFT 2
#define PMIC_RG_SYSRSTB_EN_MASK 0x1
#define PMIC_RG_SYSRSTB_EN_SHIFT 1
#define PMIC_RG_AP_RST_DIS_MASK 0x1
#define PMIC_RG_AP_RST_DIS_SHIFT 0
#define PMIC_RG_OSC_SEL_ALIGN_DIS_MASK 0x1
#define PMIC_RG_OSC_SEL_ALIGN_DIS_SHIFT 15
#define PMIC_rg_spitxck_inv_sel_MASK 0x1
#define PMIC_rg_spitxck_inv_sel_SHIFT 14
#define PMIC_RG_OSC_HW_SEL_MASK 0x1
#define PMIC_RG_OSC_HW_SEL_SHIFT 13
#define PMIC_RG_CLKSQ_HW_AUTO_EN_MASK 0x1
#define PMIC_RG_CLKSQ_HW_AUTO_EN_SHIFT 12
#define PMIC_RG_SRCLKPERI_HW_AUTO_EN_MASK 0x1
#define PMIC_RG_SRCLKPERI_HW_AUTO_EN_SHIFT 11
#define PMIC_RG_SRCLKMD2_HW_AUTO_EN_MASK 0x1
#define PMIC_RG_SRCLKMD2_HW_AUTO_EN_SHIFT 10
#define PMIC_RG_SRCVOLT_HW_AUTO_EN_MASK 0x1
#define PMIC_RG_SRCVOLT_HW_AUTO_EN_SHIFT 9
#define PMIC_RG_OSC_SEL_AUTO_MASK 0x1
#define PMIC_RG_OSC_SEL_AUTO_SHIFT 8
#define PMIC_RG_TOP_CKCON1_RSV_07_MASK 0x1
#define PMIC_RG_TOP_CKCON1_RSV_07_SHIFT 7
#define PMIC_RG_SMPS_DIV2_SRC_AUTOFF_DIS_MASK 0x1
#define PMIC_RG_SMPS_DIV2_SRC_AUTOFF_DIS_SHIFT 6
#define PMIC_RG_SMPS_AUTOFF_DIS_MASK 0x1
#define PMIC_RG_SMPS_AUTOFF_DIS_SHIFT 5
#define PMIC_RG_CLKSQ_EN_MASK 0x1
#define PMIC_RG_CLKSQ_EN_SHIFT 4
#define PMIC_RG_SRCLKPERI_EN_MASK 0x1
#define PMIC_RG_SRCLKPERI_EN_SHIFT 3
#define PMIC_RG_SRCLKMD2_EN_MASK 0x1
#define PMIC_RG_SRCLKMD2_EN_SHIFT 2
#define PMIC_RG_SRCVOLT_EN_MASK 0x1
#define PMIC_RG_SRCVOLT_EN_SHIFT 1
#define PMIC_RG_OSC_SEL_MASK 0x1
#define PMIC_RG_OSC_SEL_SHIFT 0
#define PMIC_RG_FQMTR_CKSEL_MASK 0x1
#define PMIC_RG_FQMTR_CKSEL_SHIFT 15
#define PMIC_RG_ACCDET_CKSEL_MASK 0x3
#define PMIC_RG_ACCDET_CKSEL_SHIFT 13
#define PMIC_RG_FG_ANA_CKSEL_MASK 0x1
#define PMIC_RG_FG_ANA_CKSEL_SHIFT 12
#define PMIC_RG_REGCK_SEL_MASK 0x3
#define PMIC_RG_REGCK_SEL_SHIFT 10
#define PMIC_RG_BUCK_2M_SEL_EN_MASK 0x1
#define PMIC_RG_BUCK_2M_SEL_EN_SHIFT 9
#define PMIC_VCA15_6M_SEL_MASK 0x1
#define PMIC_VCA15_6M_SEL_SHIFT 8
#define PMIC_VCORE_6M_SEL_MASK 0x1
#define PMIC_VCORE_6M_SEL_SHIFT 7
#define PMIC_RG_SPK_DIV_SEL_MASK 0x3
#define PMIC_RG_SPK_DIV_SEL_SHIFT 5
#define PMIC_RG_SPK_PWM_DIV_SEL_MASK 0x3
#define PMIC_RG_SPK_PWM_DIV_SEL_SHIFT 3
#define PMIC_RG_AUXADC_DIV_SEL_MASK 0x7
#define PMIC_RG_AUXADC_DIV_SEL_SHIFT 0
#define PMIC_AUXADC_TSTSEL_MASK 0x1
#define PMIC_AUXADC_TSTSEL_SHIFT 15
#define PMIC_PMU75K_TST_DIS_MASK 0x1
#define PMIC_PMU75K_TST_DIS_SHIFT 14
#define PMIC_SMPS_TST_DIS_MASK 0x1
#define PMIC_SMPS_TST_DIS_SHIFT 13
#define PMIC_CHR1M_TST_DIS_MASK 0x1
#define PMIC_CHR1M_TST_DIS_SHIFT 12
#define PMIC_AUD26M_TST_DIS_MASK 0x1
#define PMIC_AUD26M_TST_DIS_SHIFT 11
#define PMIC_RTC32K_TST_DIS_MASK 0x1
#define PMIC_RTC32K_TST_DIS_SHIFT 10
#define PMIC_FG_TST_DIS_MASK 0x1
#define PMIC_FG_TST_DIS_SHIFT 9
#define PMIC_SPK_TST_DIS_MASK 0x1
#define PMIC_SPK_TST_DIS_SHIFT 8
#define PMIC_CHR1M_TSTSEL_MASK 0x3
#define PMIC_CHR1M_TSTSEL_SHIFT 6
#define PMIC_SMPS_TSTSEL_MASK 0x1
#define PMIC_SMPS_TSTSEL_SHIFT 5
#define PMIC_PMU75K_TSTSEL_MASK 0x1
#define PMIC_PMU75K_TSTSEL_SHIFT 4
#define PMIC_AUD26M_TSTSEL_MASK 0x1
#define PMIC_AUD26M_TSTSEL_SHIFT 3
#define PMIC_RTC32K_TSTSEL_MASK 0x1
#define PMIC_RTC32K_TSTSEL_SHIFT 2
#define PMIC_FG_TSTSEL_MASK 0x1
#define PMIC_FG_TSTSEL_SHIFT 1
#define PMIC_SPK_TSTSEL_MASK 0x1
#define PMIC_SPK_TSTSEL_SHIFT 0
#define PMIC_RG_TOP_CKTST2_RSV_15_10_MASK 0x3F
#define PMIC_RG_TOP_CKTST2_RSV_15_10_SHIFT 10
#define PMIC_DCXO_TSTSEL_MASK 0x1
#define PMIC_DCXO_TSTSEL_SHIFT 9
#define PMIC_DCXO_TST_DIS_MASK 0x1
#define PMIC_DCXO_TST_DIS_SHIFT 8
#define PMIC_OSC32_CKSEL_MASK 0x1
#define PMIC_OSC32_CKSEL_SHIFT 7
#define PMIC_XOSC32_TSTSEL_MASK 0x1
#define PMIC_XOSC32_TSTSEL_SHIFT 6
#define PMIC_XOSC32_TST_DIS_MASK 0x1
#define PMIC_XOSC32_TST_DIS_SHIFT 5
#define PMIC_RG_PCHR_TEST_CK_SEL_MASK 0x1
#define PMIC_RG_PCHR_TEST_CK_SEL_SHIFT 4
#define PMIC_RG_STRUP_75K_26M_SEL_MASK 0x1
#define PMIC_RG_STRUP_75K_26M_SEL_SHIFT 3
#define PMIC_ACCDET_TSTSEL_MASK 0x1
#define PMIC_ACCDET_TSTSEL_SHIFT 2
#define PMIC_CK1M2M_TSTSEL_MASK 0x1
#define PMIC_CK1M2M_TSTSEL_SHIFT 1
#define PMIC_BGR_TEST_CK_EN_MASK 0x1
#define PMIC_BGR_TEST_CK_EN_SHIFT 0
#define PMIC_VDRM_DEG_EN_MASK 0x1
#define PMIC_VDRM_DEG_EN_SHIFT 7
#define PMIC_VSRMCA7_DEG_EN_MASK 0x1
#define PMIC_VSRMCA7_DEG_EN_SHIFT 6
#define PMIC_VPCA7_DEG_EN_MASK 0x1
#define PMIC_VPCA7_DEG_EN_SHIFT 5
#define PMIC_VIO18_DEG_EN_MASK 0x1
#define PMIC_VIO18_DEG_EN_SHIFT 4
#define PMIC_VGPU_DEG_EN_MASK 0x1
#define PMIC_VGPU_DEG_EN_SHIFT 3
#define PMIC_VCORE_DEG_EN_MASK 0x1
#define PMIC_VCORE_DEG_EN_SHIFT 2
#define PMIC_VSRMCA15_DEG_EN_MASK 0x1
#define PMIC_VSRMCA15_DEG_EN_SHIFT 1
#define PMIC_VCA15_DEG_EN_MASK 0x1
#define PMIC_VCA15_DEG_EN_SHIFT 0
#define PMIC_OC_GEAR_BVALID_DET_MASK 0x3
#define PMIC_OC_GEAR_BVALID_DET_SHIFT 6
#define PMIC_OC_GEAR_VBATON_UNDET_MASK 0x3
#define PMIC_OC_GEAR_VBATON_UNDET_SHIFT 4
#define PMIC_OC_GEAR_LDO_MASK 0x3
#define PMIC_OC_GEAR_LDO_SHIFT 0
#define PMIC_VGPU_OC_WND_MASK 0x3
#define PMIC_VGPU_OC_WND_SHIFT 14
#define PMIC_VGPU_OC_THD_MASK 0x3
#define PMIC_VGPU_OC_THD_SHIFT 12
#define PMIC_VCORE_OC_WND_MASK 0x3
#define PMIC_VCORE_OC_WND_SHIFT 10
#define PMIC_VCORE_OC_THD_MASK 0x3
#define PMIC_VCORE_OC_THD_SHIFT 8
#define PMIC_VSRMCA15_OC_WND_MASK 0x3
#define PMIC_VSRMCA15_OC_WND_SHIFT 6
#define PMIC_VSRMCA15_OC_THD_MASK 0x3
#define PMIC_VSRMCA15_OC_THD_SHIFT 4
#define PMIC_VCA15_OC_WND_MASK 0x3
#define PMIC_VCA15_OC_WND_SHIFT 2
#define PMIC_VCA15_OC_THD_MASK 0x3
#define PMIC_VCA15_OC_THD_SHIFT 0
#define PMIC_VDRM_OC_WND_MASK 0x3
#define PMIC_VDRM_OC_WND_SHIFT 14
#define PMIC_VDRM_OC_THD_MASK 0x3
#define PMIC_VDRM_OC_THD_SHIFT 12
#define PMIC_VSRMCA7_OC_WND_MASK 0x3
#define PMIC_VSRMCA7_OC_WND_SHIFT 10
#define PMIC_VSRMCA7_OC_THD_MASK 0x3
#define PMIC_VSRMCA7_OC_THD_SHIFT 8
#define PMIC_VPCA7_OC_WND_MASK 0x3
#define PMIC_VPCA7_OC_WND_SHIFT 6
#define PMIC_VPCA7_OC_THD_MASK 0x3
#define PMIC_VPCA7_OC_THD_SHIFT 4
#define PMIC_VIO18_OC_WND_MASK 0x3
#define PMIC_VIO18_OC_WND_SHIFT 2
#define PMIC_VIO18_OC_THD_MASK 0x3
#define PMIC_VIO18_OC_THD_SHIFT 0
#define PMIC_INT_RSV_15_8_MASK 0xFF
#define PMIC_INT_RSV_15_8_SHIFT 8
#define PMIC_IVGEN_EXT_EN_MASK 0x1
#define PMIC_IVGEN_EXT_EN_SHIFT 7
#define PMIC_RG_PWRKEY_RSTB_INT_SEL_MASK 0x1
#define PMIC_RG_PWRKEY_RSTB_INT_SEL_SHIFT 5
#define PMIC_RG_PWRKEY_INT_SEL_MASK 0x1
#define PMIC_RG_PWRKEY_INT_SEL_SHIFT 4
#define PMIC_RG_HOMEKEY_INT_SEL_MASK 0x1
#define PMIC_RG_HOMEKEY_INT_SEL_SHIFT 3
#define PMIC_POLARITY_BVALID_DET_MASK 0x1
#define PMIC_POLARITY_BVALID_DET_SHIFT 2
#define PMIC_POLARITY_VBATON_UNDET_MASK 0x1
#define PMIC_POLARITY_VBATON_UNDET_SHIFT 1
#define PMIC_POLARITY_MASK 0x1
#define PMIC_POLARITY_SHIFT 0
#define PMIC_RG_MON_GRP_SEL_MASK 0xF
#define PMIC_RG_MON_GRP_SEL_SHIFT 8
#define PMIC_RG_MON_FLAG_SEL_MASK 0xFF
#define PMIC_RG_MON_FLAG_SEL_SHIFT 0
#define PMIC_RG_TEST_SPK_PWM_MASK 0x1
#define PMIC_RG_TEST_SPK_PWM_SHIFT 13
#define PMIC_RG_TEST_SPK_MASK 0x1
#define PMIC_RG_TEST_SPK_SHIFT 12
#define PMIC_RG_TEST_STRUP_MASK 0x1
#define PMIC_RG_TEST_STRUP_SHIFT 11
#define PMIC_RG_EFUSE_MODE_MASK 0x1
#define PMIC_RG_EFUSE_MODE_SHIFT 10
#define PMIC_RG_NANDTREE_MODE_MASK 0x1
#define PMIC_RG_NANDTREE_MODE_SHIFT 9
#define PMIC_RG_TEST_AUXADC_MASK 0x1
#define PMIC_RG_TEST_AUXADC_SHIFT 8
#define PMIC_RG_TEST_FGPLL_MASK 0x1
#define PMIC_RG_TEST_FGPLL_SHIFT 7
#define PMIC_RG_TEST_FG_MASK 0x1
#define PMIC_RG_TEST_FG_SHIFT 6
#define PMIC_RG_TEST_AUD_MASK 0x1
#define PMIC_RG_TEST_AUD_SHIFT 5
#define PMIC_RG_TEST_WRAP_MASK 0x1
#define PMIC_RG_TEST_WRAP_SHIFT 4
#define PMIC_RG_TEST_IO_FG_SEL_MASK 0x1
#define PMIC_RG_TEST_IO_FG_SEL_SHIFT 3
#define PMIC_RG_TEST_CLASSD_MASK 0x1
#define PMIC_RG_TEST_CLASSD_SHIFT 2
#define PMIC_RG_TEST_DRIVER_MASK 0x1
#define PMIC_RG_TEST_DRIVER_SHIFT 1
#define PMIC_RG_TEST_BOOST_MASK 0x1
#define PMIC_RG_TEST_BOOST_SHIFT 0
#define PMIC_VRTC_STATUS_MASK 0x1
#define PMIC_VRTC_STATUS_SHIFT 15
#define PMIC_STATUS_VTCXO_EN_MASK 0x1
#define PMIC_STATUS_VTCXO_EN_SHIFT 9
#define PMIC_STATUS_VUSB_EN_MASK 0x1
#define PMIC_STATUS_VUSB_EN_SHIFT 8
#define PMIC_STATUS_VDRM_EN_MASK 0x1
#define PMIC_STATUS_VDRM_EN_SHIFT 7
#define PMIC_STATUS_VSRMCA7_EN_MASK 0x1
#define PMIC_STATUS_VSRMCA7_EN_SHIFT 6
#define PMIC_STATUS_VPCA7_EN_MASK 0x1
#define PMIC_STATUS_VPCA7_EN_SHIFT 5
#define PMIC_STATUS_VIO18_EN_MASK 0x1
#define PMIC_STATUS_VIO18_EN_SHIFT 4
#define PMIC_STATUS_VGPU_EN_MASK 0x1
#define PMIC_STATUS_VGPU_EN_SHIFT 3
#define PMIC_STATUS_VCORE_EN_MASK 0x1
#define PMIC_STATUS_VCORE_EN_SHIFT 2
#define PMIC_STATUS_VSRMCA15_EN_MASK 0x1
#define PMIC_STATUS_VSRMCA15_EN_SHIFT 1
#define PMIC_STATUS_VCA15_EN_MASK 0x1
#define PMIC_STATUS_VCA15_EN_SHIFT 0
#define PMIC_STATUS_VA28_EN_MASK 0x1
#define PMIC_STATUS_VA28_EN_SHIFT 15
#define PMIC_STATUS_VCAMA_EN_MASK 0x1
#define PMIC_STATUS_VCAMA_EN_SHIFT 12
#define PMIC_STATUS_VEMC_3V3_EN_MASK 0x1
#define PMIC_STATUS_VEMC_3V3_EN_SHIFT 10
#define PMIC_STATUS_VCAMD_EN_MASK 0x1
#define PMIC_STATUS_VCAMD_EN_SHIFT 9
#define PMIC_STATUS_VCAMIO_EN_MASK 0x1
#define PMIC_STATUS_VCAMIO_EN_SHIFT 8
#define PMIC_STATUS_VCAMAF_EN_MASK 0x1
#define PMIC_STATUS_VCAMAF_EN_SHIFT 7
#define PMIC_STATUS_VGP4_EN_MASK 0x1
#define PMIC_STATUS_VGP4_EN_SHIFT 6
#define PMIC_STATUS_VGP5_EN_MASK 0x1
#define PMIC_STATUS_VGP5_EN_SHIFT 5
#define PMIC_STATUS_VGP6_EN_MASK 0x1
#define PMIC_STATUS_VGP6_EN_SHIFT 4
#define PMIC_STATUS_VIBR_EN_MASK 0x1
#define PMIC_STATUS_VIBR_EN_SHIFT 3
#define PMIC_STATUS_VIO28_EN_MASK 0x1
#define PMIC_STATUS_VIO28_EN_SHIFT 2
#define PMIC_STATUS_VMC_EN_MASK 0x1
#define PMIC_STATUS_VMC_EN_SHIFT 1
#define PMIC_STATUS_VMCH_EN_MASK 0x1
#define PMIC_STATUS_VMCH_EN_SHIFT 0
#define PMIC_VSRMCA15_PG_DEB_MASK 0x1
#define PMIC_VSRMCA15_PG_DEB_SHIFT 12
#define PMIC_VPCA15_PG_DEB_MASK 0x1
#define PMIC_VPCA15_PG_DEB_SHIFT 11
#define PMIC_VMCH_PG_DEB_MASK 0x1
#define PMIC_VMCH_PG_DEB_SHIFT 10
#define PMIC_VMC_PG_DEB_MASK 0x1
#define PMIC_VMC_PG_DEB_SHIFT 9
#define PMIC_VEMC_PG_DEB_MASK 0x1
#define PMIC_VEMC_PG_DEB_SHIFT 8
#define PMIC_VTCXO_PG_DEB_MASK 0x1
#define PMIC_VTCXO_PG_DEB_SHIFT 7
#define PMIC_VIO28_PG_DEB_MASK 0x1
#define PMIC_VIO28_PG_DEB_SHIFT 6
#define PMIC_VA28_PG_DEB_MASK 0x1
#define PMIC_VA28_PG_DEB_SHIFT 5
#define PMIC_VIO18_PG_DEB_MASK 0x1
#define PMIC_VIO18_PG_DEB_SHIFT 4
#define PMIC_VDRM_PG_DEB_MASK 0x1
#define PMIC_VDRM_PG_DEB_SHIFT 3
#define PMIC_VCORE_PG_DEB_MASK 0x1
#define PMIC_VCORE_PG_DEB_SHIFT 2
#define PMIC_VSRMCA7_PG_DEB_MASK 0x1
#define PMIC_VSRMCA7_PG_DEB_SHIFT 1
#define PMIC_VPCA7_PG_DEB_MASK 0x1
#define PMIC_VPCA7_PG_DEB_SHIFT 0
#define PMIC_RTC_XTAL_DET_RSV_MASK 0xF
#define PMIC_RTC_XTAL_DET_RSV_SHIFT 8
#define PMIC_RTC_XTAL_DET_DONE_MASK 0x1
#define PMIC_RTC_XTAL_DET_DONE_SHIFT 7
#define PMIC_RO_BATON_UNDET_MASK 0x1
#define PMIC_RO_BATON_UNDET_SHIFT 6
#define PMIC_PCHR_CHRDET_MASK 0x1
#define PMIC_PCHR_CHRDET_SHIFT 5
#define PMIC_VBAT_OV_MASK 0x1
#define PMIC_VBAT_OV_SHIFT 4
#define PMIC_PWRKEY_DEB_MASK 0x1
#define PMIC_PWRKEY_DEB_SHIFT 3
#define PMIC_USBDL_MASK 0x1
#define PMIC_USBDL_SHIFT 2
#define PMIC_PWRKEY_RST_B_INT_MASK 0x1
#define PMIC_PWRKEY_RST_B_INT_SHIFT 1
#define PMIC_PMU_TEST_MODE_SCAN_MASK 0x1
#define PMIC_PMU_TEST_MODE_SCAN_SHIFT 0
#define PMIC_OC_STATUS_VTCXO_MASK 0x1
#define PMIC_OC_STATUS_VTCXO_SHIFT 9
#define PMIC_OC_STATUS_VUSB_MASK 0x1
#define PMIC_OC_STATUS_VUSB_SHIFT 8
#define PMIC_OC_STATUS_VDRM_MASK 0x1
#define PMIC_OC_STATUS_VDRM_SHIFT 7
#define PMIC_OC_STATUS_VSRMCA7_MASK 0x1
#define PMIC_OC_STATUS_VSRMCA7_SHIFT 6
#define PMIC_OC_STATUS_VPCA7_MASK 0x1
#define PMIC_OC_STATUS_VPCA7_SHIFT 5
#define PMIC_OC_STATUS_VIO18_MASK 0x1
#define PMIC_OC_STATUS_VIO18_SHIFT 4
#define PMIC_OC_STATUS_VGPU_MASK 0x1
#define PMIC_OC_STATUS_VGPU_SHIFT 3
#define PMIC_OC_STATUS_VCORE_MASK 0x1
#define PMIC_OC_STATUS_VCORE_SHIFT 2
#define PMIC_OC_STATUS_VSRMCA15_MASK 0x1
#define PMIC_OC_STATUS_VSRMCA15_SHIFT 1
#define PMIC_OC_STATUS_VCA15_MASK 0x1
#define PMIC_OC_STATUS_VCA15_SHIFT 0
#define PMIC_OC_STATUS_VA28_MASK 0x1
#define PMIC_OC_STATUS_VA28_SHIFT 13
#define PMIC_OC_STATUS_VCAMA_MASK 0x1
#define PMIC_OC_STATUS_VCAMA_SHIFT 12
#define PMIC_OC_STATUS_VEMC_3V3_MASK 0x1
#define PMIC_OC_STATUS_VEMC_3V3_SHIFT 10
#define PMIC_OC_STATUS_VCAMD_MASK 0x1
#define PMIC_OC_STATUS_VCAMD_SHIFT 9
#define PMIC_OC_STATUS_VCAMIO_MASK 0x1
#define PMIC_OC_STATUS_VCAMIO_SHIFT 8
#define PMIC_OC_STATUS_VCAMAF_MASK 0x1
#define PMIC_OC_STATUS_VCAMAF_SHIFT 7
#define PMIC_OC_STATUS_VGP4_MASK 0x1
#define PMIC_OC_STATUS_VGP4_SHIFT 6
#define PMIC_OC_STATUS_VGP5_MASK 0x1
#define PMIC_OC_STATUS_VGP5_SHIFT 5
#define PMIC_OC_STATUS_VGP6_MASK 0x1
#define PMIC_OC_STATUS_VGP6_SHIFT 4
#define PMIC_OC_STATUS_VIBR_MASK 0x1
#define PMIC_OC_STATUS_VIBR_SHIFT 3
#define PMIC_OC_STATUS_VIO28_MASK 0x1
#define PMIC_OC_STATUS_VIO28_SHIFT 2
#define PMIC_OC_STATUS_VMC_MASK 0x1
#define PMIC_OC_STATUS_VMC_SHIFT 1
#define PMIC_OC_STATUS_VMCH_MASK 0x1
#define PMIC_OC_STATUS_VMCH_SHIFT 0
#define PMIC_HOMEKEY_DEB_MASK 0x1
#define PMIC_HOMEKEY_DEB_SHIFT 4
#define PMIC_SPK_OC_DET_D_R_MASK 0x1
#define PMIC_SPK_OC_DET_D_R_SHIFT 3
#define PMIC_SPK_OC_DET_D_L_MASK 0x1
#define PMIC_SPK_OC_DET_D_L_SHIFT 2
#define PMIC_SPK_OC_DET_AB_R_MASK 0x1
#define PMIC_SPK_OC_DET_AB_R_SHIFT 1
#define PMIC_SPK_OC_DET_AB_L_MASK 0x1
#define PMIC_SPK_OC_DET_AB_L_SHIFT 0
#define PMIC_RG_TOP_RSV_MASK 0xFFF
#define PMIC_RG_TOP_RSV_SHIFT 4
#define PMIC_RG_HDMI_PAD_IE_MASK 0x1
#define PMIC_RG_HDMI_PAD_IE_SHIFT 0
#define PMIC_TEST_OUT_L_MASK 0xFFFF
#define PMIC_TEST_OUT_L_SHIFT 0
#define PMIC_TEST_OUT_H_MASK 0xFFFF
#define PMIC_TEST_OUT_H_SHIFT 0
#define PMIC_RG_HDMI_TDSEL_MASK 0x1
#define PMIC_RG_HDMI_TDSEL_SHIFT 7
#define PMIC_RG_PMU_TDSEL_MASK 0x1
#define PMIC_RG_PMU_TDSEL_SHIFT 6
#define PMIC_RG_SPI_TDSEL_MASK 0x1
#define PMIC_RG_SPI_TDSEL_SHIFT 5
#define PMIC_RG_I2S_TDSEL_MASK 0x1
#define PMIC_RG_I2S_TDSEL_SHIFT 4
#define PMIC_RG_KP_TDSEL_MASK 0x1
#define PMIC_RG_KP_TDSEL_SHIFT 3
#define PMIC_RG_PWM_TDSEL_MASK 0x1
#define PMIC_RG_PWM_TDSEL_SHIFT 2
#define PMIC_RG_I2C_TDSEL_MASK 0x1
#define PMIC_RG_I2C_TDSEL_SHIFT 1
#define PMIC_RG_SIMAP_TDSEL_MASK 0x1
#define PMIC_RG_SIMAP_TDSEL_SHIFT 0
#define PMIC_RG_HDMI_RDSEL_MASK 0x1
#define PMIC_RG_HDMI_RDSEL_SHIFT 7
#define PMIC_RG_PMU_RDSEL_MASK 0x1
#define PMIC_RG_PMU_RDSEL_SHIFT 6
#define PMIC_RG_SPI_RDSEL_MASK 0x1
#define PMIC_RG_SPI_RDSEL_SHIFT 5
#define PMIC_RG_I2S_RDSEL_MASK 0x1
#define PMIC_RG_I2S_RDSEL_SHIFT 4
#define PMIC_RG_KP_RDSEL_MASK 0x1
#define PMIC_RG_KP_RDSEL_SHIFT 3
#define PMIC_RG_PWM_RDSEL_MASK 0x1
#define PMIC_RG_PWM_RDSEL_SHIFT 2
#define PMIC_RG_I2C_RDSEL_MASK 0x1
#define PMIC_RG_I2C_RDSEL_SHIFT 1
#define PMIC_RG_SIMAP_RDSEL_MASK 0x1
#define PMIC_RG_SIMAP_RDSEL_SHIFT 0
#define PMIC_RG_SMT15_MASK 0x1
#define PMIC_RG_SMT15_SHIFT 15
#define PMIC_RG_SMT14_MASK 0x1
#define PMIC_RG_SMT14_SHIFT 14
#define PMIC_RG_SMT13_MASK 0x1
#define PMIC_RG_SMT13_SHIFT 13
#define PMIC_RG_SMT12_MASK 0x1
#define PMIC_RG_SMT12_SHIFT 12
#define PMIC_RG_SMT11_MASK 0x1
#define PMIC_RG_SMT11_SHIFT 11
#define PMIC_RG_SMT10_MASK 0x1
#define PMIC_RG_SMT10_SHIFT 10
#define PMIC_RG_SMT9_MASK 0x1
#define PMIC_RG_SMT9_SHIFT 9
#define PMIC_RG_SMT8_MASK 0x1
#define PMIC_RG_SMT8_SHIFT 8
#define PMIC_RG_SMT7_MASK 0x1
#define PMIC_RG_SMT7_SHIFT 7
#define PMIC_RG_SMT6_MASK 0x1
#define PMIC_RG_SMT6_SHIFT 6
#define PMIC_RG_SMT5_MASK 0x1
#define PMIC_RG_SMT5_SHIFT 5
#define PMIC_RG_SMT4_MASK 0x1
#define PMIC_RG_SMT4_SHIFT 4
#define PMIC_RG_SMT3_MASK 0x1
#define PMIC_RG_SMT3_SHIFT 3
#define PMIC_RG_SMT2_MASK 0x1
#define PMIC_RG_SMT2_SHIFT 2
#define PMIC_RG_SMT1_MASK 0x1
#define PMIC_RG_SMT1_SHIFT 1
#define PMIC_RG_SMT0_MASK 0x1
#define PMIC_RG_SMT0_SHIFT 0
#define PMIC_RG_SMT31_MASK 0x1
#define PMIC_RG_SMT31_SHIFT 15
#define PMIC_RG_SMT30_MASK 0x1
#define PMIC_RG_SMT30_SHIFT 14
#define PMIC_RG_SMT29_MASK 0x1
#define PMIC_RG_SMT29_SHIFT 13
#define PMIC_RG_SMT28_MASK 0x1
#define PMIC_RG_SMT28_SHIFT 12
#define PMIC_RG_SMT27_MASK 0x1
#define PMIC_RG_SMT27_SHIFT 11
#define PMIC_RG_SMT26_MASK 0x1
#define PMIC_RG_SMT26_SHIFT 10
#define PMIC_RG_SMT25_MASK 0x1
#define PMIC_RG_SMT25_SHIFT 9
#define PMIC_RG_SMT24_MASK 0x1
#define PMIC_RG_SMT24_SHIFT 8
#define PMIC_RG_SMT23_MASK 0x1
#define PMIC_RG_SMT23_SHIFT 7
#define PMIC_RG_SMT22_MASK 0x1
#define PMIC_RG_SMT22_SHIFT 6
#define PMIC_RG_SMT21_MASK 0x1
#define PMIC_RG_SMT21_SHIFT 5
#define PMIC_RG_SMT20_MASK 0x1
#define PMIC_RG_SMT20_SHIFT 4
#define PMIC_RG_SMT19_MASK 0x1
#define PMIC_RG_SMT19_SHIFT 3
#define PMIC_RG_SMT18_MASK 0x1
#define PMIC_RG_SMT18_SHIFT 2
#define PMIC_RG_SMT17_MASK 0x1
#define PMIC_RG_SMT17_SHIFT 1
#define PMIC_RG_SMT16_MASK 0x1
#define PMIC_RG_SMT16_SHIFT 0
#define PMIC_RG_SMT47_MASK 0x1
#define PMIC_RG_SMT47_SHIFT 15
#define PMIC_RG_SMT46_MASK 0x1
#define PMIC_RG_SMT46_SHIFT 14
#define PMIC_RG_SMT45_MASK 0x1
#define PMIC_RG_SMT45_SHIFT 13
#define PMIC_RG_SMT44_MASK 0x1
#define PMIC_RG_SMT44_SHIFT 12
#define PMIC_RG_SMT43_MASK 0x1
#define PMIC_RG_SMT43_SHIFT 11
#define PMIC_RG_SMT42_MASK 0x1
#define PMIC_RG_SMT42_SHIFT 10
#define PMIC_RG_SMT41_MASK 0x1
#define PMIC_RG_SMT41_SHIFT 9
#define PMIC_RG_SMT40_MASK 0x1
#define PMIC_RG_SMT40_SHIFT 8
#define PMIC_RG_SMT39_MASK 0x1
#define PMIC_RG_SMT39_SHIFT 7
#define PMIC_RG_SMT38_MASK 0x1
#define PMIC_RG_SMT38_SHIFT 6
#define PMIC_RG_SMT37_MASK 0x1
#define PMIC_RG_SMT37_SHIFT 5
#define PMIC_RG_SMT36_MASK 0x1
#define PMIC_RG_SMT36_SHIFT 4
#define PMIC_RG_SMT35_MASK 0x1
#define PMIC_RG_SMT35_SHIFT 3
#define PMIC_RG_SMT34_MASK 0x1
#define PMIC_RG_SMT34_SHIFT 2
#define PMIC_RG_SMT33_MASK 0x1
#define PMIC_RG_SMT33_SHIFT 1
#define PMIC_RG_SMT32_MASK 0x1
#define PMIC_RG_SMT32_SHIFT 0
#define PMIC_RG_HOMEKEY_PDEN_MASK 0x1
#define PMIC_RG_HOMEKEY_PDEN_SHIFT 9
#define PMIC_RG_HOMEKEY_PUEN_MASK 0x1
#define PMIC_RG_HOMEKEY_PUEN_SHIFT 8
#define PMIC_RG_SMT50_MASK 0x1
#define PMIC_RG_SMT50_SHIFT 2
#define PMIC_RG_SMT49_MASK 0x1
#define PMIC_RG_SMT49_SHIFT 1
#define PMIC_RG_SMT48_MASK 0x1
#define PMIC_RG_SMT48_SHIFT 0
#define PMIC_RG_OCTL_SRCLKEN_PERI_MASK 0xF
#define PMIC_RG_OCTL_SRCLKEN_PERI_SHIFT 12
#define PMIC_RG_OCTL_SRCVOLTEN_MASK 0xF
#define PMIC_RG_OCTL_SRCVOLTEN_SHIFT 8
#define PMIC_RG_OCTL_INT_MASK 0xF
#define PMIC_RG_OCTL_INT_SHIFT 4
#define PMIC_RG_OCTL_HOMEKEY_MASK 0xF
#define PMIC_RG_OCTL_HOMEKEY_SHIFT 0
#define PMIC_RG_OCTL_SPI_CLK_MASK 0xF
#define PMIC_RG_OCTL_SPI_CLK_SHIFT 12
#define PMIC_RG_OCTL_WRAP_EVENT_MASK 0xF
#define PMIC_RG_OCTL_WRAP_EVENT_SHIFT 8
#define PMIC_RG_OCTL_RTC_32K1V8_MASK 0xF
#define PMIC_RG_OCTL_RTC_32K1V8_SHIFT 4
#define PMIC_RG_OCTL_SPI_MISO_MASK 0xF
#define PMIC_RG_OCTL_SPI_MISO_SHIFT 8
#define PMIC_RG_OCTL_SPI_MOSI_MASK 0xF
#define PMIC_RG_OCTL_SPI_MOSI_SHIFT 4
#define PMIC_RG_OCTL_SPI_CSN_MASK 0xF
#define PMIC_RG_OCTL_SPI_CSN_SHIFT 0
#define PMIC_RG_OCTL_AUD_MOSI_MASK 0xF
#define PMIC_RG_OCTL_AUD_MOSI_SHIFT 8
#define PMIC_RG_OCTL_AUD_MISO_MASK 0xF
#define PMIC_RG_OCTL_AUD_MISO_SHIFT 4
#define PMIC_RG_OCTL_AUD_ClK_MASK 0xF
#define PMIC_RG_OCTL_AUD_ClK_SHIFT 0
#define PMIC_RG_OCTL_COL2_MASK 0xF
#define PMIC_RG_OCTL_COL2_SHIFT 12
#define PMIC_RG_OCTL_COL1_MASK 0xF
#define PMIC_RG_OCTL_COL1_SHIFT 8
#define PMIC_RG_OCTL_COL0_MASK 0xF
#define PMIC_RG_OCTL_COL0_SHIFT 4
#define PMIC_RG_OCTL_COL6_MASK 0xF
#define PMIC_RG_OCTL_COL6_SHIFT 12
#define PMIC_RG_OCTL_COL5_MASK 0xF
#define PMIC_RG_OCTL_COL5_SHIFT 8
#define PMIC_RG_OCTL_COL4_MASK 0xF
#define PMIC_RG_OCTL_COL4_SHIFT 4
#define PMIC_RG_OCTL_COL3_MASK 0xF
#define PMIC_RG_OCTL_COL3_SHIFT 0
#define PMIC_RG_OCTL_ROW2_MASK 0xF
#define PMIC_RG_OCTL_ROW2_SHIFT 12
#define PMIC_RG_OCTL_ROW1_MASK 0xF
#define PMIC_RG_OCTL_ROW1_SHIFT 8
#define PMIC_RG_OCTL_ROW0_MASK 0xF
#define PMIC_RG_OCTL_ROW0_SHIFT 4
#define PMIC_RG_OCTL_COL7_MASK 0xF
#define PMIC_RG_OCTL_COL7_SHIFT 0
#define PMIC_RG_OCTL_ROW6_MASK 0xF
#define PMIC_RG_OCTL_ROW6_SHIFT 12
#define PMIC_RG_OCTL_ROW5_MASK 0xF
#define PMIC_RG_OCTL_ROW5_SHIFT 8
#define PMIC_RG_OCTL_ROW4_MASK 0xF
#define PMIC_RG_OCTL_ROW4_SHIFT 4
#define PMIC_RG_OCTL_ROW3_MASK 0xF
#define PMIC_RG_OCTL_ROW3_SHIFT 0
#define PMIC_RG_OCTL_PWM_MASK 0xF
#define PMIC_RG_OCTL_PWM_SHIFT 12
#define PMIC_RG_OCTL_VMSEL2_MASK 0xF
#define PMIC_RG_OCTL_VMSEL2_SHIFT 8
#define PMIC_RG_OCTL_VMSEL1_MASK 0xF
#define PMIC_RG_OCTL_VMSEL1_SHIFT 4
#define PMIC_RG_OCTL_ROW7_MASK 0xF
#define PMIC_RG_OCTL_ROW7_SHIFT 0
#define PMIC_RG_OCTL_SDA1_MASK 0xF
#define PMIC_RG_OCTL_SDA1_SHIFT 12
#define PMIC_RG_OCTL_SCL1_MASK 0xF
#define PMIC_RG_OCTL_SCL1_SHIFT 8
#define PMIC_RG_OCTL_SDA0_MASK 0xF
#define PMIC_RG_OCTL_SDA0_SHIFT 4
#define PMIC_RG_OCTL_SCL0_MASK 0xF
#define PMIC_RG_OCTL_SCL0_SHIFT 0
#define PMIC_RG_OCTL_SDA2_MASK 0xF
#define PMIC_RG_OCTL_SDA2_SHIFT 4
#define PMIC_RG_OCTL_SCL2_MASK 0xF
#define PMIC_RG_OCTL_SCL2_SHIFT 0
#define PMIC_RG_OCTL_CEC_MASK 0xF
#define PMIC_RG_OCTL_CEC_SHIFT 12
#define PMIC_RG_OCTL_HTPLG_MASK 0xF
#define PMIC_RG_OCTL_HTPLG_SHIFT 8
#define PMIC_RG_OCTL_HDMISD_MASK 0xF
#define PMIC_RG_OCTL_HDMISD_SHIFT 4
#define PMIC_RG_OCTL_HDMISCK_MASK 0xF
#define PMIC_RG_OCTL_HDMISCK_SHIFT 0
#define PMIC_RG_OCTL_SIMLS2_SRST_MASK 0xF
#define PMIC_RG_OCTL_SIMLS2_SRST_SHIFT 4
#define PMIC_RG_OCTL_SIMLS2_SCLK_MASK 0xF
#define PMIC_RG_OCTL_SIMLS2_SCLK_SHIFT 0
#define PMIC_RG_INT_EN_OV_MASK 0x1
#define PMIC_RG_INT_EN_OV_SHIFT 15
#define PMIC_RG_INT_EN_CHRDET_MASK 0x1
#define PMIC_RG_INT_EN_CHRDET_SHIFT 14
#define PMIC_RG_INT_EN_BVALID_DET_MASK 0x1
#define PMIC_RG_INT_EN_BVALID_DET_SHIFT 13
#define PMIC_RG_INT_EN_VBATON_UNDET_MASK 0x1
#define PMIC_RG_INT_EN_VBATON_UNDET_SHIFT 12
#define PMIC_RG_INT_EN_THR_H_MASK 0x1
#define PMIC_RG_INT_EN_THR_H_SHIFT 11
#define PMIC_RG_INT_EN_THR_L_MASK 0x1
#define PMIC_RG_INT_EN_THR_L_SHIFT 10
#define PMIC_RG_INT_EN_PWRKEY_MASK 0x1
#define PMIC_RG_INT_EN_PWRKEY_SHIFT 9
#define PMIC_RG_INT_EN_WATCHDOG_MASK 0x1
#define PMIC_RG_INT_EN_WATCHDOG_SHIFT 8
#define PMIC_RG_INT_EN_FG_BAT_H_MASK 0x1
#define PMIC_RG_INT_EN_FG_BAT_H_SHIFT 7
#define PMIC_RG_INT_EN_FG_BAT_L_MASK 0x1
#define PMIC_RG_INT_EN_FG_BAT_L_SHIFT 6
#define PMIC_RG_INT_EN_BAT_H_MASK 0x1
#define PMIC_RG_INT_EN_BAT_H_SHIFT 5
#define PMIC_RG_INT_EN_BAT_L_MASK 0x1
#define PMIC_RG_INT_EN_BAT_L_SHIFT 4
#define PMIC_RG_INT_EN_SPKR_MASK 0x1
#define PMIC_RG_INT_EN_SPKR_SHIFT 3
#define PMIC_RG_INT_EN_SPKL_MASK 0x1
#define PMIC_RG_INT_EN_SPKL_SHIFT 2
#define PMIC_RG_INT_EN_SPKR_AB_MASK 0x1
#define PMIC_RG_INT_EN_SPKR_AB_SHIFT 1
#define PMIC_RG_INT_EN_SPKL_AB_MASK 0x1
#define PMIC_RG_INT_EN_SPKL_AB_SHIFT 0
#define PMIC_RG_INT_EN_VDRM_MASK 0x1
#define PMIC_RG_INT_EN_VDRM_SHIFT 15
#define PMIC_RG_INT_EN_VSRMCA7_MASK 0x1
#define PMIC_RG_INT_EN_VSRMCA7_SHIFT 14
#define PMIC_RG_INT_EN_VPCA7_MASK 0x1
#define PMIC_RG_INT_EN_VPCA7_SHIFT 13
#define PMIC_RG_INT_EN_VIO18_MASK 0x1
#define PMIC_RG_INT_EN_VIO18_SHIFT 12
#define PMIC_RG_INT_EN_VGPU_MASK 0x1
#define PMIC_RG_INT_EN_VGPU_SHIFT 11
#define PMIC_RG_INT_EN_VCORE_MASK 0x1
#define PMIC_RG_INT_EN_VCORE_SHIFT 10
#define PMIC_RG_INT_EN_VSRMCA15_MASK 0x1
#define PMIC_RG_INT_EN_VSRMCA15_SHIFT 9
#define PMIC_RG_INT_EN_VCA15_MASK 0x1
#define PMIC_RG_INT_EN_VCA15_SHIFT 8
#define PMIC_RG_INT_EN_HDMI_CEC_MASK 0x1
#define PMIC_RG_INT_EN_HDMI_CEC_SHIFT 7
#define PMIC_RG_INT_EN_HDMI_SIFM_MASK 0x1
#define PMIC_RG_INT_EN_HDMI_SIFM_SHIFT 6
#define PMIC_RG_INT_EN_PWRKEY_RSTB_MASK 0x1
#define PMIC_RG_INT_EN_PWRKEY_RSTB_SHIFT 5
#define PMIC_RG_INT_EN_RTC_MASK 0x1
#define PMIC_RG_INT_EN_RTC_SHIFT 4
#define PMIC_RG_INT_EN_AUDIO_MASK 0x1
#define PMIC_RG_INT_EN_AUDIO_SHIFT 3
#define PMIC_RG_INT_EN_ACCDET_MASK 0x1
#define PMIC_RG_INT_EN_ACCDET_SHIFT 2
#define PMIC_RG_INT_EN_HOMEKEY_MASK 0x1
#define PMIC_RG_INT_EN_HOMEKEY_SHIFT 1
#define PMIC_RG_INT_EN_LDO_MASK 0x1
#define PMIC_RG_INT_EN_LDO_SHIFT 0
#define PMIC_RG_INT_STATUS_OV_MASK 0x1
#define PMIC_RG_INT_STATUS_OV_SHIFT 15
#define PMIC_RG_INT_STATUS_CHRDET_MASK 0x1
#define PMIC_RG_INT_STATUS_CHRDET_SHIFT 14
#define PMIC_RG_INT_STATUS_BVALID_DET_MASK 0x1
#define PMIC_RG_INT_STATUS_BVALID_DET_SHIFT 13
#define PMIC_RG_INT_STATUS_VBATON_UNDET_MASK 0x1
#define PMIC_RG_INT_STATUS_VBATON_UNDET_SHIFT 12
#define PMIC_RG_INT_STATUS_THR_H_MASK 0x1
#define PMIC_RG_INT_STATUS_THR_H_SHIFT 11
#define PMIC_RG_INT_STATUS_THR_L_MASK 0x1
#define PMIC_RG_INT_STATUS_THR_L_SHIFT 10
#define PMIC_RG_INT_STATUS_PWRKEY_MASK 0x1
#define PMIC_RG_INT_STATUS_PWRKEY_SHIFT 9
#define PMIC_RG_INT_STATUS_WATCHDOG_MASK 0x1
#define PMIC_RG_INT_STATUS_WATCHDOG_SHIFT 8
#define PMIC_RG_INT_STATUS_FG_BAT_H_MASK 0x1
#define PMIC_RG_INT_STATUS_FG_BAT_H_SHIFT 7
#define PMIC_RG_INT_STATUS_FG_BAT_L_MASK 0x1
#define PMIC_RG_INT_STATUS_FG_BAT_L_SHIFT 6
#define PMIC_RG_INT_STATUS_BAT_H_MASK 0x1
#define PMIC_RG_INT_STATUS_BAT_H_SHIFT 5
#define PMIC_RG_INT_STATUS_BAT_L_MASK 0x1
#define PMIC_RG_INT_STATUS_BAT_L_SHIFT 4
#define PMIC_RG_INT_STATUS_SPKR_MASK 0x1
#define PMIC_RG_INT_STATUS_SPKR_SHIFT 3
#define PMIC_RG_INT_STATUS_SPKL_MASK 0x1
#define PMIC_RG_INT_STATUS_SPKL_SHIFT 2
#define PMIC_RG_INT_STATUS_SPKR_AB_MASK 0x1
#define PMIC_RG_INT_STATUS_SPKR_AB_SHIFT 1
#define PMIC_RG_INT_STATUS_SPKL_AB_MASK 0x1
#define PMIC_RG_INT_STATUS_SPKL_AB_SHIFT 0
#define PMIC_RG_INT_STATUS_VDRM_MASK 0x1
#define PMIC_RG_INT_STATUS_VDRM_SHIFT 15
#define PMIC_RG_INT_STATUS_VSRMCA7_MASK 0x1
#define PMIC_RG_INT_STATUS_VSRMCA7_SHIFT 14
#define PMIC_RG_INT_STATUS_VPCA7_MASK 0x1
#define PMIC_RG_INT_STATUS_VPCA7_SHIFT 13
#define PMIC_RG_INT_STATUS_VIO18_MASK 0x1
#define PMIC_RG_INT_STATUS_VIO18_SHIFT 12
#define PMIC_RG_INT_STATUS_VGPU_MASK 0x1
#define PMIC_RG_INT_STATUS_VGPU_SHIFT 11
#define PMIC_RG_INT_STATUS_VCORE_MASK 0x1
#define PMIC_RG_INT_STATUS_VCORE_SHIFT 10
#define PMIC_RG_INT_STATUS_VSRMCA15_MASK 0x1
#define PMIC_RG_INT_STATUS_VSRMCA15_SHIFT 9
#define PMIC_RG_INT_STATUS_VCA15_MASK 0x1
#define PMIC_RG_INT_STATUS_VCA15_SHIFT 8
#define PMIC_RG_INT_STATUS_HDMI_CEC_MASK 0x1
#define PMIC_RG_INT_STATUS_HDMI_CEC_SHIFT 7
#define PMIC_RG_INT_STATUS_HDMI_SIFM_MASK 0x1
#define PMIC_RG_INT_STATUS_HDMI_SIFM_SHIFT 6
#define PMIC_RG_INT_STATUS_PWRKEY_RSTB_MASK 0x1
#define PMIC_RG_INT_STATUS_PWRKEY_RSTB_SHIFT 5
#define PMIC_RG_INT_STATUS_RTC_MASK 0x1
#define PMIC_RG_INT_STATUS_RTC_SHIFT 4
#define PMIC_RG_INT_STATUS_AUDIO_MASK 0x1
#define PMIC_RG_INT_STATUS_AUDIO_SHIFT 3
#define PMIC_RG_INT_STATUS_ACCDET_MASK 0x1
#define PMIC_RG_INT_STATUS_ACCDET_SHIFT 2
#define PMIC_RG_INT_STATUS_HOMEKEY_MASK 0x1
#define PMIC_RG_INT_STATUS_HOMEKEY_SHIFT 1
#define PMIC_RG_INT_STATUS_LDO_MASK 0x1
#define PMIC_RG_INT_STATUS_LDO_SHIFT 0
#define PMIC_FQMTR_EN_MASK 0x1
#define PMIC_FQMTR_EN_SHIFT 15
#define PMIC_FQMTR_RST_MASK 0x1
#define PMIC_FQMTR_RST_SHIFT 14
#define PMIC_FQMTR_BUSY_MASK 0x1
#define PMIC_FQMTR_BUSY_SHIFT 3
#define PMIC_FQMTR_TCKSEL_MASK 0x7
#define PMIC_FQMTR_TCKSEL_SHIFT 0
#define PMIC_FQMTR_WINSET_MASK 0xFFFF
#define PMIC_FQMTR_WINSET_SHIFT 0
#define PMIC_FQMTR_DATA_MASK 0xFFFF
#define PMIC_FQMTR_DATA_SHIFT 0
#define PMIC_RG_EFUSE_ADDR_MASK 0x3F
#define PMIC_RG_EFUSE_ADDR_SHIFT 0
#define PMIC_RG_EFUSE_PROG_MASK 0x1F
#define PMIC_RG_EFUSE_PROG_SHIFT 0
#define PMIC_RG_EFUSE_EN_MASK 0x1
#define PMIC_RG_EFUSE_EN_SHIFT 0
#define PMIC_RG_EFUSE_PKEY_MASK 0xFFFF
#define PMIC_RG_EFUSE_PKEY_SHIFT 0
#define PMIC_RG_EFUSE_RD_TRIG_MASK 0x1
#define PMIC_RG_EFUSE_RD_TRIG_SHIFT 0
#define PMIC_RG_RD_RDY_BYPASS_MASK 0x1
#define PMIC_RG_RD_RDY_BYPASS_SHIFT 4
#define PMIC_RG_SKIP_EFUSE_OUT_MASK 0x1
#define PMIC_RG_SKIP_EFUSE_OUT_SHIFT 2
#define PMIC_RG_EFUSE_PROG_SRC_MASK 0x1
#define PMIC_RG_EFUSE_PROG_SRC_SHIFT 0
#define PMIC_RG_EFUSE_BUSY_MASK 0x1
#define PMIC_RG_EFUSE_BUSY_SHIFT 2
#define PMIC_RG_EFUSE_RD_ACK_MASK 0x1
#define PMIC_RG_EFUSE_RD_ACK_SHIFT 0
#define PMIC_RG_EFUSE_VAL_0_15_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_0_15_SHIFT 0
#define PMIC_RG_EFUSE_VAL_16_31_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_16_31_SHIFT 0
#define PMIC_RG_EFUSE_VAL_32_47_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_32_47_SHIFT 0
#define PMIC_RG_EFUSE_VAL_48_63_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_48_63_SHIFT 0
#define PMIC_RG_EFUSE_VAL_64_79_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_64_79_SHIFT 0
#define PMIC_RG_EFUSE_VAL_80_95_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_80_95_SHIFT 0
#define PMIC_RG_EFUSE_VAL_96_111_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_96_111_SHIFT 0
#define PMIC_RG_EFUSE_VAL_112_127_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_112_127_SHIFT 0
#define PMIC_RG_EFUSE_VAL_128_143_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_128_143_SHIFT 0
#define PMIC_RG_EFUSE_VAL_144_159_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_144_159_SHIFT 0
#define PMIC_RG_EFUSE_VAL_160_175_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_160_175_SHIFT 0
#define PMIC_RG_EFUSE_VAL_176_191_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_176_191_SHIFT 0
#define PMIC_RG_EFUSE_VAL_192_207_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_192_207_SHIFT 0
#define PMIC_RG_EFUSE_VAL_208_223_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_208_223_SHIFT 0
#define PMIC_RG_EFUSE_VAL_224_239_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_224_239_SHIFT 0
#define PMIC_RG_EFUSE_VAL_240_255_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_240_255_SHIFT 0
#define PMIC_RG_EFUSE_VAL_256_271_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_256_271_SHIFT 0
#define PMIC_RG_EFUSE_VAL_272_287_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_272_287_SHIFT 0
#define PMIC_RG_EFUSE_VAL_288_303_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_288_303_SHIFT 0
#define PMIC_RG_EFUSE_VAL_304_319_MASK 0xFFFF
#define PMIC_RG_EFUSE_VAL_304_319_SHIFT 0
#define PMIC_RG_EFUSE_DOUT_0_15_MASK 0xFFFF
#define PMIC_RG_EFUSE_DOUT_0_15_SHIFT 0
#define PMIC_RG_EFUSE_DOUT_16_31_MASK 0xFFFF
#define PMIC_RG_EFUSE_DOUT_16_31_SHIFT 0
#define PMIC_RG_EFUSE_DOUT_32_47_MASK 0xFFFF
#define PMIC_RG_EFUSE_DOUT_32_47_SHIFT 0
#define PMIC_RG_EFUSE_DOUT_48_63_MASK 0xFFFF
#define PMIC_RG_EFUSE_DOUT_48_63_SHIFT 0
#define PMIC_SPI_CON_MASK 0x1
#define PMIC_SPI_CON_SHIFT 0
#define PMIC_RG_AUXADC_DIV_CK_PDN_MASK 0x1
#define PMIC_RG_AUXADC_DIV_CK_PDN_SHIFT 1
#define PMIC_RG_RTC_75K_DIV4_CK_PDN_MASK 0x1
#define PMIC_RG_RTC_75K_DIV4_CK_PDN_SHIFT 0
#define PMIC_RG_WRAP_EVENT_EN_MASK 0x1
#define PMIC_RG_WRAP_EVENT_EN_SHIFT 4
#define PMIC_RG_WRAP_EN_SEL_MASK 0x1
#define PMIC_RG_WRAP_EN_SEL_SHIFT 3
#define PMIC_RG_DCXO_SEL_MASK 0x1
#define PMIC_RG_DCXO_SEL_SHIFT 2
#define PMIC_RG_EINT_CK_SEL_MASK 0x1
#define PMIC_RG_EINT_CK_SEL_SHIFT 1
#define PMIC_RG_AUD_CK_SEL_MASK 0x1
#define PMIC_RG_AUD_CK_SEL_SHIFT 0
#define PMIC_EFUSE_DOUT_64_79_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_64_79_SHIFT 0
#define PMIC_EFUSE_DOUT_80_95_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_80_95_SHIFT 0
#define PMIC_EFUSE_DOUT_96_111_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_96_111_SHIFT 0
#define PMIC_EFUSE_DOUT_112_127_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_112_127_SHIFT 0
#define PMIC_EFUSE_DOUT_128_143_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_128_143_SHIFT 0
#define PMIC_EFUSE_DOUT_144_159_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_144_159_SHIFT 0
#define PMIC_EFUSE_DOUT_160_175_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_160_175_SHIFT 0
#define PMIC_EFUSE_DOUT_176_191_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_176_191_SHIFT 0
#define PMIC_EFUSE_DOUT_192_207_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_192_207_SHIFT 0
#define PMIC_EFUSE_DOUT_208_223_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_208_223_SHIFT 0
#define PMIC_EFUSE_DOUT_224_239_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_224_239_SHIFT 0
#define PMIC_EFUSE_DOUT_240_255_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_240_255_SHIFT 0
#define PMIC_EFUSE_DOUT_256_271_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_256_271_SHIFT 0
#define PMIC_EFUSE_DOUT_272_287_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_272_287_SHIFT 0
#define PMIC_EFUSE_DOUT_288_303_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_288_303_SHIFT 0
#define PMIC_EFUSE_DOUT_304_319_MASK 0xFFFF
#define PMIC_EFUSE_DOUT_304_319_SHIFT 0
#define PMIC_RG_SMPS_TESTMODE_B_MASK 0x1FF
#define PMIC_RG_SMPS_TESTMODE_B_SHIFT 0
#define PMIC_QI_VSRMCA7_DIG_MON_MASK 0xF
#define PMIC_QI_VSRMCA7_DIG_MON_SHIFT 12
#define PMIC_QI_VPCA7_DIG_MON_MASK 0xF
#define PMIC_QI_VPCA7_DIG_MON_SHIFT 8
#define PMIC_QI_VSRMCA15_DIG_MON_MASK 0xF
#define PMIC_QI_VSRMCA15_DIG_MON_SHIFT 4
#define PMIC_QI_VCA15_DIG_MON_MASK 0xF
#define PMIC_QI_VCA15_DIG_MON_SHIFT 0
#define PMIC_QI_VCORE_DIG_MON_MASK 0xF
#define PMIC_QI_VCORE_DIG_MON_SHIFT 8
#define PMIC_QI_VDRM_DIG_MON_MASK 0xF
#define PMIC_QI_VDRM_DIG_MON_SHIFT 4
#define PMIC_QI_VGPU_DIG_MON_MASK 0xF
#define PMIC_QI_VGPU_DIG_MON_SHIFT 0
#define PMIC_BUCK_RSV_MASK 0x1FFF
#define PMIC_BUCK_RSV_SHIFT 0
#define PMIC_RG_VPCA7_TRIMH_MASK 0x7
#define PMIC_RG_VPCA7_TRIMH_SHIFT 12
#define PMIC_RG_VPCA7_TRIML_MASK 0x7
#define PMIC_RG_VPCA7_TRIML_SHIFT 8
#define PMIC_RG_VCA15_TRIMH_MASK 0x7
#define PMIC_RG_VCA15_TRIMH_SHIFT 4
#define PMIC_RG_VCA15_TRIML_MASK 0x7
#define PMIC_RG_VCA15_TRIML_SHIFT 0
#define PMIC_RG_VSRMCA7_TRIMH_MASK 0x7
#define PMIC_RG_VSRMCA7_TRIMH_SHIFT 12
#define PMIC_RG_VSRMCA7_TRIML_MASK 0x7
#define PMIC_RG_VSRMCA7_TRIML_SHIFT 8
#define PMIC_RG_VSRMCA15_TRIMH_MASK 0x7
#define PMIC_RG_VSRMCA15_TRIMH_SHIFT 4
#define PMIC_RG_VSRMCA15_TRIML_MASK 0x7
#define PMIC_RG_VSRMCA15_TRIML_SHIFT 0
#define PMIC_RG_VCORE_TRIMH_MASK 0x7
#define PMIC_RG_VCORE_TRIMH_SHIFT 12
#define PMIC_RG_VCORE_TRIML_MASK 0x7
#define PMIC_RG_VCORE_TRIML_SHIFT 8
#define PMIC_RG_VGPU_TRIMH_MASK 0x7
#define PMIC_RG_VGPU_TRIMH_SHIFT 4
#define PMIC_RG_VGPU_TRIML_MASK 0x7
#define PMIC_RG_VGPU_TRIML_SHIFT 0
#define PMIC_RG_VDRM_TRIMH_MASK 0x7
#define PMIC_RG_VDRM_TRIMH_SHIFT 4
#define PMIC_RG_VDRM_TRIML_MASK 0x7
#define PMIC_RG_VDRM_TRIML_SHIFT 0
#define PMIC_QI_VCORE_VSLEEP_MASK 0x3
#define PMIC_QI_VCORE_VSLEEP_SHIFT 10
#define PMIC_QI_VGPU_VSLEEP_MASK 0x3
#define PMIC_QI_VGPU_VSLEEP_SHIFT 8
#define PMIC_QI_VSRMCA7_VSLEEP_MASK 0x3
#define PMIC_QI_VSRMCA7_VSLEEP_SHIFT 6
#define PMIC_QI_VSRMCA15_VSLEEP_MASK 0x3
#define PMIC_QI_VSRMCA15_VSLEEP_SHIFT 4
#define PMIC_QI_VPCA7_VSLEEP_MASK 0x3
#define PMIC_QI_VPCA7_VSLEEP_SHIFT 2
#define PMIC_QI_VCA15_VSLEEP_MASK 0x3
#define PMIC_QI_VCA15_VSLEEP_SHIFT 0
#define PMIC_QI_VDRM_VSLEEP_MASK 0x3
#define PMIC_QI_VDRM_VSLEEP_SHIFT 0
#define PMIC_RG_VCA15_ZXOS_TRIM2_MASK 0x3F
#define PMIC_RG_VCA15_ZXOS_TRIM2_SHIFT 8
#define PMIC_RG_VCA15_ZXOS_TRIM1_MASK 0x3F
#define PMIC_RG_VCA15_ZXOS_TRIM1_SHIFT 0
#define PMIC_RG_VCA15_CSL2_MASK 0x3
#define PMIC_RG_VCA15_CSL2_SHIFT 12
#define PMIC_RG_VCA15_CSL1_MASK 0x3
#define PMIC_RG_VCA15_CSL1_SHIFT 10
#define PMIC_RG_VCA15_CSR2_MASK 0x3
#define PMIC_RG_VCA15_CSR2_SHIFT 8
#define PMIC_RG_VCA15_CSR1_MASK 0x3
#define PMIC_RG_VCA15_CSR1_SHIFT 6
#define PMIC_RG_VCA15_CC_MASK 0x7
#define PMIC_RG_VCA15_CC_SHIFT 3
#define PMIC_RG_VCA15_RZSEL_MASK 0x7
#define PMIC_RG_VCA15_RZSEL_SHIFT 0
#define PMIC_RG_VCA15_NDIS_EN_MASK 0x1
#define PMIC_RG_VCA15_NDIS_EN_SHIFT 12
#define PMIC_RG_VCA15_MODESET_MASK 0x1
#define PMIC_RG_VCA15_MODESET_SHIFT 11
#define PMIC_RG_VCA15_ACGB_EN_MASK 0x1
#define PMIC_RG_VCA15_ACGB_EN_SHIFT 10
#define PMIC_RG_VCA15_SLP2_MASK 0x3
#define PMIC_RG_VCA15_SLP2_SHIFT 6
#define PMIC_RG_VCA15_SLP1_MASK 0x3
#define PMIC_RG_VCA15_SLP1_SHIFT 4
#define PMIC_RG_VCA15_ZX_OS2_MASK 0x3
#define PMIC_RG_VCA15_ZX_OS2_SHIFT 2
#define PMIC_RG_VCA15_ZX_OS1_MASK 0x3
#define PMIC_RG_VCA15_ZX_OS1_SHIFT 0
#define PMIC_RG_VCA15_CSM2_MASK 0x7
#define PMIC_RG_VCA15_CSM2_SHIFT 4
#define PMIC_RG_VCA15_CSM1_MASK 0x7
#define PMIC_RG_VCA15_CSM1_SHIFT 0
#define PMIC_RG_VCA15_RSV1_MASK 0xFF
#define PMIC_RG_VCA15_RSV1_SHIFT 0
#define PMIC_VCA15_TRACK_ON_CTRL_MASK 0x1
#define PMIC_VCA15_TRACK_ON_CTRL_SHIFT 4
#define PMIC_VCA15_BURST_CTRL_MASK 0x1
#define PMIC_VCA15_BURST_CTRL_SHIFT 3
#define PMIC_VCA15_DLC_CTRL_MASK 0x1
#define PMIC_VCA15_DLC_CTRL_SHIFT 2
#define PMIC_VCA15_VOSEL_CTRL_MASK 0x1
#define PMIC_VCA15_VOSEL_CTRL_SHIFT 1
#define PMIC_VCA15_EN_CTRL_MASK 0x1
#define PMIC_VCA15_EN_CTRL_SHIFT 0
#define PMIC_VCA15_BURST_SEL_MASK 0x3
#define PMIC_VCA15_BURST_SEL_SHIFT 12
#define PMIC_VCA15_DLC_SEL_MASK 0x3
#define PMIC_VCA15_DLC_SEL_SHIFT 8
#define PMIC_VCA15_VOSEL_SEL_MASK 0x3
#define PMIC_VCA15_VOSEL_SEL_SHIFT 4
#define PMIC_VCA15_EN_SEL_MASK 0x3
#define PMIC_VCA15_EN_SEL_SHIFT 0
#define PMIC_QI_VCA15_OC_STATUS_MASK 0x1
#define PMIC_QI_VCA15_OC_STATUS_SHIFT 15
#define PMIC_QI_VCA15_MODE_MASK 0x1
#define PMIC_QI_VCA15_MODE_SHIFT 14
#define PMIC_QI_VCA15_EN_MASK 0x1
#define PMIC_QI_VCA15_EN_SHIFT 13
#define PMIC_QI_VCA15_STB_MASK 0x1
#define PMIC_QI_VCA15_STB_SHIFT 12
#define PMIC_VCA15_STBTD_MASK 0x3
#define PMIC_VCA15_STBTD_SHIFT 4
#define PMIC_VCA15_EN_MASK 0x1
#define PMIC_VCA15_EN_SHIFT 0
#define PMIC_VCA15_SFCHG_REN_MASK 0x1
#define PMIC_VCA15_SFCHG_REN_SHIFT 15
#define PMIC_VCA15_SFCHG_RRATE_MASK 0x7F
#define PMIC_VCA15_SFCHG_RRATE_SHIFT 8
#define PMIC_VCA15_SFCHG_FEN_MASK 0x1
#define PMIC_VCA15_SFCHG_FEN_SHIFT 7
#define PMIC_VCA15_SFCHG_FRATE_MASK 0x7F
#define PMIC_VCA15_SFCHG_FRATE_SHIFT 0
#define PMIC_VCA15_VOSEL_MASK 0x7F
#define PMIC_VCA15_VOSEL_SHIFT 0
#define PMIC_VCA15_VOSEL_ON_MASK 0x7F
#define PMIC_VCA15_VOSEL_ON_SHIFT 0
#define PMIC_VCA15_VOSEL_SLEEP_MASK 0x7F
#define PMIC_VCA15_VOSEL_SLEEP_SHIFT 0
#define PMIC_NI_VCA15_VOSEL_MASK 0x7F
#define PMIC_NI_VCA15_VOSEL_SHIFT 0
#define PMIC_QI_VCA15_BURST_MASK 0x3
#define PMIC_QI_VCA15_BURST_SHIFT 12
#define PMIC_VCA15_BURST_SLEEP_MASK 0x3
#define PMIC_VCA15_BURST_SLEEP_SHIFT 8
#define PMIC_VCA15_BURST_ON_MASK 0x3
#define PMIC_VCA15_BURST_ON_SHIFT 4
#define PMIC_VCA15_BURST_MASK 0x3
#define PMIC_VCA15_BURST_SHIFT 0
#define PMIC_QI_VCA15_DLC_MASK 0x3
#define PMIC_QI_VCA15_DLC_SHIFT 12
#define PMIC_VCA15_DLC_SLEEP_MASK 0x3
#define PMIC_VCA15_DLC_SLEEP_SHIFT 8
#define PMIC_VCA15_DLC_ON_MASK 0x3
#define PMIC_VCA15_DLC_ON_SHIFT 4
#define PMIC_VCA15_DLC_MASK 0x3
#define PMIC_VCA15_DLC_SHIFT 0
#define PMIC_QI_VCA15_DLC_N_MASK 0x3
#define PMIC_QI_VCA15_DLC_N_SHIFT 12
#define PMIC_VCA15_DLC_N_SLEEP_MASK 0x3
#define PMIC_VCA15_DLC_N_SLEEP_SHIFT 8
#define PMIC_VCA15_DLC_N_ON_MASK 0x3
#define PMIC_VCA15_DLC_N_ON_SHIFT 4
#define PMIC_VCA15_DLC_N_MASK 0x3
#define PMIC_VCA15_DLC_N_SHIFT 0
#define PMIC_QI_VCA15_BURSTH_MASK 0x3
#define PMIC_QI_VCA15_BURSTH_SHIFT 12
#define PMIC_QI_VCA15_BURSTL_MASK 0x3
#define PMIC_QI_VCA15_BURSTL_SHIFT 12
#define PMIC_NI_VCA15_VSLEEP_SEL_MASK 0x1
#define PMIC_NI_VCA15_VSLEEP_SEL_SHIFT 15
#define PMIC_NI_VCA15_R2R_PDN_MASK 0x1
#define PMIC_NI_VCA15_R2R_PDN_SHIFT 14
#define PMIC_VCA15_VSLEEP_SEL_MASK 0x1
#define PMIC_VCA15_VSLEEP_SEL_SHIFT 11
#define PMIC_VCA15_R2R_PDN_MASK 0x1
#define PMIC_VCA15_R2R_PDN_SHIFT 10
#define PMIC_VCA15_VSLEEP_EN_MASK 0x1
#define PMIC_VCA15_VSLEEP_EN_SHIFT 8
#define PMIC_NI_VCA15_VOSEL_TRANS_MASK 0x1
#define PMIC_NI_VCA15_VOSEL_TRANS_SHIFT 7
#define PMIC_VCA15_VOSEL_TRANS_ONCE_MASK 0x1
#define PMIC_VCA15_VOSEL_TRANS_ONCE_SHIFT 6
#define PMIC_VCA15_VOSEL_TRANS_EN_MASK 0x3
#define PMIC_VCA15_VOSEL_TRANS_EN_SHIFT 4
#define PMIC_VCA15_TRANSTD_MASK 0x3
#define PMIC_VCA15_TRANSTD_SHIFT 0
#define PMIC_RG_VSRMCA15_ZXOS_TRIM_MASK 0x3F
#define PMIC_RG_VSRMCA15_ZXOS_TRIM_SHIFT 0
#define PMIC_RG_VSRMCA15_ZX_OS_MASK 0x3
#define PMIC_RG_VSRMCA15_ZX_OS_SHIFT 14
#define PMIC_RG_VSRMCA15_CSL_MASK 0x3
#define PMIC_RG_VSRMCA15_CSL_SHIFT 8
#define PMIC_RG_VSRMCA15_CSR_MASK 0x3
#define PMIC_RG_VSRMCA15_CSR_SHIFT 6
#define PMIC_RG_VSRMCA15_CC_MASK 0x3
#define PMIC_RG_VSRMCA15_CC_SHIFT 4
#define PMIC_RG_VSRMCA15_RZSEL_MASK 0x3
#define PMIC_RG_VSRMCA15_RZSEL_SHIFT 0
#define PMIC_RG_VSRMCA15_NDIS_EN_MASK 0x1
#define PMIC_RG_VSRMCA15_NDIS_EN_SHIFT 9
#define PMIC_RG_VSRMCA15_MODESET_MASK 0x1
#define PMIC_RG_VSRMCA15_MODESET_SHIFT 8
#define PMIC_RG_VSRMCA15_CSM_MASK 0x7
#define PMIC_RG_VSRMCA15_CSM_SHIFT 4
#define PMIC_RG_VSRMCA15_SMRIP_EN_MASK 0x1
#define PMIC_RG_VSRMCA15_SMRIP_EN_SHIFT 0
#define PMIC_QI_VSRMCA15_SLPO_OUT_MASK 0xF
#define PMIC_QI_VSRMCA15_SLPO_OUT_SHIFT 12
#define PMIC_QI_VSRMCA15_SLP_MASK 0xF
#define PMIC_QI_VSRMCA15_SLP_SHIFT 8
#define PMIC_VSRMCA15_SAWCAL_TD_MASK 0x3
#define PMIC_VSRMCA15_SAWCAL_TD_SHIFT 4
#define PMIC_VSRMCA15_SLP_MASK 0xF
#define PMIC_VSRMCA15_SLP_SHIFT 0
#define PMIC_RG_VSRMCA15_RSV_MASK 0xFF
#define PMIC_RG_VSRMCA15_RSV_SHIFT 0
#define PMIC_VSRMCA15_TRACK_SLEEP_CTRL_MASK 0x1
#define PMIC_VSRMCA15_TRACK_SLEEP_CTRL_SHIFT 5
#define PMIC_VSRMCA15_TRACK_ON_CTRL_MASK 0x1
#define PMIC_VSRMCA15_TRACK_ON_CTRL_SHIFT 4
#define PMIC_VSRMCA15_BURST_CTRL_MASK 0x1
#define PMIC_VSRMCA15_BURST_CTRL_SHIFT 3
#define PMIC_VSRMCA15_DLC_CTRL_MASK 0x1
#define PMIC_VSRMCA15_DLC_CTRL_SHIFT 2
#define PMIC_VSRMCA15_VOSEL_CTRL_MASK 0x1
#define PMIC_VSRMCA15_VOSEL_CTRL_SHIFT 1
#define PMIC_VSRMCA15_EN_CTRL_MASK 0x1
#define PMIC_VSRMCA15_EN_CTRL_SHIFT 0
#define PMIC_VSRMCA15_BURST_SEL_MASK 0x3
#define PMIC_VSRMCA15_BURST_SEL_SHIFT 12
#define PMIC_VSRMCA15_DLC_SEL_MASK 0x3
#define PMIC_VSRMCA15_DLC_SEL_SHIFT 8
#define PMIC_VSRMCA15_VOSEL_SEL_MASK 0x3
#define PMIC_VSRMCA15_VOSEL_SEL_SHIFT 4
#define PMIC_VSRMCA15_EN_SEL_MASK 0x3
#define PMIC_VSRMCA15_EN_SEL_SHIFT 0
#define PMIC_QI_VSRMCA15_OC_STATUS_MASK 0x1
#define PMIC_QI_VSRMCA15_OC_STATUS_SHIFT 15
#define PMIC_QI_VSRMCA15_MODE_MASK 0x1
#define PMIC_QI_VSRMCA15_MODE_SHIFT 14
#define PMIC_QI_VSRMCA15_EN_MASK 0x1
#define PMIC_QI_VSRMCA15_EN_SHIFT 13
#define PMIC_QI_VSRMCA15_STB_MASK 0x1
#define PMIC_QI_VSRMCA15_STB_SHIFT 12
#define PMIC_VSRMCA15_STBTD_MASK 0x3
#define PMIC_VSRMCA15_STBTD_SHIFT 4
#define PMIC_VSRMCA15_EN_MASK 0x1
#define PMIC_VSRMCA15_EN_SHIFT 0
#define PMIC_VSRMCA15_SFCHG_REN_MASK 0x1
#define PMIC_VSRMCA15_SFCHG_REN_SHIFT 15
#define PMIC_VSRMCA15_SFCHG_RRATE_MASK 0x7F
#define PMIC_VSRMCA15_SFCHG_RRATE_SHIFT 8
#define PMIC_VSRMCA15_SFCHG_FEN_MASK 0x1
#define PMIC_VSRMCA15_SFCHG_FEN_SHIFT 7
#define PMIC_VSRMCA15_SFCHG_FRATE_MASK 0x7F
#define PMIC_VSRMCA15_SFCHG_FRATE_SHIFT 0
#define PMIC_VSRMCA15_VOSEL_MASK 0x7F
#define PMIC_VSRMCA15_VOSEL_SHIFT 0
#define PMIC_VSRMCA15_VOSEL_ON_MASK 0x7F
#define PMIC_VSRMCA15_VOSEL_ON_SHIFT 0
#define PMIC_VSRMCA15_VOSEL_SLEEP_MASK 0x7F
#define PMIC_VSRMCA15_VOSEL_SLEEP_SHIFT 0
#define PMIC_NI_VSRMCA15_VOSEL_MASK 0x7F
#define PMIC_NI_VSRMCA15_VOSEL_SHIFT 0
#define PMIC_QI_VSRMCA15_BURST_MASK 0x7
#define PMIC_QI_VSRMCA15_BURST_SHIFT 12
#define PMIC_VSRMCA15_BURST_SLEEP_MASK 0x7
#define PMIC_VSRMCA15_BURST_SLEEP_SHIFT 8
#define PMIC_VSRMCA15_BURST_ON_MASK 0x7
#define PMIC_VSRMCA15_BURST_ON_SHIFT 4
#define PMIC_VSRMCA15_BURST_MASK 0x7
#define PMIC_VSRMCA15_BURST_SHIFT 0
#define PMIC_QI_VSRMCA15_DLC_MASK 0x3
#define PMIC_QI_VSRMCA15_DLC_SHIFT 12
#define PMIC_VSRMCA15_DLC_SLEEP_MASK 0x3
#define PMIC_VSRMCA15_DLC_SLEEP_SHIFT 8
#define PMIC_VSRMCA15_DLC_ON_MASK 0x3
#define PMIC_VSRMCA15_DLC_ON_SHIFT 4
#define PMIC_VSRMCA15_DLC_MASK 0x3
#define PMIC_VSRMCA15_DLC_SHIFT 0
#define PMIC_QI_VSRMCA15_DLC_N_MASK 0x3
#define PMIC_QI_VSRMCA15_DLC_N_SHIFT 12
#define PMIC_VSRMCA15_DLC_N_SLEEP_MASK 0x3
#define PMIC_VSRMCA15_DLC_N_SLEEP_SHIFT 8
#define PMIC_VSRMCA15_DLC_N_ON_MASK 0x3
#define PMIC_VSRMCA15_DLC_N_ON_SHIFT 4
#define PMIC_VSRMCA15_DLC_N_MASK 0x3
#define PMIC_VSRMCA15_DLC_N_SHIFT 0
#define PMIC_QI_VSRMCA15_BURSTH_MASK 0x3
#define PMIC_QI_VSRMCA15_BURSTH_SHIFT 12
#define PMIC_QI_VSRMCA15_BURSTL_MASK 0x3
#define PMIC_QI_VSRMCA15_BURSTL_SHIFT 12
#define PMIC_NI_VSRMCA15_VSLEEP_SEL_MASK 0x1
#define PMIC_NI_VSRMCA15_VSLEEP_SEL_SHIFT 15
#define PMIC_NI_VSRMCA15_R2R_PDN_MASK 0x1
#define PMIC_NI_VSRMCA15_R2R_PDN_SHIFT 14
#define PMIC_VSRMCA15_VSLEEP_SEL_MASK 0x1
#define PMIC_VSRMCA15_VSLEEP_SEL_SHIFT 11
#define PMIC_VSRMCA15_R2R_PDN_MASK 0x1
#define PMIC_VSRMCA15_R2R_PDN_SHIFT 10
#define PMIC_VSRMCA15_VSLEEP_EN_MASK 0x1
#define PMIC_VSRMCA15_VSLEEP_EN_SHIFT 8
#define PMIC_NI_VSRMCA15_VOSEL_TRANS_MASK 0x1
#define PMIC_NI_VSRMCA15_VOSEL_TRANS_SHIFT 7
#define PMIC_VSRMCA15_VOSEL_TRANS_ONCE_MASK 0x1
#define PMIC_VSRMCA15_VOSEL_TRANS_ONCE_SHIFT 6
#define PMIC_VSRMCA15_VOSEL_TRANS_EN_MASK 0x3
#define PMIC_VSRMCA15_VOSEL_TRANS_EN_SHIFT 4
#define PMIC_VSRMCA15_TRANSTD_MASK 0x3
#define PMIC_VSRMCA15_TRANSTD_SHIFT 0
#define PMIC_VSRMCA15_VOSEL_OFFSET_MASK 0x7F
#define PMIC_VSRMCA15_VOSEL_OFFSET_SHIFT 8
#define PMIC_VSRMCA15_VOSEL_DELTA_MASK 0x7F
#define PMIC_VSRMCA15_VOSEL_DELTA_SHIFT 0
#define PMIC_VSRMCA15_VOSEL_ON_HB_MASK 0x7F
#define PMIC_VSRMCA15_VOSEL_ON_HB_SHIFT 8
#define PMIC_VSRMCA15_VOSEL_ON_LB_MASK 0x7F
#define PMIC_VSRMCA15_VOSEL_ON_LB_SHIFT 0
#define PMIC_VSRMCA15_VOSEL_SLEEP_LB_MASK 0x7F
#define PMIC_VSRMCA15_VOSEL_SLEEP_LB_SHIFT 0
#define PMIC_RG_VCORE_ZXOS_TRIM_MASK 0x3F
#define PMIC_RG_VCORE_ZXOS_TRIM_SHIFT 0
#define PMIC_RG_VCORE_ZX_OS_MASK 0x3
#define PMIC_RG_VCORE_ZX_OS_SHIFT 14
#define PMIC_RG_VCORE_CSL_MASK 0x3
#define PMIC_RG_VCORE_CSL_SHIFT 8
#define PMIC_RG_VCORE_CSR_MASK 0x3
#define PMIC_RG_VCORE_CSR_SHIFT 6
#define PMIC_RG_VCORE_CC_MASK 0x3
#define PMIC_RG_VCORE_CC_SHIFT 4
#define PMIC_RG_VCORE_RZSEL_MASK 0x3
#define PMIC_RG_VCORE_RZSEL_SHIFT 0
#define PMIC_RG_VCORE_NDIS_EN_MASK 0x1
#define PMIC_RG_VCORE_NDIS_EN_SHIFT 9
#define PMIC_RG_VCORE_MODESET_MASK 0x1
#define PMIC_RG_VCORE_MODESET_SHIFT 8
#define PMIC_RG_VCORE_CSM_MASK 0x7
#define PMIC_RG_VCORE_CSM_SHIFT 4
#define PMIC_RG_VCORE_AVP_EN_MASK 0x1
#define PMIC_RG_VCORE_AVP_EN_SHIFT 3
#define PMIC_RG_VCORE_AVP_OS_MASK 0x7
#define PMIC_RG_VCORE_AVP_OS_SHIFT 0
#define PMIC_RG_VCORE_SLP_MASK 0x3
#define PMIC_RG_VCORE_SLP_SHIFT 0
#define PMIC_RG_VCORE_RSV_MASK 0xFF
#define PMIC_RG_VCORE_RSV_SHIFT 0
#define PMIC_VCORE_BURST_CTRL_MASK 0x1
#define PMIC_VCORE_BURST_CTRL_SHIFT 3
#define PMIC_VCORE_DLC_CTRL_MASK 0x1
#define PMIC_VCORE_DLC_CTRL_SHIFT 2
#define PMIC_VCORE_VOSEL_CTRL_MASK 0x1
#define PMIC_VCORE_VOSEL_CTRL_SHIFT 1
#define PMIC_VCORE_EN_CTRL_MASK 0x1
#define PMIC_VCORE_EN_CTRL_SHIFT 0
#define PMIC_VCORE_BURST_SEL_MASK 0x3
#define PMIC_VCORE_BURST_SEL_SHIFT 12
#define PMIC_VCORE_DLC_SEL_MASK 0x3
#define PMIC_VCORE_DLC_SEL_SHIFT 8
#define PMIC_VCORE_VOSEL_SEL_MASK 0x3
#define PMIC_VCORE_VOSEL_SEL_SHIFT 4
#define PMIC_VCORE_EN_SEL_MASK 0x3
#define PMIC_VCORE_EN_SEL_SHIFT 0
#define PMIC_QI_VCORE_OC_STATUS_MASK 0x1
#define PMIC_QI_VCORE_OC_STATUS_SHIFT 15
#define PMIC_QI_VCORE_MODE_MASK 0x1
#define PMIC_QI_VCORE_MODE_SHIFT 14
#define PMIC_QI_VCORE_EN_MASK 0x1
#define PMIC_QI_VCORE_EN_SHIFT 13
#define PMIC_QI_VCORE_STB_MASK 0x1
#define PMIC_QI_VCORE_STB_SHIFT 12
#define PMIC_VCORE_EN_MASK 0x1
#define PMIC_VCORE_EN_SHIFT 0
#define PMIC_VCORE_SFCHG_REN_MASK 0x1
#define PMIC_VCORE_SFCHG_REN_SHIFT 15
#define PMIC_VCORE_SFCHG_RRATE_MASK 0x7F
#define PMIC_VCORE_SFCHG_RRATE_SHIFT 8
#define PMIC_VCORE_SFCHG_FEN_MASK 0x1
#define PMIC_VCORE_SFCHG_FEN_SHIFT 7
#define PMIC_VCORE_SFCHG_FRATE_MASK 0x7F
#define PMIC_VCORE_SFCHG_FRATE_SHIFT 0
#define PMIC_VCORE_VOSEL_MASK 0x7F
#define PMIC_VCORE_VOSEL_SHIFT 0
#define PMIC_VCORE_VOSEL_ON_MASK 0x7F
#define PMIC_VCORE_VOSEL_ON_SHIFT 0
#define PMIC_VCORE_VOSEL_SLEEP_MASK 0x7F
#define PMIC_VCORE_VOSEL_SLEEP_SHIFT 0
#define PMIC_NI_VCORE_VOSEL_MASK 0x7F
#define PMIC_NI_VCORE_VOSEL_SHIFT 0
#define PMIC_QI_VCORE_BURST_MASK 0x3
#define PMIC_QI_VCORE_BURST_SHIFT 12
#define PMIC_VCORE_BURST_SLEEP_MASK 0x3
#define PMIC_VCORE_BURST_SLEEP_SHIFT 8
#define PMIC_VCORE_BURST_ON_MASK 0x3
#define PMIC_VCORE_BURST_ON_SHIFT 4
#define PMIC_VCORE_BURST_MASK 0x3
#define PMIC_VCORE_BURST_SHIFT 0
#define PMIC_QI_VCORE_DLC_MASK 0x3
#define PMIC_QI_VCORE_DLC_SHIFT 12
#define PMIC_VCORE_DLC_SLEEP_MASK 0x3
#define PMIC_VCORE_DLC_SLEEP_SHIFT 8
#define PMIC_VCORE_DLC_ON_MASK 0x3
#define PMIC_VCORE_DLC_ON_SHIFT 4
#define PMIC_VCORE_DLC_MASK 0x3
#define PMIC_VCORE_DLC_SHIFT 0
#define PMIC_QI_VCORE_DLC_N_MASK 0x3
#define PMIC_QI_VCORE_DLC_N_SHIFT 12
#define PMIC_VCORE_DLC_N_SLEEP_MASK 0x3
#define PMIC_VCORE_DLC_N_SLEEP_SHIFT 8
#define PMIC_VCORE_DLC_N_ON_MASK 0x3
#define PMIC_VCORE_DLC_N_ON_SHIFT 4
#define PMIC_VCORE_DLC_N_MASK 0x3
#define PMIC_VCORE_DLC_N_SHIFT 0
#define PMIC_QI_VCORE_BURSTH_MASK 0x3
#define PMIC_QI_VCORE_BURSTH_SHIFT 12
#define PMIC_QI_VCORE_BURSTL_MASK 0x3
#define PMIC_QI_VCORE_BURSTL_SHIFT 12
#define PMIC_NI_VCORE_VSLEEP_SEL_MASK 0x1
#define PMIC_NI_VCORE_VSLEEP_SEL_SHIFT 15
#define PMIC_NI_VCORE_R2R_PDN_MASK 0x1
#define PMIC_NI_VCORE_R2R_PDN_SHIFT 14
#define PMIC_VCORE_VSLEEP_SEL_MASK 0x1
#define PMIC_VCORE_VSLEEP_SEL_SHIFT 11
#define PMIC_VCORE_R2R_PDN_MASK 0x1
#define PMIC_VCORE_R2R_PDN_SHIFT 10
#define PMIC_VCORE_VSLEEP_EN_MASK 0x1
#define PMIC_VCORE_VSLEEP_EN_SHIFT 8
#define PMIC_NI_VCORE_VOSEL_TRANS_MASK 0x1
#define PMIC_NI_VCORE_VOSEL_TRANS_SHIFT 7
#define PMIC_VCORE_VOSEL_TRANS_ONCE_MASK 0x1
#define PMIC_VCORE_VOSEL_TRANS_ONCE_SHIFT 6
#define PMIC_VCORE_VOSEL_TRANS_EN_MASK 0x3
#define PMIC_VCORE_VOSEL_TRANS_EN_SHIFT 4
#define PMIC_VCORE_TRANSTD_MASK 0x3
#define PMIC_VCORE_TRANSTD_SHIFT 0
#define PMIC_RG_VGPU_ZXOS_TRIM_MASK 0x3F
#define PMIC_RG_VGPU_ZXOS_TRIM_SHIFT 0
#define PMIC_RG_VGPU_ZX_OS_MASK 0x3
#define PMIC_RG_VGPU_ZX_OS_SHIFT 14
#define PMIC_RG_VGPU_CSL_MASK 0x3
#define PMIC_RG_VGPU_CSL_SHIFT 8
#define PMIC_RG_VGPU_CSR_MASK 0x3
#define PMIC_RG_VGPU_CSR_SHIFT 6
#define PMIC_RG_VGPU_CC_MASK 0x3
#define PMIC_RG_VGPU_CC_SHIFT 4
#define PMIC_RG_VGPU_RZSEL_MASK 0x3
#define PMIC_RG_VGPU_RZSEL_SHIFT 0
#define PMIC_RG_VGPU_NDIS_EN_MASK 0x1
#define PMIC_RG_VGPU_NDIS_EN_SHIFT 9
#define PMIC_RG_VGPU_MODESET_MASK 0x1
#define PMIC_RG_VGPU_MODESET_SHIFT 8
#define PMIC_RG_VGPU_CSM_MASK 0x7
#define PMIC_RG_VGPU_CSM_SHIFT 4
#define PMIC_RG_VGPU_AVP_EN_MASK 0x1
#define PMIC_RG_VGPU_AVP_EN_SHIFT 3
#define PMIC_RG_VGPU_AVP_OS_MASK 0x7
#define PMIC_RG_VGPU_AVP_OS_SHIFT 0
#define PMIC_RG_VGPU_SLP_MASK 0x3
#define PMIC_RG_VGPU_SLP_SHIFT 0
#define PMIC_RG_VGPU_RSV_MASK 0xFF
#define PMIC_RG_VGPU_RSV_SHIFT 0
#define PMIC_VGPU_BURST_CTRL_MASK 0x1
#define PMIC_VGPU_BURST_CTRL_SHIFT 3
#define PMIC_VGPU_DLC_CTRL_MASK 0x1
#define PMIC_VGPU_DLC_CTRL_SHIFT 2
#define PMIC_VGPU_VOSEL_CTRL_MASK 0x1
#define PMIC_VGPU_VOSEL_CTRL_SHIFT 1
#define PMIC_VGPU_EN_CTRL_MASK 0x1
#define PMIC_VGPU_EN_CTRL_SHIFT 0
#define PMIC_VGPU_BURST_SEL_MASK 0x3
#define PMIC_VGPU_BURST_SEL_SHIFT 12
#define PMIC_VGPU_DLC_SEL_MASK 0x3
#define PMIC_VGPU_DLC_SEL_SHIFT 8
#define PMIC_VGPU_VOSEL_SEL_MASK 0x3
#define PMIC_VGPU_VOSEL_SEL_SHIFT 4
#define PMIC_VGPU_EN_SEL_MASK 0x3
#define PMIC_VGPU_EN_SEL_SHIFT 0
#define PMIC_QI_VGPU_OC_STATUS_MASK 0x1
#define PMIC_QI_VGPU_OC_STATUS_SHIFT 15
#define PMIC_QI_VGPU_MODE_MASK 0x1
#define PMIC_QI_VGPU_MODE_SHIFT 14
#define PMIC_QI_VGPU_EN_MASK 0x1
#define PMIC_QI_VGPU_EN_SHIFT 13
#define PMIC_QI_VGPU_STB_MASK 0x1
#define PMIC_QI_VGPU_STB_SHIFT 12
#define PMIC_VGPU_STBTD_MASK 0x3
#define PMIC_VGPU_STBTD_SHIFT 4
#define PMIC_VGPU_EN_MASK 0x1
#define PMIC_VGPU_EN_SHIFT 0
#define PMIC_VGPU_SFCHG_REN_MASK 0x1
#define PMIC_VGPU_SFCHG_REN_SHIFT 15
#define PMIC_VGPU_SFCHG_RRATE_MASK 0x7F
#define PMIC_VGPU_SFCHG_RRATE_SHIFT 8
#define PMIC_VGPU_SFCHG_FEN_MASK 0x1
#define PMIC_VGPU_SFCHG_FEN_SHIFT 7
#define PMIC_VGPU_SFCHG_FRATE_MASK 0x7F
#define PMIC_VGPU_SFCHG_FRATE_SHIFT 0
#define PMIC_VGPU_VOSEL_MASK 0x7F
#define PMIC_VGPU_VOSEL_SHIFT 0
#define PMIC_VGPU_VOSEL_ON_MASK 0x7F
#define PMIC_VGPU_VOSEL_ON_SHIFT 0
#define PMIC_VGPU_VOSEL_SLEEP_MASK 0x7F
#define PMIC_VGPU_VOSEL_SLEEP_SHIFT 0
#define PMIC_NI_VGPU_VOSEL_MASK 0x7F
#define PMIC_NI_VGPU_VOSEL_SHIFT 0
#define PMIC_QI_VGPU_BURST_MASK 0x3
#define PMIC_QI_VGPU_BURST_SHIFT 12
#define PMIC_VGPU_BURST_SLEEP_MASK 0x3
#define PMIC_VGPU_BURST_SLEEP_SHIFT 8
#define PMIC_VGPU_BURST_ON_MASK 0x3
#define PMIC_VGPU_BURST_ON_SHIFT 4
#define PMIC_VGPU_BURST_MASK 0x3
#define PMIC_VGPU_BURST_SHIFT 0
#define PMIC_QI_VGPU_DLC_MASK 0x3
#define PMIC_QI_VGPU_DLC_SHIFT 12
#define PMIC_VGPU_DLC_SLEEP_MASK 0x3
#define PMIC_VGPU_DLC_SLEEP_SHIFT 8
#define PMIC_VGPU_DLC_ON_MASK 0x3
#define PMIC_VGPU_DLC_ON_SHIFT 4
#define PMIC_VGPU_DLC_MASK 0x3
#define PMIC_VGPU_DLC_SHIFT 0
#define PMIC_QI_VGPU_DLC_N_MASK 0x3
#define PMIC_QI_VGPU_DLC_N_SHIFT 12
#define PMIC_VGPU_DLC_N_SLEEP_MASK 0x3
#define PMIC_VGPU_DLC_N_SLEEP_SHIFT 8
#define PMIC_VGPU_DLC_N_ON_MASK 0x3
#define PMIC_VGPU_DLC_N_ON_SHIFT 4
#define PMIC_VGPU_DLC_N_MASK 0x3
#define PMIC_VGPU_DLC_N_SHIFT 0
#define PMIC_QI_VGPU_BURSTH_MASK 0x3
#define PMIC_QI_VGPU_BURSTH_SHIFT 12
#define PMIC_QI_VGPU_BURSTL_MASK 0x3
#define PMIC_QI_VGPU_BURSTL_SHIFT 12
#define PMIC_NI_VGPU_VSLEEP_SEL_MASK 0x1
#define PMIC_NI_VGPU_VSLEEP_SEL_SHIFT 15
#define PMIC_NI_VGPU_R2R_PDN_MASK 0x1
#define PMIC_NI_VGPU_R2R_PDN_SHIFT 14
#define PMIC_VGPU_VSLEEP_SEL_MASK 0x1
#define PMIC_VGPU_VSLEEP_SEL_SHIFT 11
#define PMIC_VGPU_R2R_PDN_MASK 0x1
#define PMIC_VGPU_R2R_PDN_SHIFT 10
#define PMIC_VGPU_VSLEEP_EN_MASK 0x1
#define PMIC_VGPU_VSLEEP_EN_SHIFT 8
#define PMIC_NI_VGPU_VOSEL_TRANS_MASK 0x1
#define PMIC_NI_VGPU_VOSEL_TRANS_SHIFT 7
#define PMIC_VGPU_VOSEL_TRANS_ONCE_MASK 0x1
#define PMIC_VGPU_VOSEL_TRANS_ONCE_SHIFT 6
#define PMIC_VGPU_VOSEL_TRANS_EN_MASK 0x3
#define PMIC_VGPU_VOSEL_TRANS_EN_SHIFT 4
#define PMIC_VGPU_TRANSTD_MASK 0x3
#define PMIC_VGPU_TRANSTD_SHIFT 0
#define PMIC_RG_VIO18_TRIM_MASK 0x7
#define PMIC_RG_VIO18_TRIM_SHIFT 0
#define PMIC_RG_VIO18_ZX_OS_MASK 0x3
#define PMIC_RG_VIO18_ZX_OS_SHIFT 14
#define PMIC_RG_VIO18_SLEW_MASK 0x3
#define PMIC_RG_VIO18_SLEW_SHIFT 12
#define PMIC_RG_VIO18_SLEW_NMOS_MASK 0x3
#define PMIC_RG_VIO18_SLEW_NMOS_SHIFT 10
#define PMIC_RG_VIO18_CSL_MASK 0x3
#define PMIC_RG_VIO18_CSL_SHIFT 8
#define PMIC_RG_VIO18_CSR_MASK 0x3
#define PMIC_RG_VIO18_CSR_SHIFT 6
#define PMIC_RG_VIO18_CC_MASK 0x3
#define PMIC_RG_VIO18_CC_SHIFT 4
#define PMIC_RG_VIO18_RZSEL_MASK 0x3
#define PMIC_RG_VIO18_RZSEL_SHIFT 0
#define PMIC_RG_VIO18_CSMIR_MASK 0x3
#define PMIC_RG_VIO18_CSMIR_SHIFT 12
#define PMIC_RG_VIO18_NDIS_EN_MASK 0x1
#define PMIC_RG_VIO18_NDIS_EN_SHIFT 9
#define PMIC_RG_VIO18_MODESET_MASK 0x1
#define PMIC_RG_VIO18_MODESET_SHIFT 8
#define PMIC_RG_VIO18_SLP_MASK 0x3
#define PMIC_RG_VIO18_SLP_SHIFT 0
#define PMIC_RG_VIO18_RSV_MASK 0xFF
#define PMIC_RG_VIO18_RSV_SHIFT 0
#define PMIC_VIO18_BURST_CTRL_MASK 0x1
#define PMIC_VIO18_BURST_CTRL_SHIFT 3
#define PMIC_VIO18_DLC_CTRL_MASK 0x1
#define PMIC_VIO18_DLC_CTRL_SHIFT 2
#define PMIC_VIO18_VOSEL_CTRL_MASK 0x1
#define PMIC_VIO18_VOSEL_CTRL_SHIFT 1
#define PMIC_VIO18_EN_CTRL_MASK 0x1
#define PMIC_VIO18_EN_CTRL_SHIFT 0
#define PMIC_VIO18_BURST_SEL_MASK 0x3
#define PMIC_VIO18_BURST_SEL_SHIFT 12
#define PMIC_VIO18_DLC_SEL_MASK 0x3
#define PMIC_VIO18_DLC_SEL_SHIFT 8
#define PMIC_VIO18_VOSEL_SEL_MASK 0x3
#define PMIC_VIO18_VOSEL_SEL_SHIFT 4
#define PMIC_VIO18_EN_SEL_MASK 0x3
#define PMIC_VIO18_EN_SEL_SHIFT 0
#define PMIC_QI_VIO18_OC_STATUS_MASK 0x1
#define PMIC_QI_VIO18_OC_STATUS_SHIFT 15
#define PMIC_QI_VIO18_MODE_MASK 0x1
#define PMIC_QI_VIO18_MODE_SHIFT 14
#define PMIC_QI_VIO18_EN_MASK 0x1
#define PMIC_QI_VIO18_EN_SHIFT 13
#define PMIC_QI_VIO18_STB_MASK 0x1
#define PMIC_QI_VIO18_STB_SHIFT 12
#define PMIC_VIO18_EN_MASK 0x1
#define PMIC_VIO18_EN_SHIFT 0
#define PMIC_VIO18_SFCHG_REN_MASK 0x1
#define PMIC_VIO18_SFCHG_REN_SHIFT 15
#define PMIC_VIO18_SFCHG_RRATE_MASK 0x7F
#define PMIC_VIO18_SFCHG_RRATE_SHIFT 8
#define PMIC_VIO18_SFCHG_FEN_MASK 0x1
#define PMIC_VIO18_SFCHG_FEN_SHIFT 7
#define PMIC_VIO18_SFCHG_FRATE_MASK 0x7F
#define PMIC_VIO18_SFCHG_FRATE_SHIFT 0
#define PMIC_VIO18_VOSEL_MASK 0x1F
#define PMIC_VIO18_VOSEL_SHIFT 0
#define PMIC_VIO18_VOSEL_ON_MASK 0x1F
#define PMIC_VIO18_VOSEL_ON_SHIFT 0
#define PMIC_VIO18_VOSEL_SLEEP_MASK 0x1F
#define PMIC_VIO18_VOSEL_SLEEP_SHIFT 0
#define PMIC_NI_VIO18_VOSEL_MASK 0x1F
#define PMIC_NI_VIO18_VOSEL_SHIFT 0
#define PMIC_QI_VIO18_BURST_MASK 0x3
#define PMIC_QI_VIO18_BURST_SHIFT 12
#define PMIC_QI_VIO18_DLC_MASK 0x3
#define PMIC_QI_VIO18_DLC_SHIFT 12
#define PMIC_VIO18_DLC_SLEEP_MASK 0x3
#define PMIC_VIO18_DLC_SLEEP_SHIFT 8
#define PMIC_VIO18_DLC_ON_MASK 0x3
#define PMIC_VIO18_DLC_ON_SHIFT 4
#define PMIC_VIO18_DLC_MASK 0x3
#define PMIC_VIO18_DLC_SHIFT 0
#define PMIC_QI_VIO18_DLC_N_MASK 0x3
#define PMIC_QI_VIO18_DLC_N_SHIFT 12
#define PMIC_VIO18_DLC_N_SLEEP_MASK 0x3
#define PMIC_VIO18_DLC_N_SLEEP_SHIFT 8
#define PMIC_VIO18_DLC_N_ON_MASK 0x3
#define PMIC_VIO18_DLC_N_ON_SHIFT 4
#define PMIC_VIO18_DLC_N_MASK 0x3
#define PMIC_VIO18_DLC_N_SHIFT 0
#define PMIC_QI_VIO18_BURSTH_MASK 0x3
#define PMIC_QI_VIO18_BURSTH_SHIFT 12
#define PMIC_VIO18_BURSTH_SLEEP_MASK 0x3
#define PMIC_VIO18_BURSTH_SLEEP_SHIFT 8
#define PMIC_VIO18_BURSTH_ON_MASK 0x3
#define PMIC_VIO18_BURSTH_ON_SHIFT 4
#define PMIC_VIO18_BURSTH_MASK 0x3
#define PMIC_VIO18_BURSTH_SHIFT 0
#define PMIC_QI_VIO18_BURSTL_MASK 0x3
#define PMIC_QI_VIO18_BURSTL_SHIFT 12
#define PMIC_VIO18_BURSTL_SLEEP_MASK 0x3
#define PMIC_VIO18_BURSTL_SLEEP_SHIFT 8
#define PMIC_VIO18_BURSTL_ON_MASK 0x3
#define PMIC_VIO18_BURSTL_ON_SHIFT 4
#define PMIC_VIO18_BURSTL_MASK 0x3
#define PMIC_VIO18_BURSTL_SHIFT 0
#define PMIC_QI_VIO18_SLEEP_PDN_MASK 0x1
#define PMIC_QI_VIO18_SLEEP_PDN_SHIFT 14
#define PMIC_VIO18_SLEEP_PDN_MASK 0x1
#define PMIC_VIO18_SLEEP_PDN_SHIFT 10
#define PMIC_VIO18_VSLEEP_EN_MASK 0x1
#define PMIC_VIO18_VSLEEP_EN_SHIFT 8
#define PMIC_RG_VPCA7_ZXOS_TRIM_MASK 0x3F
#define PMIC_RG_VPCA7_ZXOS_TRIM_SHIFT 0
#define PMIC_RG_VPCA7_ZX_OS_MASK 0x3
#define PMIC_RG_VPCA7_ZX_OS_SHIFT 14
#define PMIC_RG_VPCA7_CSL_MASK 0x3
#define PMIC_RG_VPCA7_CSL_SHIFT 8
#define PMIC_RG_VPCA7_CSR_MASK 0x3
#define PMIC_RG_VPCA7_CSR_SHIFT 6
#define PMIC_RG_VPCA7_CC_MASK 0x3
#define PMIC_RG_VPCA7_CC_SHIFT 4
#define PMIC_RG_VPCA7_RZSEL_MASK 0x3
#define PMIC_RG_VPCA7_RZSEL_SHIFT 0
#define PMIC_RG_VPCA7_NDIS_EN_MASK 0x1
#define PMIC_RG_VPCA7_NDIS_EN_SHIFT 9
#define PMIC_RG_VPCA7_MODESET_MASK 0x1
#define PMIC_RG_VPCA7_MODESET_SHIFT 8
#define PMIC_RG_VPCA7_CSM_MASK 0x7
#define PMIC_RG_VPCA7_CSM_SHIFT 4
#define PMIC_RG_VPCA7_SMRIP_EN_MASK 0x1
#define PMIC_RG_VPCA7_SMRIP_EN_SHIFT 0
#define PMIC_QI_VPCA7_SLPO_OUT_MASK 0xF
#define PMIC_QI_VPCA7_SLPO_OUT_SHIFT 12
#define PMIC_QI_VPCA7_SLP_MASK 0xF
#define PMIC_QI_VPCA7_SLP_SHIFT 8
#define PMIC_VPCA7_SAWCAL_TD_MASK 0x3
#define PMIC_VPCA7_SAWCAL_TD_SHIFT 4
#define PMIC_VPCA7_SLP_MASK 0xF
#define PMIC_VPCA7_SLP_SHIFT 0
#define PMIC_RG_VPCA7_RSV_MASK 0xFF
#define PMIC_RG_VPCA7_RSV_SHIFT 0
#define PMIC_VPCA7_TRACK_ON_CTRL_MASK 0x1
#define PMIC_VPCA7_TRACK_ON_CTRL_SHIFT 4
#define PMIC_VPCA7_BURST_CTRL_MASK 0x1
#define PMIC_VPCA7_BURST_CTRL_SHIFT 3
#define PMIC_VPCA7_DLC_CTRL_MASK 0x1
#define PMIC_VPCA7_DLC_CTRL_SHIFT 2
#define PMIC_VPCA7_VOSEL_CTRL_MASK 0x1
#define PMIC_VPCA7_VOSEL_CTRL_SHIFT 1
#define PMIC_VPCA7_EN_CTRL_MASK 0x1
#define PMIC_VPCA7_EN_CTRL_SHIFT 0
#define PMIC_VPCA7_BURST_SEL_MASK 0x3
#define PMIC_VPCA7_BURST_SEL_SHIFT 12
#define PMIC_VPCA7_DLC_SEL_MASK 0x3
#define PMIC_VPCA7_DLC_SEL_SHIFT 8
#define PMIC_VPCA7_VOSEL_SEL_MASK 0x3
#define PMIC_VPCA7_VOSEL_SEL_SHIFT 4
#define PMIC_VPCA7_EN_SEL_MASK 0x3
#define PMIC_VPCA7_EN_SEL_SHIFT 0
#define PMIC_QI_VPCA7_OC_STATUS_MASK 0x1
#define PMIC_QI_VPCA7_OC_STATUS_SHIFT 15
#define PMIC_QI_VPCA7_MODE_MASK 0x1
#define PMIC_QI_VPCA7_MODE_SHIFT 14
#define PMIC_QI_VPCA7_EN_MASK 0x1
#define PMIC_QI_VPCA7_EN_SHIFT 13
#define PMIC_QI_VPCA7_STB_MASK 0x1
#define PMIC_QI_VPCA7_STB_SHIFT 12
#define PMIC_VPCA7_STBTD_MASK 0x3
#define PMIC_VPCA7_STBTD_SHIFT 4
#define PMIC_VPCA7_EN_MASK 0x1
#define PMIC_VPCA7_EN_SHIFT 0
#define PMIC_VPCA7_SFCHG_REN_MASK 0x1
#define PMIC_VPCA7_SFCHG_REN_SHIFT 15
#define PMIC_VPCA7_SFCHG_RRATE_MASK 0x7F
#define PMIC_VPCA7_SFCHG_RRATE_SHIFT 8
#define PMIC_VPCA7_SFCHG_FEN_MASK 0x1
#define PMIC_VPCA7_SFCHG_FEN_SHIFT 7
#define PMIC_VPCA7_SFCHG_FRATE_MASK 0x7F
#define PMIC_VPCA7_SFCHG_FRATE_SHIFT 0
#define PMIC_VPCA7_VOSEL_MASK 0x7F
#define PMIC_VPCA7_VOSEL_SHIFT 0
#define PMIC_VPCA7_VOSEL_ON_MASK 0x7F
#define PMIC_VPCA7_VOSEL_ON_SHIFT 0
#define PMIC_VPCA7_VOSEL_SLEEP_MASK 0x7F
#define PMIC_VPCA7_VOSEL_SLEEP_SHIFT 0
#define PMIC_NI_VPCA7_VOSEL_MASK 0x7F
#define PMIC_NI_VPCA7_VOSEL_SHIFT 0
#define PMIC_QI_VPCA7_BURST_MASK 0x7
#define PMIC_QI_VPCA7_BURST_SHIFT 12
#define PMIC_VPCA7_BURST_SLEEP_MASK 0x7
#define PMIC_VPCA7_BURST_SLEEP_SHIFT 8
#define PMIC_VPCA7_BURST_ON_MASK 0x7
#define PMIC_VPCA7_BURST_ON_SHIFT 4
#define PMIC_VPCA7_BURST_MASK 0x7
#define PMIC_VPCA7_BURST_SHIFT 0
#define PMIC_QI_VPCA7_DLC_MASK 0x3
#define PMIC_QI_VPCA7_DLC_SHIFT 12
#define PMIC_VPCA7_DLC_SLEEP_MASK 0x3
#define PMIC_VPCA7_DLC_SLEEP_SHIFT 8
#define PMIC_VPCA7_DLC_ON_MASK 0x3
#define PMIC_VPCA7_DLC_ON_SHIFT 4
#define PMIC_VPCA7_DLC_MASK 0x3
#define PMIC_VPCA7_DLC_SHIFT 0
#define PMIC_QI_VPCA7_DLC_N_MASK 0x3
#define PMIC_QI_VPCA7_DLC_N_SHIFT 12
#define PMIC_VPCA7_DLC_N_SLEEP_MASK 0x3
#define PMIC_VPCA7_DLC_N_SLEEP_SHIFT 8
#define PMIC_VPCA7_DLC_N_ON_MASK 0x3
#define PMIC_VPCA7_DLC_N_ON_SHIFT 4
#define PMIC_VPCA7_DLC_N_MASK 0x3
#define PMIC_VPCA7_DLC_N_SHIFT 0
#define PMIC_QI_VPCA7_BURSTH_MASK 0x3
#define PMIC_QI_VPCA7_BURSTH_SHIFT 12
#define PMIC_QI_VPCA7_BURSTL_MASK 0x3
#define PMIC_QI_VPCA7_BURSTL_SHIFT 12
#define PMIC_NI_VPCA7_VSLEEP_SEL_MASK 0x1
#define PMIC_NI_VPCA7_VSLEEP_SEL_SHIFT 15
#define PMIC_NI_VPCA7_R2R_PDN_MASK 0x1
#define PMIC_NI_VPCA7_R2R_PDN_SHIFT 14
#define PMIC_VPCA7_VSLEEP_SEL_MASK 0x1
#define PMIC_VPCA7_VSLEEP_SEL_SHIFT 11
#define PMIC_VPCA7_R2R_PDN_MASK 0x1
#define PMIC_VPCA7_R2R_PDN_SHIFT 10
#define PMIC_VPCA7_VSLEEP_EN_MASK 0x1
#define PMIC_VPCA7_VSLEEP_EN_SHIFT 8
#define PMIC_NI_VPCA7_VOSEL_TRANS_MASK 0x1
#define PMIC_NI_VPCA7_VOSEL_TRANS_SHIFT 7
#define PMIC_VPCA7_VOSEL_TRANS_ONCE_MASK 0x1
#define PMIC_VPCA7_VOSEL_TRANS_ONCE_SHIFT 6
#define PMIC_VPCA7_VOSEL_TRANS_EN_MASK 0x3
#define PMIC_VPCA7_VOSEL_TRANS_EN_SHIFT 4
#define PMIC_VPCA7_TRANSTD_MASK 0x3
#define PMIC_VPCA7_TRANSTD_SHIFT 0
#define PMIC_RG_VSRMCA7_ZXOS_TRIM_MASK 0x3F
#define PMIC_RG_VSRMCA7_ZXOS_TRIM_SHIFT 0
#define PMIC_RG_VSRMCA7_ZX_OS_MASK 0x3
#define PMIC_RG_VSRMCA7_ZX_OS_SHIFT 14
#define PMIC_RG_VSRMCA7_CSL_MASK 0x3
#define PMIC_RG_VSRMCA7_CSL_SHIFT 8
#define PMIC_RG_VSRMCA7_CSR_MASK 0x3
#define PMIC_RG_VSRMCA7_CSR_SHIFT 6
#define PMIC_RG_VSRMCA7_CC_MASK 0x3
#define PMIC_RG_VSRMCA7_CC_SHIFT 4
#define PMIC_RG_VSRMCA7_RZSEL_MASK 0x3
#define PMIC_RG_VSRMCA7_RZSEL_SHIFT 0
#define PMIC_RG_VSRMCA7_NDIS_EN_MASK 0x1
#define PMIC_RG_VSRMCA7_NDIS_EN_SHIFT 9
#define PMIC_RG_VSRMCA7_MODESET_MASK 0x1
#define PMIC_RG_VSRMCA7_MODESET_SHIFT 8
#define PMIC_RG_VSRMCA7_CSM_MASK 0x7
#define PMIC_RG_VSRMCA7_CSM_SHIFT 4
#define PMIC_RG_VSRMCA7_SMRIP_EN_MASK 0x1
#define PMIC_RG_VSRMCA7_SMRIP_EN_SHIFT 0
#define PMIC_QI_VSRMCA7_SLPO_OUT_MASK 0xF
#define PMIC_QI_VSRMCA7_SLPO_OUT_SHIFT 12
#define PMIC_QI_VSRMCA7_SLP_MASK 0xF
#define PMIC_QI_VSRMCA7_SLP_SHIFT 8
#define PMIC_VSRMCA7_SAWCAL_TD_MASK 0x3
#define PMIC_VSRMCA7_SAWCAL_TD_SHIFT 4
#define PMIC_VSRMCA7_SLP_MASK 0xF
#define PMIC_VSRMCA7_SLP_SHIFT 0
#define PMIC_RG_VSRMCA7_RSV_MASK 0xFF
#define PMIC_RG_VSRMCA7_RSV_SHIFT 0
#define PMIC_VSRMCA7_TRACK_SLEEP_CTRL_MASK 0x1
#define PMIC_VSRMCA7_TRACK_SLEEP_CTRL_SHIFT 5
#define PMIC_VSRMCA7_TRACK_ON_CTRL_MASK 0x1
#define PMIC_VSRMCA7_TRACK_ON_CTRL_SHIFT 4
#define PMIC_VSRMCA7_BURST_CTRL_MASK 0x1
#define PMIC_VSRMCA7_BURST_CTRL_SHIFT 3
#define PMIC_VSRMCA7_DLC_CTRL_MASK 0x1
#define PMIC_VSRMCA7_DLC_CTRL_SHIFT 2
#define PMIC_VSRMCA7_VOSEL_CTRL_MASK 0x1
#define PMIC_VSRMCA7_VOSEL_CTRL_SHIFT 1
#define PMIC_VSRMCA7_EN_CTRL_MASK 0x1
#define PMIC_VSRMCA7_EN_CTRL_SHIFT 0
#define PMIC_VSRMCA7_BURST_SEL_MASK 0x3
#define PMIC_VSRMCA7_BURST_SEL_SHIFT 12
#define PMIC_VSRMCA7_DLC_SEL_MASK 0x3
#define PMIC_VSRMCA7_DLC_SEL_SHIFT 8
#define PMIC_VSRMCA7_VOSEL_SEL_MASK 0x3
#define PMIC_VSRMCA7_VOSEL_SEL_SHIFT 4
#define PMIC_VSRMCA7_EN_SEL_MASK 0x3
#define PMIC_VSRMCA7_EN_SEL_SHIFT 0
#define PMIC_QI_VSRMCA7_OC_STATUS_MASK 0x1
#define PMIC_QI_VSRMCA7_OC_STATUS_SHIFT 15
#define PMIC_QI_VSRMCA7_MODE_MASK 0x1
#define PMIC_QI_VSRMCA7_MODE_SHIFT 14
#define PMIC_QI_VSRMCA7_EN_MASK 0x1
#define PMIC_QI_VSRMCA7_EN_SHIFT 13
#define PMIC_QI_VSRMCA7_STB_MASK 0x1
#define PMIC_QI_VSRMCA7_STB_SHIFT 12
#define PMIC_VSRMCA7_STBTD_MASK 0x3
#define PMIC_VSRMCA7_STBTD_SHIFT 4
#define PMIC_VSRMCA7_EN_MASK 0x1
#define PMIC_VSRMCA7_EN_SHIFT 0
#define PMIC_VSRMCA7_SFCHG_REN_MASK 0x1
#define PMIC_VSRMCA7_SFCHG_REN_SHIFT 15
#define PMIC_VSRMCA7_SFCHG_RRATE_MASK 0x7F
#define PMIC_VSRMCA7_SFCHG_RRATE_SHIFT 8
#define PMIC_VSRMCA7_SFCHG_FEN_MASK 0x1
#define PMIC_VSRMCA7_SFCHG_FEN_SHIFT 7
#define PMIC_VSRMCA7_SFCHG_FRATE_MASK 0x7F
#define PMIC_VSRMCA7_SFCHG_FRATE_SHIFT 0
#define PMIC_VSRMCA7_VOSEL_MASK 0x7F
#define PMIC_VSRMCA7_VOSEL_SHIFT 0
#define PMIC_VSRMCA7_VOSEL_ON_MASK 0x7F
#define PMIC_VSRMCA7_VOSEL_ON_SHIFT 0
#define PMIC_VSRMCA7_VOSEL_SLEEP_MASK 0x7F
#define PMIC_VSRMCA7_VOSEL_SLEEP_SHIFT 0
#define PMIC_NI_VSRMCA7_VOSEL_MASK 0x7F
#define PMIC_NI_VSRMCA7_VOSEL_SHIFT 0
#define PMIC_QI_VSRMCA7_BURST_MASK 0x7
#define PMIC_QI_VSRMCA7_BURST_SHIFT 12
#define PMIC_VSRMCA7_BURST_SLEEP_MASK 0x7
#define PMIC_VSRMCA7_BURST_SLEEP_SHIFT 8
#define PMIC_VSRMCA7_BURST_ON_MASK 0x7
#define PMIC_VSRMCA7_BURST_ON_SHIFT 4
#define PMIC_VSRMCA7_BURST_MASK 0x7
#define PMIC_VSRMCA7_BURST_SHIFT 0
#define PMIC_QI_VSRMCA7_DLC_MASK 0x3
#define PMIC_QI_VSRMCA7_DLC_SHIFT 12
#define PMIC_VSRMCA7_DLC_SLEEP_MASK 0x3
#define PMIC_VSRMCA7_DLC_SLEEP_SHIFT 8
#define PMIC_VSRMCA7_DLC_ON_MASK 0x3
#define PMIC_VSRMCA7_DLC_ON_SHIFT 4
#define PMIC_VSRMCA7_DLC_MASK 0x3
#define PMIC_VSRMCA7_DLC_SHIFT 0
#define PMIC_QI_VSRMCA7_DLC_N_MASK 0x3
#define PMIC_QI_VSRMCA7_DLC_N_SHIFT 12
#define PMIC_VSRMCA7_DLC_N_SLEEP_MASK 0x3
#define PMIC_VSRMCA7_DLC_N_SLEEP_SHIFT 8
#define PMIC_VSRMCA7_DLC_N_ON_MASK 0x3
#define PMIC_VSRMCA7_DLC_N_ON_SHIFT 4
#define PMIC_VSRMCA7_DLC_N_MASK 0x3
#define PMIC_VSRMCA7_DLC_N_SHIFT 0
#define PMIC_QI_VSRMCA7_BURSTH_MASK 0x3
#define PMIC_QI_VSRMCA7_BURSTH_SHIFT 12
#define PMIC_QI_VSRMCA7_BURSTL_MASK 0x3
#define PMIC_QI_VSRMCA7_BURSTL_SHIFT 12
#define PMIC_NI_VSRMCA7_VSLEEP_SEL_MASK 0x1
#define PMIC_NI_VSRMCA7_VSLEEP_SEL_SHIFT 15
#define PMIC_NI_VSRMCA7_R2R_PDN_MASK 0x1
#define PMIC_NI_VSRMCA7_R2R_PDN_SHIFT 14
#define PMIC_VSRMCA7_VSLEEP_SEL_MASK 0x1
#define PMIC_VSRMCA7_VSLEEP_SEL_SHIFT 11
#define PMIC_VSRMCA7_R2R_PDN_MASK 0x1
#define PMIC_VSRMCA7_R2R_PDN_SHIFT 10
#define PMIC_VSRMCA7_VSLEEP_EN_MASK 0x1
#define PMIC_VSRMCA7_VSLEEP_EN_SHIFT 8
#define PMIC_NI_VSRMCA7_VOSEL_TRANS_MASK 0x1
#define PMIC_NI_VSRMCA7_VOSEL_TRANS_SHIFT 7
#define PMIC_VSRMCA7_VOSEL_TRANS_ONCE_MASK 0x1
#define PMIC_VSRMCA7_VOSEL_TRANS_ONCE_SHIFT 6
#define PMIC_VSRMCA7_VOSEL_TRANS_EN_MASK 0x3
#define PMIC_VSRMCA7_VOSEL_TRANS_EN_SHIFT 4
#define PMIC_VSRMCA7_TRANSTD_MASK 0x3
#define PMIC_VSRMCA7_TRANSTD_SHIFT 0
#define PMIC_VSRMCA7_VOSEL_OFFSET_MASK 0x7F
#define PMIC_VSRMCA7_VOSEL_OFFSET_SHIFT 8
#define PMIC_VSRMCA7_VOSEL_DELTA_MASK 0x7F
#define PMIC_VSRMCA7_VOSEL_DELTA_SHIFT 0
#define PMIC_VSRMCA7_VOSEL_ON_HB_MASK 0x7F
#define PMIC_VSRMCA7_VOSEL_ON_HB_SHIFT 8
#define PMIC_VSRMCA7_VOSEL_ON_LB_MASK 0x7F
#define PMIC_VSRMCA7_VOSEL_ON_LB_SHIFT 0
#define PMIC_VSRMCA7_VOSEL_SLEEP_LB_MASK 0x7F
#define PMIC_VSRMCA7_VOSEL_SLEEP_LB_SHIFT 0
#define PMIC_RG_VDRM_ZXOS_TRIM_MASK 0x3F
#define PMIC_RG_VDRM_ZXOS_TRIM_SHIFT 0
#define PMIC_RG_VDRM_ZX_OS_MASK 0x3
#define PMIC_RG_VDRM_ZX_OS_SHIFT 14
#define PMIC_RG_VDRM_CSL_MASK 0x3
#define PMIC_RG_VDRM_CSL_SHIFT 8
#define PMIC_RG_VDRM_CSR_MASK 0x3
#define PMIC_RG_VDRM_CSR_SHIFT 6
#define PMIC_RG_VDRM_CC_MASK 0x3
#define PMIC_RG_VDRM_CC_SHIFT 4
#define PMIC_RG_VDRM_RZSEL_MASK 0x3
#define PMIC_RG_VDRM_RZSEL_SHIFT 0
#define PMIC_RG_VDRM_NDIS_EN_MASK 0x1
#define PMIC_RG_VDRM_NDIS_EN_SHIFT 9
#define PMIC_RG_VDRM_MODESET_MASK 0x1
#define PMIC_RG_VDRM_MODESET_SHIFT 8
#define PMIC_RG_VDRM_CSM_MASK 0x7
#define PMIC_RG_VDRM_CSM_SHIFT 4
#define PMIC_RG_VDRM_AVP_EN_MASK 0x1
#define PMIC_RG_VDRM_AVP_EN_SHIFT 3
#define PMIC_RG_VDRM_AVP_OS_MASK 0x7
#define PMIC_RG_VDRM_AVP_OS_SHIFT 0
#define PMIC_RG_VDRM_SLP_MASK 0x3
#define PMIC_RG_VDRM_SLP_SHIFT 0
#define PMIC_RG_VDRM_RSV_MASK 0xFF
#define PMIC_RG_VDRM_RSV_SHIFT 0
#define PMIC_VDRM_BURST_CTRL_MASK 0x1
#define PMIC_VDRM_BURST_CTRL_SHIFT 3
#define PMIC_VDRM_DLC_CTRL_MASK 0x1
#define PMIC_VDRM_DLC_CTRL_SHIFT 2
#define PMIC_VDRM_VOSEL_CTRL_MASK 0x1
#define PMIC_VDRM_VOSEL_CTRL_SHIFT 1
#define PMIC_VDRM_EN_CTRL_MASK 0x1
#define PMIC_VDRM_EN_CTRL_SHIFT 0
#define PMIC_VDRM_BURST_SEL_MASK 0x3
#define PMIC_VDRM_BURST_SEL_SHIFT 12
#define PMIC_VDRM_DLC_SEL_MASK 0x3
#define PMIC_VDRM_DLC_SEL_SHIFT 8
#define PMIC_VDRM_VOSEL_SEL_MASK 0x3
#define PMIC_VDRM_VOSEL_SEL_SHIFT 4
#define PMIC_VDRM_EN_SEL_MASK 0x3
#define PMIC_VDRM_EN_SEL_SHIFT 0
#define PMIC_QI_VDRM_OC_STATUS_MASK 0x1
#define PMIC_QI_VDRM_OC_STATUS_SHIFT 15
#define PMIC_QI_VDRM_MODE_MASK 0x1
#define PMIC_QI_VDRM_MODE_SHIFT 14
#define PMIC_QI_VDRM_EN_MASK 0x1
#define PMIC_QI_VDRM_EN_SHIFT 13
#define PMIC_QI_VDRM_STB_MASK 0x1
#define PMIC_QI_VDRM_STB_SHIFT 12
#define PMIC_VDRM_EN_MASK 0x1
#define PMIC_VDRM_EN_SHIFT 0
#define PMIC_VDRM_SFCHG_REN_MASK 0x1
#define PMIC_VDRM_SFCHG_REN_SHIFT 15
#define PMIC_VDRM_SFCHG_RRATE_MASK 0x7F
#define PMIC_VDRM_SFCHG_RRATE_SHIFT 8
#define PMIC_VDRM_SFCHG_FEN_MASK 0x1
#define PMIC_VDRM_SFCHG_FEN_SHIFT 7
#define PMIC_VDRM_SFCHG_FRATE_MASK 0x7F
#define PMIC_VDRM_SFCHG_FRATE_SHIFT 0
#define PMIC_VDRM_VOSEL_MASK 0x7F
#define PMIC_VDRM_VOSEL_SHIFT 0
#define PMIC_VDRM_VOSEL_ON_MASK 0x7F
#define PMIC_VDRM_VOSEL_ON_SHIFT 0
#define PMIC_VDRM_VOSEL_SLEEP_MASK 0x7F
#define PMIC_VDRM_VOSEL_SLEEP_SHIFT 0
#define PMIC_NI_VDRM_VOSEL_MASK 0x7F
#define PMIC_NI_VDRM_VOSEL_SHIFT 0
#define PMIC_QI_VDRM_BURST_MASK 0x3
#define PMIC_QI_VDRM_BURST_SHIFT 12
#define PMIC_VDRM_BURST_SLEEP_MASK 0x3
#define PMIC_VDRM_BURST_SLEEP_SHIFT 8
#define PMIC_VDRM_BURST_ON_MASK 0x3
#define PMIC_VDRM_BURST_ON_SHIFT 4
#define PMIC_VDRM_BURST_MASK 0x3
#define PMIC_VDRM_BURST_SHIFT 0
#define PMIC_QI_VDRM_DLC_MASK 0x3
#define PMIC_QI_VDRM_DLC_SHIFT 12
#define PMIC_VDRM_DLC_SLEEP_MASK 0x3
#define PMIC_VDRM_DLC_SLEEP_SHIFT 8
#define PMIC_VDRM_DLC_ON_MASK 0x3
#define PMIC_VDRM_DLC_ON_SHIFT 4
#define PMIC_VDRM_DLC_MASK 0x3
#define PMIC_VDRM_DLC_SHIFT 0
#define PMIC_QI_VDRM_DLC_N_MASK 0x3
#define PMIC_QI_VDRM_DLC_N_SHIFT 12
#define PMIC_VDRM_DLC_N_SLEEP_MASK 0x3
#define PMIC_VDRM_DLC_N_SLEEP_SHIFT 8
#define PMIC_VDRM_DLC_N_ON_MASK 0x3
#define PMIC_VDRM_DLC_N_ON_SHIFT 4
#define PMIC_VDRM_DLC_N_MASK 0x3
#define PMIC_VDRM_DLC_N_SHIFT 0
#define PMIC_QI_VDRM_BURSTH_MASK 0x3
#define PMIC_QI_VDRM_BURSTH_SHIFT 12
#define PMIC_QI_VDRM_BURSTL_MASK 0x3
#define PMIC_QI_VDRM_BURSTL_SHIFT 12
#define PMIC_NI_VDRM_VSLEEP_SEL_MASK 0x1
#define PMIC_NI_VDRM_VSLEEP_SEL_SHIFT 15
#define PMIC_NI_VDRM_R2R_PDN_MASK 0x1
#define PMIC_NI_VDRM_R2R_PDN_SHIFT 14
#define PMIC_VDRM_VSLEEP_SEL_MASK 0x1
#define PMIC_VDRM_VSLEEP_SEL_SHIFT 11
#define PMIC_VDRM_R2R_PDN_MASK 0x1
#define PMIC_VDRM_R2R_PDN_SHIFT 10
#define PMIC_VDRM_VSLEEP_EN_MASK 0x1
#define PMIC_VDRM_VSLEEP_EN_SHIFT 8
#define PMIC_NI_VDRM_VOSEL_TRANS_MASK 0x1
#define PMIC_NI_VDRM_VOSEL_TRANS_SHIFT 7
#define PMIC_VDRM_VOSEL_TRANS_ONCE_MASK 0x1
#define PMIC_VDRM_VOSEL_TRANS_ONCE_SHIFT 6
#define PMIC_VDRM_VOSEL_TRANS_EN_MASK 0x3
#define PMIC_VDRM_VOSEL_TRANS_EN_SHIFT 4
#define PMIC_VDRM_TRANSTD_MASK 0x3
#define PMIC_VDRM_TRANSTD_SHIFT 0
#define PMIC_K_CONTROL_SMPS_MASK 0x1F
#define PMIC_K_CONTROL_SMPS_SHIFT 8
#define PMIC_K_AUTO_EN_MASK 0x1
#define PMIC_K_AUTO_EN_SHIFT 6
#define PMIC_K_SRC_SEL_MASK 0x1
#define PMIC_K_SRC_SEL_SHIFT 5
#define PMIC_K_START_MANUAL_MASK 0x1
#define PMIC_K_START_MANUAL_SHIFT 4
#define PMIC_K_ONCE_MASK 0x1
#define PMIC_K_ONCE_SHIFT 3
#define PMIC_K_ONCE_EN_MASK 0x1
#define PMIC_K_ONCE_EN_SHIFT 2
#define PMIC_K_MAP_SEL_MASK 0x1
#define PMIC_K_MAP_SEL_SHIFT 1
#define PMIC_K_RST_DONE_MASK 0x1
#define PMIC_K_RST_DONE_SHIFT 0
#define PMIC_QI_SMPS_OSC_CAL_MASK 0x1F
#define PMIC_QI_SMPS_OSC_CAL_SHIFT 8
#define PMIC_K_CONTROL_MASK 0x1F
#define PMIC_K_CONTROL_SHIFT 3
#define PMIC_K_DONE_MASK 0x1
#define PMIC_K_DONE_SHIFT 1
#define PMIC_K_RESULT_MASK 0x1
#define PMIC_K_RESULT_SHIFT 0
#define PMIC_QI_VTCXO_EN_MASK 0x1
#define PMIC_QI_VTCXO_EN_SHIFT 15
#define PMIC_VTCXO_SRCLK_EN_SEL_MASK 0x3
#define PMIC_VTCXO_SRCLK_EN_SEL_SHIFT 13
#define PMIC_VTCXO_ON_CTRL_MASK 0x1
#define PMIC_VTCXO_ON_CTRL_SHIFT 11
#define PMIC_RG_VTCXO_EN_MASK 0x1
#define PMIC_RG_VTCXO_EN_SHIFT 10
#define PMIC_RG_VTCXO_STBTD_MASK 0x3
#define PMIC_RG_VTCXO_STBTD_SHIFT 8
#define PMIC_QI_VTCXO_MODE_MASK 0x1
#define PMIC_QI_VTCXO_MODE_SHIFT 7
#define PMIC_VTCXO_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VTCXO_SRCLK_MODE_SEL_SHIFT 5
#define PMIC_VTCXOTD_SEL_MASK 0x3
#define PMIC_VTCXOTD_SEL_SHIFT 3
#define PMIC_RG_VTCXO_OCFB_EN_MASK 0x1
#define PMIC_RG_VTCXO_OCFB_EN_SHIFT 2
#define PMIC_VTCXO_LP_SET_MASK 0x1
#define PMIC_VTCXO_LP_SET_SHIFT 1
#define PMIC_VTCXO_LP_SEL_MASK 0x1
#define PMIC_VTCXO_LP_SEL_SHIFT 0
#define PMIC_QI_VA28_EN_MASK 0x1
#define PMIC_QI_VA28_EN_SHIFT 15
#define PMIC_RG_VA28_EN_MASK 0x1
#define PMIC_RG_VA28_EN_SHIFT 14
#define PMIC_RG_VA28_STBTD_MASK 0x3
#define PMIC_RG_VA28_STBTD_SHIFT 12
#define PMIC_QI_VA28_MODE_MASK 0x1
#define PMIC_QI_VA28_MODE_SHIFT 7
#define PMIC_VA28_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VA28_SRCLK_MODE_SEL_SHIFT 4
#define PMIC_VA28_LP_SET_MASK 0x1
#define PMIC_VA28_LP_SET_SHIFT 1
#define PMIC_VA28_LP_SEL_MASK 0x1
#define PMIC_VA28_LP_SEL_SHIFT 0
#define PMIC_RG_VCAMA_EN_MASK 0x1
#define PMIC_RG_VCAMA_EN_SHIFT 15
#define PMIC_RG_VCAMA_STBTD_MASK 0x3
#define PMIC_RG_VCAMA_STBTD_SHIFT 12
#define PMIC_RG_VCAMA_OCFB_EN_MASK 0x1
#define PMIC_RG_VCAMA_OCFB_EN_SHIFT 2
#define PMIC_QI_VTCXO_OC_STATUS_MASK 0x1
#define PMIC_QI_VTCXO_OC_STATUS_SHIFT 3
#define PMIC_QI_VA28_OC_STATUS_MASK 0x1
#define PMIC_QI_VA28_OC_STATUS_SHIFT 2
#define PMIC_QI_VCAMA_OC_STATUS_MASK 0x1
#define PMIC_QI_VCAMA_OC_STATUS_SHIFT 1
#define PMIC_RG_VA28_BIST_EN_MASK 0x1
#define PMIC_RG_VA28_BIST_EN_SHIFT 0
#define PMIC_RG_VTCXO_CAL_MASK 0xF
#define PMIC_RG_VTCXO_CAL_SHIFT 8
#define PMIC_RG_VTCXO_NDIS_EN_MASK 0x1
#define PMIC_RG_VTCXO_NDIS_EN_SHIFT 4
#define PMIC_RG_VA28_CAL_MASK 0xF
#define PMIC_RG_VA28_CAL_SHIFT 8
#define PMIC_RG_VA28_OCFB_EN_MASK 0x1
#define PMIC_RG_VA28_OCFB_EN_SHIFT 6
#define PMIC_RG_VA28_NDIS_EN_MASK 0x1
#define PMIC_RG_VA28_NDIS_EN_SHIFT 4
#define PMIC_RG_VCAMA_CAL_MASK 0xF
#define PMIC_RG_VCAMA_CAL_SHIFT 8
#define PMIC_RG_VCAMA_VOSEL_MASK 0x3
#define PMIC_RG_VCAMA_VOSEL_SHIFT 6
#define PMIC_RG_VCAMA_NDIS_EN_MASK 0x1
#define PMIC_RG_VCAMA_NDIS_EN_SHIFT 4
#define PMIC_RG_VCAMA_FBSEL_MASK 0x3
#define PMIC_RG_VCAMA_FBSEL_SHIFT 0
#define PMIC_RG_ALDO_RESERVE_1_MASK 0x1
#define PMIC_RG_ALDO_RESERVE_1_SHIFT 15
#define PMIC_RG_ALDO_RESERVE_2_MASK 0x1
#define PMIC_RG_ALDO_RESERVE_2_SHIFT 13
#define PMIC_ANALDO_RSV0_MASK 0xF
#define PMIC_ANALDO_RSV0_SHIFT 8
#define PMIC_ANALDO_RSV1_MASK 0xFF
#define PMIC_ANALDO_RSV1_SHIFT 0
#define PMIC_QI_VIO28_EN_MASK 0x1
#define PMIC_QI_VIO28_EN_SHIFT 15
#define PMIC_VIO28_EN_MASK 0x1
#define PMIC_VIO28_EN_SHIFT 14
#define PMIC_RG_VIO28_STBTD_MASK 0x3
#define PMIC_RG_VIO28_STBTD_SHIFT 12
#define PMIC_QI_VIO28_MODE_MASK 0x1
#define PMIC_QI_VIO28_MODE_SHIFT 7
#define PMIC_VIO28_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VIO28_SRCLK_MODE_SEL_SHIFT 4
#define PMIC_RG_VIO28_OCFB_EN_MASK 0x1
#define PMIC_RG_VIO28_OCFB_EN_SHIFT 2
#define PMIC_VIO28_LP_MODE_SET_MASK 0x1
#define PMIC_VIO28_LP_MODE_SET_SHIFT 1
#define PMIC_VIO28_LP_SEL_MASK 0x1
#define PMIC_VIO28_LP_SEL_SHIFT 0
#define PMIC_QI_VUSB_EN_MASK 0x1
#define PMIC_QI_VUSB_EN_SHIFT 15
#define PMIC_RG_VUSB_EN_MASK 0x1
#define PMIC_RG_VUSB_EN_SHIFT 14
#define PMIC_RG_VUSB_STBTD_MASK 0x3
#define PMIC_RG_VUSB_STBTD_SHIFT 12
#define PMIC_QI_VUSB_MODE_MASK 0x1
#define PMIC_QI_VUSB_MODE_SHIFT 7
#define PMIC_VUSB_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VUSB_SRCLK_MODE_SEL_SHIFT 4
#define PMIC_RG_VUSB_OCFB_EN_MASK 0x1
#define PMIC_RG_VUSB_OCFB_EN_SHIFT 2
#define PMIC_VUSB_LP_MODE_SET_MASK 0x1
#define PMIC_VUSB_LP_MODE_SET_SHIFT 1
#define PMIC_VUSB_LP_SEL_MASK 0x1
#define PMIC_VUSB_LP_SEL_SHIFT 0
#define PMIC_QI_VMC_EN_MASK 0x1
#define PMIC_QI_VMC_EN_SHIFT 15
#define PMIC_RG_VMC_INT_DIS_SEL_MASK 0x3
#define PMIC_RG_VMC_INT_DIS_SEL_SHIFT 13
#define PMIC_RG_VMC_EN_MASK 0x1
#define PMIC_RG_VMC_EN_SHIFT 12
#define PMIC_RG_VMC_STBTD_MASK 0x3
#define PMIC_RG_VMC_STBTD_SHIFT 8
#define PMIC_QI_VMC_MODE_MASK 0x1
#define PMIC_QI_VMC_MODE_SHIFT 7
#define PMIC_VMC_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VMC_SRCLK_MODE_SEL_SHIFT 4
#define PMIC_RG_VMC_OCFB_EN_MASK 0x1
#define PMIC_RG_VMC_OCFB_EN_SHIFT 2
#define PMIC_VMC_LP_MODE_SET_MASK 0x1
#define PMIC_VMC_LP_MODE_SET_SHIFT 1
#define PMIC_VMC_LP_SEL_MASK 0x1
#define PMIC_VMC_LP_SEL_SHIFT 0
#define PMIC_QI_VMCH_EN_MASK 0x1
#define PMIC_QI_VMCH_EN_SHIFT 15
#define PMIC_RG_VMCH_EN_MASK 0x1
#define PMIC_RG_VMCH_EN_SHIFT 14
#define PMIC_RG_VMCH_STBTD_MASK 0x3
#define PMIC_RG_VMCH_STBTD_SHIFT 12
#define PMIC_QI_VMCH_MODE_MASK 0x1
#define PMIC_QI_VMCH_MODE_SHIFT 7
#define PMIC_VMCH_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VMCH_SRCLK_MODE_SEL_SHIFT 4
#define PMIC_VMCH_LP_MODE_SET_MASK 0x1
#define PMIC_VMCH_LP_MODE_SET_SHIFT 1
#define PMIC_VMCH_LP_SEL_MASK 0x1
#define PMIC_VMCH_LP_SEL_SHIFT 0
#define PMIC_QI_VEMC_3V3_EN_MASK 0x1
#define PMIC_QI_VEMC_3V3_EN_SHIFT 15
#define PMIC_RG_VEMC_3V3_EN_MASK 0x1
#define PMIC_RG_VEMC_3V3_EN_SHIFT 14
#define PMIC_RG_VEMC_3V3_STBTD_MASK 0x3
#define PMIC_RG_VEMC_3V3_STBTD_SHIFT 12
#define PMIC_QI_VEMC_3V3_MODE_MASK 0x1
#define PMIC_QI_VEMC_3V3_MODE_SHIFT 7
#define PMIC_VEMC_3V3_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VEMC_3V3_SRCLK_MODE_SEL_SHIFT 4
#define PMIC_RG_VEMC_3V3_OCFB_EN_MASK 0x1
#define PMIC_RG_VEMC_3V3_OCFB_EN_SHIFT 2
#define PMIC_VEMC_3V3_LP_MODE_SET_MASK 0x1
#define PMIC_VEMC_3V3_LP_MODE_SET_SHIFT 1
#define PMIC_VEMC_3V3_LP_SEL_MASK 0x1
#define PMIC_VEMC_3V3_LP_SEL_SHIFT 0
#define PMIC_RG_VCAMD_SW_EN_MASK 0x1
#define PMIC_RG_VCAMD_SW_EN_SHIFT 15
#define PMIC_RG_VCAMD_STBTD_MASK 0x3
#define PMIC_RG_VCAMD_STBTD_SHIFT 12
#define PMIC_QI_VCAMD_MODE_MASK 0x1
#define PMIC_QI_VCAMD_MODE_SHIFT 7
#define PMIC_VCAMD_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VCAMD_SRCLK_MODE_SEL_SHIFT 5
#define PMIC_RG_VCAMD_OCFB_EN_MASK 0x1
#define PMIC_RG_VCAMD_OCFB_EN_SHIFT 2
#define PMIC_VCAMD_LP_MODE_SET_MASK 0x1
#define PMIC_VCAMD_LP_MODE_SET_SHIFT 1
#define PMIC_VCAMD_LP_SEL_MASK 0x1
#define PMIC_VCAMD_LP_SEL_SHIFT 0
#define PMIC_RG_VCAMIO_SW_EN_MASK 0x1
#define PMIC_RG_VCAMIO_SW_EN_SHIFT 15
#define PMIC_RG_VCAMIO_STBTD_MASK 0x3
#define PMIC_RG_VCAMIO_STBTD_SHIFT 12
#define PMIC_QI_VCAMIO_MODE_MASK 0x1
#define PMIC_QI_VCAMIO_MODE_SHIFT 7
#define PMIC_VCAMIO_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VCAMIO_SRCLK_MODE_SEL_SHIFT 5
#define PMIC_RG_VCAMIO_OCFB_EN_MASK 0x1
#define PMIC_RG_VCAMIO_OCFB_EN_SHIFT 2
#define PMIC_VCAMIO_LP_MODE_SET_MASK 0x1
#define PMIC_VCAMIO_LP_MODE_SET_SHIFT 1
#define PMIC_VCAMIO_LP_SEL_MASK 0x1
#define PMIC_VCAMIO_LP_SEL_SHIFT 0
#define PMIC_RG_VCAMAF_SW_EN_MASK 0x1
#define PMIC_RG_VCAMAF_SW_EN_SHIFT 15
#define PMIC_RG_VCAMAF_STBTD_MASK 0x3
#define PMIC_RG_VCAMAF_STBTD_SHIFT 12
#define PMIC_QI_VCAMAF_MODE_MASK 0x1
#define PMIC_QI_VCAMAF_MODE_SHIFT 7
#define PMIC_VCAMAF_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VCAMAF_SRCLK_MODE_SEL_SHIFT 5
#define PMIC_RG_VCAMAF_OCFB_EN_MASK 0x1
#define PMIC_RG_VCAMAF_OCFB_EN_SHIFT 2
#define PMIC_VCAMAF_LP_MODE_SET_MASK 0x1
#define PMIC_VCAMAF_LP_MODE_SET_SHIFT 1
#define PMIC_VCAMAF_LP_SEL_MASK 0x1
#define PMIC_VCAMAF_LP_SEL_SHIFT 0
#define PMIC_RG_VGP4_SW_EN_MASK 0x1
#define PMIC_RG_VGP4_SW_EN_SHIFT 15
#define PMIC_RG_VGP4_STBTD_MASK 0x3
#define PMIC_RG_VGP4_STBTD_SHIFT 12
#define PMIC_QI_VGP4_MODE_MASK 0x1
#define PMIC_QI_VGP4_MODE_SHIFT 7
#define PMIC_VGP4_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VGP4_SRCLK_MODE_SEL_SHIFT 5
#define PMIC_RG_VGP4_OCFB_EN_MASK 0x1
#define PMIC_RG_VGP4_OCFB_EN_SHIFT 2
#define PMIC_VGP4_LP_MODE_SET_MASK 0x1
#define PMIC_VGP4_LP_MODE_SET_SHIFT 1
#define PMIC_VGP4_LP_SEL_MASK 0x1
#define PMIC_VGP4_LP_SEL_SHIFT 0
#define PMIC_RG_VGP5_SW_EN_MASK 0x1
#define PMIC_RG_VGP5_SW_EN_SHIFT 15
#define PMIC_RG_VGP5_STBTD_MASK 0x3
#define PMIC_RG_VGP5_STBTD_SHIFT 12
#define PMIC_QI_VGP5_MODE_MASK 0x1
#define PMIC_QI_VGP5_MODE_SHIFT 7
#define PMIC_VGP5_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VGP5_SRCLK_MODE_SEL_SHIFT 5
#define PMIC_RG_VGP5_OCFB_EN_MASK 0x1
#define PMIC_RG_VGP5_OCFB_EN_SHIFT 2
#define PMIC_VGP5_LP_MODE_SET_MASK 0x1
#define PMIC_VGP5_LP_MODE_SET_SHIFT 1
#define PMIC_VGP5_LP_SEL_MASK 0x1
#define PMIC_VGP5_LP_SEL_SHIFT 0
#define PMIC_RG_VGP6_SW_EN_MASK 0x1
#define PMIC_RG_VGP6_SW_EN_SHIFT 15
#define PMIC_RG_VGP6_STBTD_MASK 0x3
#define PMIC_RG_VGP6_STBTD_SHIFT 12
#define PMIC_QI_VGP6_MODE_MASK 0x1
#define PMIC_QI_VGP6_MODE_SHIFT 7
#define PMIC_VGP6_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VGP6_SRCLK_MODE_SEL_SHIFT 5
#define PMIC_RG_VGP6_OCFB_EN_MASK 0x1
#define PMIC_RG_VGP6_OCFB_EN_SHIFT 2
#define PMIC_VGP6_LP_MODE_SET_MASK 0x1
#define PMIC_VGP6_LP_MODE_SET_SHIFT 1
#define PMIC_VGP6_LP_SEL_MASK 0x1
#define PMIC_VGP6_LP_SEL_SHIFT 0
#define PMIC_RG_VIBR_MID_STATE_MASK 0x3
#define PMIC_RG_VIBR_MID_STATE_SHIFT 14
#define PMIC_RG_VIBR_MST_TIME_MASK 0x3
#define PMIC_RG_VIBR_MST_TIME_SHIFT 6
#define PMIC_RG_VIBR_SW_MODE_MASK 0x1
#define PMIC_RG_VIBR_SW_MODE_SHIFT 5
#define PMIC_RG_VIBR_FR_ORI_MASK 0x3
#define PMIC_RG_VIBR_FR_ORI_SHIFT 3
#define PMIC_QI_VRTC_EN_MASK 0x1
#define PMIC_QI_VRTC_EN_SHIFT 15
#define PMIC_VRTC_EN_MASK 0x1
#define PMIC_VRTC_EN_SHIFT 8
#define PMIC_RG_VIO28_BIST_EN_MASK 0x1
#define PMIC_RG_VIO28_BIST_EN_SHIFT 15
#define PMIC_RG_VMCH_BIST_EN_MASK 0x1
#define PMIC_RG_VMCH_BIST_EN_SHIFT 14
#define PMIC_RG_VRTC_BIST_EN_MASK 0x1
#define PMIC_RG_VRTC_BIST_EN_SHIFT 13
#define PMIC_QI_VIO28_OC_STATUS_MASK 0x1
#define PMIC_QI_VIO28_OC_STATUS_SHIFT 15
#define PMIC_QI_VUSB_OC_STATUS_MASK 0x1
#define PMIC_QI_VUSB_OC_STATUS_SHIFT 14
#define PMIC_QI_VMC_OC_STATUS_MASK 0x1
#define PMIC_QI_VMC_OC_STATUS_SHIFT 13
#define PMIC_QI_VMCH_OC_STATUS_MASK 0x1
#define PMIC_QI_VMCH_OC_STATUS_SHIFT 12
#define PMIC_QI_VEMC_3V3_OC_STATUS_MASK 0x1
#define PMIC_QI_VEMC_3V3_OC_STATUS_SHIFT 11
#define PMIC_QI_VCAMD_OC_STATUS_MASK 0x1
#define PMIC_QI_VCAMD_OC_STATUS_SHIFT 10
#define PMIC_QI_VCAMIO_OC_STATUS_MASK 0x1
#define PMIC_QI_VCAMIO_OC_STATUS_SHIFT 9
#define PMIC_QI_VCAMAF_OC_STATUS_MASK 0x1
#define PMIC_QI_VCAMAF_OC_STATUS_SHIFT 8
#define PMIC_QI_VGP4_OC_STATUS_MASK 0x1
#define PMIC_QI_VGP4_OC_STATUS_SHIFT 7
#define PMIC_QI_VGP5_OC_STATUS_MASK 0x1
#define PMIC_QI_VGP5_OC_STATUS_SHIFT 6
#define PMIC_QI_VGP6_OC_STATUS_MASK 0x1
#define PMIC_QI_VGP6_OC_STATUS_SHIFT 5
#define PMIC_QI_VIBR_OC_STATUS_MASK 0x1
#define PMIC_QI_VIBR_OC_STATUS_SHIFT 4
#define PMIC_RG_VIO28_CAL_MASK 0xF
#define PMIC_RG_VIO28_CAL_SHIFT 8
#define PMIC_RG_VIO28_NDIS_EN_MASK 0x1
#define PMIC_RG_VIO28_NDIS_EN_SHIFT 4
#define PMIC_RG_VUSB_CAL_MASK 0xF
#define PMIC_RG_VUSB_CAL_SHIFT 8
#define PMIC_RG_VUSB_STB_SEL_MASK 0x1
#define PMIC_RG_VUSB_STB_SEL_SHIFT 5
#define PMIC_RG_VUSB_NDIS_EN_MASK 0x1
#define PMIC_RG_VUSB_NDIS_EN_SHIFT 4
#define PMIC_RG_VMCH_CAL_MASK 0xF
#define PMIC_RG_VMCH_CAL_SHIFT 8
#define PMIC_RG_VMCH_VOSEL_MASK 0x1
#define PMIC_RG_VMCH_VOSEL_SHIFT 7
#define PMIC_RG_VMCH_STB_SEL_MASK 0x1
#define PMIC_RG_VMCH_STB_SEL_SHIFT 6
#define PMIC_RG_VMCH_DB_EN_MASK 0x1
#define PMIC_RG_VMCH_DB_EN_SHIFT 4
#define PMIC_RG_VMCH_OCFB_MASK 0x1
#define PMIC_RG_VMCH_OCFB_SHIFT 2
#define PMIC_RG_VMCH_NDIS_EN_MASK 0x1
#define PMIC_RG_VMCH_NDIS_EN_SHIFT 0
#define PMIC_RG_VEMC_3V3_CAL_MASK 0xF
#define PMIC_RG_VEMC_3V3_CAL_SHIFT 5
#define PMIC_RG_VEMC_3V3_VOSEL_MASK 0x1
#define PMIC_RG_VEMC_3V3_VOSEL_SHIFT 4
#define PMIC_RG_VEMC_3V3_STB_CAL_MASK 0x3
#define PMIC_RG_VEMC_3V3_STB_CAL_SHIFT 2
#define PMIC_RG_VEMC_3V3_DL_EN_MASK 0x1
#define PMIC_RG_VEMC_3V3_DL_EN_SHIFT 1
#define PMIC_RG_VEMC_3V3_NDIS_EN_MASK 0x1
#define PMIC_RG_VEMC_3V3_NDIS_EN_SHIFT 0
#define PMIC_RG_VCAMD_CAL_MASK 0xF
#define PMIC_RG_VCAMD_CAL_SHIFT 8
#define PMIC_RG_VCAMD_VOSEL_MASK 0x7
#define PMIC_RG_VCAMD_VOSEL_SHIFT 5
#define PMIC_RG_VCAMD_STB_SEL_MASK 0x1
#define PMIC_RG_VCAMD_STB_SEL_SHIFT 4
#define PMIC_RG_VCAMD_NDIS_EN_MASK 0x1
#define PMIC_RG_VCAMD_NDIS_EN_SHIFT 0
#define PMIC_RG_VCAMIO_CAL_MASK 0xF
#define PMIC_RG_VCAMIO_CAL_SHIFT 8
#define PMIC_RG_VCAMIO_VOSEL_MASK 0x7
#define PMIC_RG_VCAMIO_VOSEL_SHIFT 5
#define PMIC_RG_VCAMIO_STB_SEL_MASK 0x1
#define PMIC_RG_VCAMIO_STB_SEL_SHIFT 4
#define PMIC_RG_VCAMIO_NDIS_EN_MASK 0x1
#define PMIC_RG_VCAMIO_NDIS_EN_SHIFT 0
#define PMIC_RG_VCAMAF_CAL_MASK 0xF
#define PMIC_RG_VCAMAF_CAL_SHIFT 8
#define PMIC_RG_VCAMAF_VOSEL_MASK 0x7
#define PMIC_RG_VCAMAF_VOSEL_SHIFT 5
#define PMIC_RG_VCAMAF_STB_SEL_MASK 0x1
#define PMIC_RG_VCAMAF_STB_SEL_SHIFT 4
#define PMIC_RG_VCAMAF_NDIS_EN_MASK 0x1
#define PMIC_RG_VCAMAF_NDIS_EN_SHIFT 0
#define PMIC_RG_VGP4_CAL_MASK 0xF
#define PMIC_RG_VGP4_CAL_SHIFT 8
#define PMIC_RG_VGP4_VOSEL_MASK 0x7
#define PMIC_RG_VGP4_VOSEL_SHIFT 5
#define PMIC_RG_VGP4_STB_SEL_MASK 0x1
#define PMIC_RG_VGP4_STB_SEL_SHIFT 4
#define PMIC_RG_VGP4_NDIS_EN_MASK 0x1
#define PMIC_RG_VGP4_NDIS_EN_SHIFT 0
#define PMIC_RG_VGP5_CAL_MASK 0xF
#define PMIC_RG_VGP5_CAL_SHIFT 8
#define PMIC_RG_VGP5_VOSEL_MASK 0x7
#define PMIC_RG_VGP5_VOSEL_SHIFT 5
#define PMIC_RG_VGP5_STB_SEL_MASK 0x1
#define PMIC_RG_VGP5_STB_SEL_SHIFT 4
#define PMIC_RG_VGP5_NDIS_EN_INT_MASK 0x1
#define PMIC_RG_VGP5_NDIS_EN_INT_SHIFT 3
#define PMIC_RG_VGP5_NDIS_EN_MASK 0x1
#define PMIC_RG_VGP5_NDIS_EN_SHIFT 0
#define PMIC_RG_VIBR_EN_MASK 0x1
#define PMIC_RG_VIBR_EN_SHIFT 15
#define PMIC_RG_VIBR_STBTD_MASK 0x3
#define PMIC_RG_VIBR_STBTD_SHIFT 12
#define PMIC_QI_VIBR_MODE_MASK 0x1
#define PMIC_QI_VIBR_MODE_SHIFT 7
#define PMIC_VIBR_SRCLK_MODE_SEL_MASK 0x3
#define PMIC_VIBR_SRCLK_MODE_SEL_SHIFT 5
#define PMIC_VIBR_THER_SHEN_EN_MASK 0x1
#define PMIC_VIBR_THER_SHEN_EN_SHIFT 2
#define PMIC_VIBR_LP_MODE_SET_MASK 0x1
#define PMIC_VIBR_LP_MODE_SET_SHIFT 1
#define PMIC_VIBR_LP_SEL_MASK 0x1
#define PMIC_VIBR_LP_SEL_SHIFT 0
#define PMIC_RG_VIBR_VOCAL_MASK 0xF
#define PMIC_RG_VIBR_VOCAL_SHIFT 12
#define PMIC_RG_VIBR_VOSEL_MASK 0x7
#define PMIC_RG_VIBR_VOSEL_SHIFT 9
#define PMIC_RG_VIBR_PWDB_MASK 0x1
#define PMIC_RG_VIBR_PWDB_SHIFT 6
#define PMIC_RG_VIBR_DRV_SEL_MASK 0x1
#define PMIC_RG_VIBR_DRV_SEL_SHIFT 5
#define PMIC_RG_VIBR_STB_SEL_MASK 0x1
#define PMIC_RG_VIBR_STB_SEL_SHIFT 4
#define PMIC_RG_VIBR_NDIS_EN_MASK 0x1
#define PMIC_RG_VIBR_NDIS_EN_SHIFT 0
#define PMIC_RG_VRTC_CAL_MASK 0xF
#define PMIC_RG_VRTC_CAL_SHIFT 12
#define PMIC_RG_VRTC_NDIS_EN_MASK 0x1
#define PMIC_RG_VRTC_NDIS_EN_SHIFT 0
#define PMIC_RG_LDO_FT_MASK 0x1
#define PMIC_RG_LDO_FT_SHIFT 15
#define PMIC_DIGLDO_RSV0_MASK 0xF
#define PMIC_DIGLDO_RSV0_SHIFT 8
#define PMIC_DIGLDO_RSV1_MASK 0xFF
#define PMIC_DIGLDO_RSV1_SHIFT 0
#define PMIC_VCAMD_SRCLK_EN_SEL_MASK 0x3
#define PMIC_VCAMD_SRCLK_EN_SEL_SHIFT 10
#define PMIC_VCAMIO_SRCLK_EN_SEL_MASK 0x3
#define PMIC_VCAMIO_SRCLK_EN_SEL_SHIFT 8
#define PMIC_VCAMAF_SRCLK_EN_SEL_MASK 0x3
#define PMIC_VCAMAF_SRCLK_EN_SEL_SHIFT 6
#define PMIC_VGP4_SRCLK_EN_SEL_MASK 0x3
#define PMIC_VGP4_SRCLK_EN_SEL_SHIFT 4
#define PMIC_VGP6_SRCLK_EN_SEL_MASK 0x3
#define PMIC_VGP6_SRCLK_EN_SEL_SHIFT 2
#define PMIC_VGP5_SRCLK_EN_SEL_MASK 0x3
#define PMIC_VGP5_SRCLK_EN_SEL_SHIFT 0
#define PMIC_RG_VMC_CAL_MASK 0xF
#define PMIC_RG_VMC_CAL_SHIFT 8
#define PMIC_RG_VMC_STB_CAL_MASK 0x1
#define PMIC_RG_VMC_STB_CAL_SHIFT 6
#define PMIC_RG_VMC_VOSEL_MASK 0x1
#define PMIC_RG_VMC_VOSEL_SHIFT 4
#define PMIC_RG_VMC_NDIS_EN_MASK 0x1
#define PMIC_RG_VMC_NDIS_EN_SHIFT 0
#define PMIC_VCAMD_ON_CTRL_MASK 0x1
#define PMIC_VCAMD_ON_CTRL_SHIFT 15
#define PMIC_VCAMIO_ON_CTRL_MASK 0x1
#define PMIC_VCAMIO_ON_CTRL_SHIFT 14
#define PMIC_VCAMAF_ON_CTRL_MASK 0x1
#define PMIC_VCAMAF_ON_CTRL_SHIFT 13
#define PMIC_VGP4_ON_CTRL_MASK 0x1
#define PMIC_VGP4_ON_CTRL_SHIFT 12
#define PMIC_VGP5_ON_CTRL_MASK 0x1
#define PMIC_VGP5_ON_CTRL_SHIFT 11
#define PMIC_VGP6_ON_CTRL_MASK 0x1
#define PMIC_VGP6_ON_CTRL_SHIFT 10
#define PMIC_VIBR_ON_CTRL_MASK 0x1
#define PMIC_VIBR_ON_CTRL_SHIFT 7
#define PMIC_VIBR_SRCLK_EN_SEL_MASK 0x3
#define PMIC_VIBR_SRCLK_EN_SEL_SHIFT 0
#define PMIC_RG_STB_SEL_MASK 0x1
#define PMIC_RG_STB_SEL_SHIFT 15
#define PMIC_RG_OCFB_TDSEL_MASK 0x3
#define PMIC_RG_OCFB_TDSEL_SHIFT 2
#define PMIC_RG_36US_STBTD_MASK 0x3
#define PMIC_RG_36US_STBTD_SHIFT 0
#define PMIC_RG_RSV_STB_SEL_MASK 0xFFF
#define PMIC_RG_RSV_STB_SEL_SHIFT 4
#define PMIC_RG_RSV_LDO1_MASK 0x3
#define PMIC_RG_RSV_LDO1_SHIFT 2
#define PMIC_RG_RSV_LDO2_MASK 0x3
#define PMIC_RG_RSV_LDO2_SHIFT 0
#define PMIC_RG_VGP6_CAL_MASK 0xF
#define PMIC_RG_VGP6_CAL_SHIFT 8
#define PMIC_RG_VGP6_VOSEL_MASK 0x7
#define PMIC_RG_VGP6_VOSEL_SHIFT 5
#define PMIC_RG_VGP6_STB_SEL_MASK 0x1
#define PMIC_RG_VGP6_STB_SEL_SHIFT 4
#define PMIC_RG_VGP6_NDIS_EN_MASK 0x1
#define PMIC_RG_VGP6_NDIS_EN_SHIFT 0
#define PMIC_RG_THRDET_SEL_MASK 0x1
#define PMIC_RG_THRDET_SEL_SHIFT 6
#define PMIC_THR_HWPDN_EN_MASK 0x1
#define PMIC_THR_HWPDN_EN_SHIFT 5
#define PMIC_RG_STRUP_THR_SEL_MASK 0x3
#define PMIC_RG_STRUP_THR_SEL_SHIFT 3
#define PMIC_RG_THR_TMODE_MASK 0x1
#define PMIC_RG_THR_TMODE_SHIFT 1
#define PMIC_THR_DET_DIS_MASK 0x1
#define PMIC_THR_DET_DIS_SHIFT 0
#define PMIC_RG_VREF_BG_MASK 0x7
#define PMIC_RG_VREF_BG_SHIFT 12
#define PMIC_RG_STRUP_IREF_TRIM_MASK 0x1F
#define PMIC_RG_STRUP_IREF_TRIM_SHIFT 4
#define PMIC_RG_RST_DRVSEL_MASK 0x1
#define PMIC_RG_RST_DRVSEL_SHIFT 3
#define PMIC_RG_EN_DRVSEL_MASK 0x1
#define PMIC_RG_EN_DRVSEL_SHIFT 2
#define PMIC_RG_USBDL_KEYDET_EN_MASK 0x1
#define PMIC_RG_USBDL_KEYDET_EN_SHIFT 1
#define PMIC_RG_USBDL_EN_MASK 0x1
#define PMIC_RG_USBDL_EN_SHIFT 0
#define PMIC_RG_PMU_LEV_UNGATE_MASK 0x1
#define PMIC_RG_PMU_LEV_UNGATE_SHIFT 4
#define PMIC_RG_PMU_RSV_MASK 0xF
#define PMIC_RG_PMU_RSV_SHIFT 0
#define PMIC_PMU_THR_STATUS_MASK 0x7
#define PMIC_PMU_THR_STATUS_SHIFT 8
#define PMIC_PMU_THR_DEB_MASK 0x7
#define PMIC_PMU_THR_DEB_SHIFT 4
#define PMIC_THR_TEST_MASK 0x3
#define PMIC_THR_TEST_SHIFT 0
#define PMIC_STRUP_DIG_IO28_PG_FORCE_MASK 0x1
#define PMIC_STRUP_DIG_IO28_PG_FORCE_SHIFT 15
#define PMIC_STRUP_DIG_IO_PG_FORCE_MASK 0x1
#define PMIC_STRUP_DIG_IO_PG_FORCE_SHIFT 14
#define PMIC_RTC_XOSC32_ENB_SEL_MASK 0x1
#define PMIC_RTC_XOSC32_ENB_SEL_SHIFT 13
#define PMIC_RTC_XOSC32_ENB_SW_MASK 0x1
#define PMIC_RTC_XOSC32_ENB_SW_SHIFT 12
#define PMIC_BIAS_GEN_EN_SEL_MASK 0x1
#define PMIC_BIAS_GEN_EN_SEL_SHIFT 11
#define PMIC_BIAS_GEN_EN_MASK 0x1
#define PMIC_BIAS_GEN_EN_SHIFT 10
#define PMIC_STRUP_PWRON_SEL_MASK 0x1
#define PMIC_STRUP_PWRON_SEL_SHIFT 9
#define PMIC_STRUP_PWRON_MASK 0x1
#define PMIC_STRUP_PWRON_SHIFT 8
#define PMIC_BIAS_GEN_EN_FORCE_MASK 0x1
#define PMIC_BIAS_GEN_EN_FORCE_SHIFT 7
#define PMIC_STRUP_PWRON_FORCE_MASK 0x1
#define PMIC_STRUP_PWRON_FORCE_SHIFT 6
#define PMIC_STRUP_FT_CTRL_MASK 0x3
#define PMIC_STRUP_FT_CTRL_SHIFT 4
#define PMIC_PWRBB_DEB_EN_MASK 0x1
#define PMIC_PWRBB_DEB_EN_SHIFT 1
#define PMIC_DDUVLO_DEB_EN_MASK 0x1
#define PMIC_DDUVLO_DEB_EN_SHIFT 0
#define PMIC_VSRMCA15_PG_ENB_MASK 0x1
#define PMIC_VSRMCA15_PG_ENB_SHIFT 12
#define PMIC_VPCA15_PG_ENB_MASK 0x1
#define PMIC_VPCA15_PG_ENB_SHIFT 11
#define PMIC_VMCH_PG_ENB_MASK 0x1
#define PMIC_VMCH_PG_ENB_SHIFT 10
#define PMIC_VMC_PG_ENB_MASK 0x1
#define PMIC_VMC_PG_ENB_SHIFT 9
#define PMIC_VEMC_PG_ENB_MASK 0x1
#define PMIC_VEMC_PG_ENB_SHIFT 8
#define PMIC_VTCXO_PG_ENB_MASK 0x1
#define PMIC_VTCXO_PG_ENB_SHIFT 7
#define PMIC_VIO28_PG_ENB_MASK 0x1
#define PMIC_VIO28_PG_ENB_SHIFT 6
#define PMIC_VA28_PG_ENB_MASK 0x1
#define PMIC_VA28_PG_ENB_SHIFT 5
#define PMIC_VIO18_PG_ENB_MASK 0x1
#define PMIC_VIO18_PG_ENB_SHIFT 4
#define PMIC_VDRM_PG_ENB_MASK 0x1
#define PMIC_VDRM_PG_ENB_SHIFT 3
#define PMIC_VCORE_PG_ENB_MASK 0x1
#define PMIC_VCORE_PG_ENB_SHIFT 2
#define PMIC_VSRMCA7_PG_ENB_MASK 0x1
#define PMIC_VSRMCA7_PG_ENB_SHIFT 1
#define PMIC_VPCA7_PG_ENB_MASK 0x1
#define PMIC_VPCA7_PG_ENB_SHIFT 0
#define PMIC_QI_OSC_EN_MASK 0x1
#define PMIC_QI_OSC_EN_SHIFT 15
#define PMIC_JUST_PWRKEY_RST_MASK 0x1
#define PMIC_JUST_PWRKEY_RST_SHIFT 14
#define PMIC_VSRMCA15_PG_H2L_EN_MASK 0x1
#define PMIC_VSRMCA15_PG_H2L_EN_SHIFT 12
#define PMIC_VPCA15_PG_H2L_EN_MASK 0x1
#define PMIC_VPCA15_PG_H2L_EN_SHIFT 11
#define PMIC_VCORE_PG_H2L_EN_MASK 0x1
#define PMIC_VCORE_PG_H2L_EN_SHIFT 10
#define PMIC_VSRMCA7_PG_H2L_EN_MASK 0x1
#define PMIC_VSRMCA7_PG_H2L_EN_SHIFT 9
#define PMIC_VPCA7_PG_H2L_EN_MASK 0x1
#define PMIC_VPCA7_PG_H2L_EN_SHIFT 8
#define PMIC_UVLO_L2H_DEB_EN_MASK 0x1
#define PMIC_UVLO_L2H_DEB_EN_SHIFT 5
#define PMIC_CLR_JUST_RST_MASK 0x1
#define PMIC_CLR_JUST_RST_SHIFT 4
#define PMIC_STRUP_CON8_RSV0_MASK 0xFF
#define PMIC_STRUP_CON8_RSV0_SHIFT 8
#define PMIC_STRUP_EXT_PMIC_SEL_MASK 0x1
#define PMIC_STRUP_EXT_PMIC_SEL_SHIFT 5
#define PMIC_STRUP_EXT_PMIC_EN_MASK 0x1
#define PMIC_STRUP_EXT_PMIC_EN_SHIFT 4
#define PMIC_STRUP_AUXADC_RSTB_SEL_MASK 0x1
#define PMIC_STRUP_AUXADC_RSTB_SEL_SHIFT 6
#define PMIC_STRUP_AUXADC_START_SEL_MASK 0x1
#define PMIC_STRUP_AUXADC_START_SEL_SHIFT 5
#define PMIC_STRUP_AUXADC_RSTB_SW_MASK 0x1
#define PMIC_STRUP_AUXADC_RSTB_SW_SHIFT 4
#define PMIC_STRUP_AUXADC_START_SW_MASK 0x1
#define PMIC_STRUP_AUXADC_START_SW_SHIFT 3
#define PMIC_STRUP_AUXADC_EN_SEL_MASK 0x7
#define PMIC_STRUP_AUXADC_EN_SEL_SHIFT 0
#define PMIC_STRUP_PWROFF_PREOFF_EN_MASK 0x1
#define PMIC_STRUP_PWROFF_PREOFF_EN_SHIFT 1
#define PMIC_STRUP_PWROFF_SEQ_EN_MASK 0x1
#define PMIC_STRUP_PWROFF_SEQ_EN_SHIFT 0
#define PMIC_RG_ADC_RDY_C0_MASK 0x1
#define PMIC_RG_ADC_RDY_C0_SHIFT 15
#define PMIC_RG_ADC_OUT_C0_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C0_SHIFT 0
#define PMIC_RG_ADC_RDY_C1_MASK 0x1
#define PMIC_RG_ADC_RDY_C1_SHIFT 15
#define PMIC_RG_ADC_OUT_C1_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C1_SHIFT 0
#define PMIC_RG_ADC_RDY_C2_MASK 0x1
#define PMIC_RG_ADC_RDY_C2_SHIFT 15
#define PMIC_RG_ADC_OUT_C2_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C2_SHIFT 0
#define PMIC_RG_ADC_RDY_C3_MASK 0x1
#define PMIC_RG_ADC_RDY_C3_SHIFT 15
#define PMIC_RG_ADC_OUT_C3_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C3_SHIFT 0
#define PMIC_RG_ADC_RDY_C4_MASK 0x1
#define PMIC_RG_ADC_RDY_C4_SHIFT 15
#define PMIC_RG_ADC_OUT_C4_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C4_SHIFT 0
#define PMIC_RG_ADC_RDY_C5_MASK 0x1
#define PMIC_RG_ADC_RDY_C5_SHIFT 15
#define PMIC_RG_ADC_OUT_C5_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C5_SHIFT 0
#define PMIC_RG_ADC_RDY_C6_MASK 0x1
#define PMIC_RG_ADC_RDY_C6_SHIFT 15
#define PMIC_RG_ADC_OUT_C6_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C6_SHIFT 0
#define PMIC_RG_ADC_RDY_C7_MASK 0x1
#define PMIC_RG_ADC_RDY_C7_SHIFT 15
#define PMIC_RG_ADC_OUT_C7_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C7_SHIFT 0
#define PMIC_RG_ADC_RDY_WAKEUP_PCHR_MASK 0x1
#define PMIC_RG_ADC_RDY_WAKEUP_PCHR_SHIFT 15
#define PMIC_RG_ADC_OUT_WAKEUP_PCHR_MASK 0x3FF
#define PMIC_RG_ADC_OUT_WAKEUP_PCHR_SHIFT 0
#define PMIC_RG_ADC_RDY_WAKEUP_SWCHR_MASK 0x1
#define PMIC_RG_ADC_RDY_WAKEUP_SWCHR_SHIFT 15
#define PMIC_RG_ADC_OUT_WAKEUP_SWCHR_MASK 0x3FF
#define PMIC_RG_ADC_OUT_WAKEUP_SWCHR_SHIFT 0
#define PMIC_RG_ADC_RDY_LBAT_MASK 0x1
#define PMIC_RG_ADC_RDY_LBAT_SHIFT 15
#define PMIC_RG_ADC_OUT_LBAT_MASK 0x3FF
#define PMIC_RG_ADC_OUT_LBAT_SHIFT 0
#define PMIC_RG_ADC_OUT_C0_TRIM_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C0_TRIM_SHIFT 0
#define PMIC_RG_ADC_OUT_C1_TRIM_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C1_TRIM_SHIFT 0
#define PMIC_RG_ADC_OUT_C2_TRIM_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C2_TRIM_SHIFT 0
#define PMIC_RG_ADC_OUT_C3_TRIM_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C3_TRIM_SHIFT 0
#define PMIC_RG_ADC_OUT_C4_TRIM_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C4_TRIM_SHIFT 0
#define PMIC_RG_ADC_OUT_C5_TRIM_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C5_TRIM_SHIFT 0
#define PMIC_RG_ADC_OUT_C6_TRIM_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C6_TRIM_SHIFT 0
#define PMIC_RG_ADC_OUT_C7_TRIM_MASK 0x3FF
#define PMIC_RG_ADC_OUT_C7_TRIM_SHIFT 0
#define PMIC_RG_ADC_OUT_WAKEUP_PCHR_TRIM_MASK 0x3FF
#define PMIC_RG_ADC_OUT_WAKEUP_PCHR_TRIM_SHIFT 0
#define PMIC_RG_ADC_OUT_WAKEUP_SWCHR_TRIM_MASK 0x3FF
#define PMIC_RG_ADC_OUT_WAKEUP_SWCHR_TRIM_SHIFT 0
#define PMIC_RG_ADC_OUT_LBAT_TRIM_MASK 0x3FF
#define PMIC_RG_ADC_OUT_LBAT_TRIM_SHIFT 0
#define PMIC_RG_ADC_OUT_AVG_DECI_MASK 0x1FFF
#define PMIC_RG_ADC_OUT_AVG_DECI_SHIFT 0
#define PMIC_RG_SPL_NUM_MASK 0x1F
#define PMIC_RG_SPL_NUM_SHIFT 7
#define PMIC_RG_AVG_NUM_MASK 0x7
#define PMIC_RG_AVG_NUM_SHIFT 4
#define PMIC_RG_BUF_PWD_ON_MASK 0x1
#define PMIC_RG_BUF_PWD_ON_SHIFT 3
#define PMIC_RG_ADC_PWD_ON_MASK 0x1
#define PMIC_RG_ADC_PWD_ON_SHIFT 2
#define PMIC_RG_BUF_PWD_B_MASK 0x1
#define PMIC_RG_BUF_PWD_B_SHIFT 1
#define PMIC_RG_ADC_PWD_B_MASK 0x1
#define PMIC_RG_ADC_PWD_B_SHIFT 0
#define PMIC_RG_AUXADC_CHSEL_MASK 0xF
#define PMIC_RG_AUXADC_CHSEL_SHIFT 7
#define PMIC_RG_AUXADC_AUTO_STR_EN_MASK 0x1
#define PMIC_RG_AUXADC_AUTO_STR_EN_SHIFT 6
#define PMIC_RG_AUXADC_AUTO_STR_MASK 0x1
#define PMIC_RG_AUXADC_AUTO_STR_SHIFT 5
#define PMIC_RG_ADC_TRIM_COMP_MASK 0x1
#define PMIC_RG_ADC_TRIM_COMP_SHIFT 2
#define PMIC_RG_AUXADC_BIST_ENB_MASK 0x1
#define PMIC_RG_AUXADC_BIST_ENB_SHIFT 1
#define PMIC_RG_AUXADC_START_MASK 0x1
#define PMIC_RG_AUXADC_START_SHIFT 0
#define PMIC_RG_LBAT_DEBT_MIN_MASK 0xFF
#define PMIC_RG_LBAT_DEBT_MIN_SHIFT 8
#define PMIC_RG_LBAT_DEBT_MAX_MASK 0xFF
#define PMIC_RG_LBAT_DEBT_MAX_SHIFT 0
#define PMIC_RG_LBAT_DET_PRD_15_0_MASK 0xFFFF
#define PMIC_RG_LBAT_DET_PRD_15_0_SHIFT 0
#define PMIC_RG_LBAT_DET_PRD_19_16_MASK 0xF
#define PMIC_RG_LBAT_DET_PRD_19_16_SHIFT 0
#define PMIC_RG_LBAT_MAX_IRQ_B_MASK 0x1
#define PMIC_RG_LBAT_MAX_IRQ_B_SHIFT 15
#define PMIC_RG_LBAT_EN_MAX_MASK 0x1
#define PMIC_RG_LBAT_EN_MAX_SHIFT 13
#define PMIC_RG_LBAT_IRQ_EN_MAX_MASK 0x1
#define PMIC_RG_LBAT_IRQ_EN_MAX_SHIFT 12
#define PMIC_RG_LBAT_VOLT_MAX_MASK 0x3FF
#define PMIC_RG_LBAT_VOLT_MAX_SHIFT 0
#define PMIC_RG_LBAT_MIN_IRQ_B_MASK 0x1
#define PMIC_RG_LBAT_MIN_IRQ_B_SHIFT 15
#define PMIC_RG_LBAT_EN_MIN_MASK 0x1
#define PMIC_RG_LBAT_EN_MIN_SHIFT 13
#define PMIC_RG_LBAT_IRQ_EN_MIN_MASK 0x1
#define PMIC_RG_LBAT_IRQ_EN_MIN_SHIFT 12
#define PMIC_RG_LBAT_VOLT_MIN_MASK 0x3FF
#define PMIC_RG_LBAT_VOLT_MIN_SHIFT 0
#define PMIC_RG_LBAT_DEBOUNCE_COUNT_MAX_MASK 0x1FF
#define PMIC_RG_LBAT_DEBOUNCE_COUNT_MAX_SHIFT 0
#define PMIC_RG_LBAT_DEBOUNCE_COUNT_MIN_MASK 0x1FF
#define PMIC_RG_LBAT_DEBOUNCE_COUNT_MIN_SHIFT 0
#define PMIC_RG_NI_COMP_MASK 0x1
#define PMIC_RG_NI_COMP_SHIFT 15
#define PMIC_RG_DA_DAC_MASK 0x3FF
#define PMIC_RG_DA_DAC_SHIFT 0
#define PMIC_RG_AUXADC_CALI_MASK 0x3
#define PMIC_RG_AUXADC_CALI_SHIFT 10
#define PMIC_RG_BUF_CALI_MASK 0x3
#define PMIC_RG_BUF_CALI_SHIFT 8
#define PMIC_RG_AUXADC_RSV_MASK 0x7
#define PMIC_RG_AUXADC_RSV_SHIFT 5
#define PMIC_RG_DA_DAC_SEL_MASK 0x1
#define PMIC_RG_DA_DAC_SEL_SHIFT 4
#define PMIC_RG_AUX_OUT_SEL_MASK 0x1
#define PMIC_RG_AUX_OUT_SEL_SHIFT 3
#define PMIC_RG_ARB_PRIO_2_MASK 0x1
#define PMIC_RG_ARB_PRIO_2_SHIFT 2
#define PMIC_RG_ARB_PRIO_1_MASK 0x1
#define PMIC_RG_ARB_PRIO_1_SHIFT 1
#define PMIC_RG_ARB_PRIO_0_MASK 0x1
#define PMIC_RG_ARB_PRIO_0_SHIFT 0
#define PMIC_EFUSE_OFFSET_CH0_TRIM_MASK 0x3F
#define PMIC_EFUSE_OFFSET_CH0_TRIM_SHIFT 8
#define PMIC_EFUSE_GAIN_CH0_TRIM_MASK 0x7F
#define PMIC_EFUSE_GAIN_CH0_TRIM_SHIFT 0
#define PMIC_RG_VBUF_EN_MASK 0x1
#define PMIC_RG_VBUF_EN_SHIFT 6
#define PMIC_RG_VBUF_BYP_MASK 0x1
#define PMIC_RG_VBUF_BYP_SHIFT 4
#define PMIC_RG_VBUF_EXTEN_MASK 0x1
#define PMIC_RG_VBUF_EXTEN_SHIFT 2
#define PMIC_RG_VBUF_CALEN_MASK 0x1
#define PMIC_RG_VBUF_CALEN_SHIFT 0
#define PMIC_RG_THERMAL_ADC_OE_MASK 0x3F
#define PMIC_RG_THERMAL_ADC_OE_SHIFT 8
#define PMIC_RG_THERMAL_ADC_GE_MASK 0x7F
#define PMIC_RG_THERMAL_ADC_GE_SHIFT 0
#define PMIC_RG_ADC_TRIM_CH_SEL_MASK 0xFF
#define PMIC_RG_ADC_TRIM_CH_SEL_SHIFT 8
#define PMIC_RG_SOURCE_CH0_NORM_SEL_MASK 0x1
#define PMIC_RG_SOURCE_CH0_NORM_SEL_SHIFT 2
#define PMIC_RG_SOURCE_CH0_LBAT_SEL_MASK 0x1
#define PMIC_RG_SOURCE_CH0_LBAT_SEL_SHIFT 0
#define PMIC_FLASH_RSV0_MASK 0x3
#define PMIC_FLASH_RSV0_SHIFT 13
#define PMIC_FLASH_DIM_DUTY_MASK 0x1F
#define PMIC_FLASH_DIM_DUTY_SHIFT 8
#define PMIC_FLASH_THER_SHDN_EN_MASK 0x1
#define PMIC_FLASH_THER_SHDN_EN_SHIFT 1
#define PMIC_FLASH_EN_MASK 0x1
#define PMIC_FLASH_EN_SHIFT 0
#define PMIC_FLASH_DIM_DIV_MASK 0xFF
#define PMIC_FLASH_DIM_DIV_SHIFT 8
#define PMIC_FLASH_RSV1_MASK 0xF
#define PMIC_FLASH_RSV1_SHIFT 4
#define PMIC_FLASH_SEL_MASK 0xF
#define PMIC_FLASH_SEL_SHIFT 0
#define PMIC_FLASH_SFSTREN_MASK 0x1
#define PMIC_FLASH_SFSTREN_SHIFT 7
#define PMIC_FLASH_SFSTR_MASK 0x3
#define PMIC_FLASH_SFSTR_SHIFT 4
#define PMIC_FLASH_MODE_MASK 0x1
#define PMIC_FLASH_MODE_SHIFT 0
#define PMIC_KPLED_RSV0_MASK 0x7
#define PMIC_KPLED_RSV0_SHIFT 13
#define PMIC_KPLED_DIM_DUTY_MASK 0x1F
#define PMIC_KPLED_DIM_DUTY_SHIFT 8
#define PMIC_KPLED_THER_SHDN_EN_MASK 0x1
#define PMIC_KPLED_THER_SHDN_EN_SHIFT 1
#define PMIC_KPLED_EN_MASK 0x1
#define PMIC_KPLED_EN_SHIFT 0
#define PMIC_KPLED_DIM_DIV_MASK 0xFF
#define PMIC_KPLED_DIM_DIV_SHIFT 8
#define PMIC_KPLED_RSV1_MASK 0x1F
#define PMIC_KPLED_RSV1_SHIFT 3
#define PMIC_KPLED_SEL_MASK 0x7
#define PMIC_KPLED_SEL_SHIFT 0
#define PMIC_KPLED_SFSTREN_MASK 0x1
#define PMIC_KPLED_SFSTREN_SHIFT 15
#define PMIC_KPLED_SFSTR_MASK 0x3
#define PMIC_KPLED_SFSTR_SHIFT 12
#define PMIC_KPLED_MODE_MASK 0x1
#define PMIC_KPLED_MODE_SHIFT 8
#define PMIC_ISINK_RSV0_MASK 0x7
#define PMIC_ISINK_RSV0_SHIFT 13
#define PMIC_ISINK_DIM0_DUTY_MASK 0x1F
#define PMIC_ISINK_DIM0_DUTY_SHIFT 8
#define PMIC_ISINK_DIM0_FSEL_MASK 0x1F
#define PMIC_ISINK_DIM0_FSEL_SHIFT 0
#define PMIC_ISINK_RSV1_MASK 0x7
#define PMIC_ISINK_RSV1_SHIFT 13
#define PMIC_ISINK_DIM1_DUTY_MASK 0x1F
#define PMIC_ISINK_DIM1_DUTY_SHIFT 8
#define PMIC_ISINK_DIM1_FSEL_MASK 0x1F
#define PMIC_ISINK_DIM1_FSEL_SHIFT 0
#define PMIC_ISINK_RSV2_MASK 0x7
#define PMIC_ISINK_RSV2_SHIFT 13
#define PMIC_ISINK_RSV2_ISINK0_MASK 0x1
#define PMIC_ISINK_RSV2_ISINK0_SHIFT 13
#define PMIC_ISINK_RSV2_ISINK1_MASK 0x1
#define PMIC_ISINK_RSV2_ISINK1_SHIFT 14
#define PMIC_ISINK_RSV2_ISINK2_MASK 0x1
#define PMIC_ISINK_RSV2_ISINK2_SHIFT 15
#define PMIC_ISINK_DIM2_DUTY_MASK 0x1F
#define PMIC_ISINK_DIM2_DUTY_SHIFT 8
#define PMIC_ISINK_DIM2_FSEL_MASK 0x1F
#define PMIC_ISINK_DIM2_FSEL_SHIFT 0
#define PMIC_ISINK_RSV3_MASK 0x3
#define PMIC_ISINK_RSV3_SHIFT 14
#define PMIC_ISINKS_CH2_EN_MASK 0x1
#define PMIC_ISINKS_CH2_EN_SHIFT 10
#define PMIC_ISINKS_CH1_EN_MASK 0x1
#define PMIC_ISINKS_CH1_EN_SHIFT 9
#define PMIC_ISINKS_CH0_EN_MASK 0x1
#define PMIC_ISINKS_CH0_EN_SHIFT 8
#define PMIC_ISINK_RSV4_MASK 0x3
#define PMIC_ISINK_RSV4_SHIFT 6
#define PMIC_ISINKS2_CHOP_EN_MASK 0x1
#define PMIC_ISINKS2_CHOP_EN_SHIFT 2
#define PMIC_ISINKS1_CHOP_EN_MASK 0x1
#define PMIC_ISINKS1_CHOP_EN_SHIFT 1
#define PMIC_ISINKS0_CHOP_EN_MASK 0x1
#define PMIC_ISINKS0_CHOP_EN_SHIFT 0
#define PMIC_ISINKS_CH0_STEP_MASK 0x7
#define PMIC_ISINKS_CH0_STEP_SHIFT 12
#define PMIC_ISINK0_CHOP_MODE_MASK 0x1
#define PMIC_ISINK0_CHOP_MODE_SHIFT 11
#define PMIC_ISINK0_TEST_REG_MASK 0x1
#define PMIC_ISINK0_TEST_REG_SHIFT 10
#define PMIC_ISINKS_CH0_MODE_MASK 0x3
#define PMIC_ISINKS_CH0_MODE_SHIFT 8
#define PMIC_ISINKS_CH1_STEP_MASK 0x7
#define PMIC_ISINKS_CH1_STEP_SHIFT 12
#define PMIC_ISINK1_CHOP_MODE_MASK 0x1
#define PMIC_ISINK1_CHOP_MODE_SHIFT 11
#define PMIC_ISINK1_TEST_REG_MASK 0x1
#define PMIC_ISINK1_TEST_REG_SHIFT 10
#define PMIC_ISINKS_CH1_MODE_MASK 0x3
#define PMIC_ISINKS_CH1_MODE_SHIFT 8
#define PMIC_ISINKS_CH2_STEP_MASK 0x7
#define PMIC_ISINKS_CH2_STEP_SHIFT 12
#define PMIC_ISINK2_CHOP_MODE_MASK 0x1
#define PMIC_ISINK2_CHOP_MODE_SHIFT 11
#define PMIC_ISINK2_TEST_REG_MASK 0x1
#define PMIC_ISINK2_TEST_REG_SHIFT 10
#define PMIC_ISINKS_CH2_MODE_MASK 0x3
#define PMIC_ISINKS_CH2_MODE_SHIFT 8
#define PMIC_RG_TRIM_EN_MASK 0x1
#define PMIC_RG_TRIM_EN_SHIFT 14
#define PMIC_RG_TRIM_SEL_MASK 0x7
#define PMIC_RG_TRIM_SEL_SHIFT 9
#define PMIC_RG_LDO_BIST_MASK 0x1
#define PMIC_RG_LDO_BIST_SHIFT 8
#define PMIC_RG_ISINKS_RSV_MASK 0xFF
#define PMIC_RG_ISINKS_RSV_SHIFT 0
#define PMIC_ISINKS_BREATH0_TRF_SEL_MASK 0xF
#define PMIC_ISINKS_BREATH0_TRF_SEL_SHIFT 12
#define PMIC_ISINKS_BREATH0_TON_SEL_MASK 0xF
#define PMIC_ISINKS_BREATH0_TON_SEL_SHIFT 8
#define PMIC_ISINKS_BREATH0_TOFF_SEL_MASK 0xF
#define PMIC_ISINKS_BREATH0_TOFF_SEL_SHIFT 0
#define PMIC_ISINKS_BREATH1_TRF_SEL_MASK 0xF
#define PMIC_ISINKS_BREATH1_TRF_SEL_SHIFT 12
#define PMIC_ISINKS_BREATH1_TON_SEL_MASK 0xF
#define PMIC_ISINKS_BREATH1_TON_SEL_SHIFT 8
#define PMIC_ISINKS_BREATH1_TOFF_SEL_MASK 0xF
#define PMIC_ISINKS_BREATH1_TOFF_SEL_SHIFT 0
#define PMIC_ISINKS_BREATH2_TRF_SEL_MASK 0xF
#define PMIC_ISINKS_BREATH2_TRF_SEL_SHIFT 12
#define PMIC_ISINKS_BREATH2_TON_SEL_MASK 0xF
#define PMIC_ISINKS_BREATH2_TON_SEL_SHIFT 8
#define PMIC_ISINKS_BREATH2_TOFF_SEL_MASK 0xF
#define PMIC_ISINKS_BREATH2_TOFF_SEL_SHIFT 0
#define PMIC_ISINK0_SFSTR_EN_MASK 0x1
#define PMIC_ISINK0_SFSTR_EN_SHIFT 15
#define PMIC_ISINK1_SFSTR_EN_MASK 0x1
#define PMIC_ISINK1_SFSTR_EN_SHIFT 13
#define PMIC_ISINK2_SFSTR_EN_MASK 0x1
#define PMIC_ISINK2_SFSTR_EN_SHIFT 11
#define PMIC_ISINK0_SFSTR_TC_MASK 0x3
#define PMIC_ISINK0_SFSTR_TC_SHIFT 8
#define PMIC_ISINK1_SFSTR_TC_MASK 0x3
#define PMIC_ISINK1_SFSTR_TC_SHIFT 6
#define PMIC_ISINK2_SFSTR_TC_MASK 0x3
#define PMIC_ISINK2_SFSTR_TC_SHIFT 4
#define PMIC_RG_AUDACCDETRSV_MASK 0xF
#define PMIC_RG_AUDACCDETRSV_SHIFT 12
#define PMIC_ACCDET_CON0_RSV1_MASK 0x7
#define PMIC_ACCDET_CON0_RSV1_SHIFT 9
#define PMIC_RG_AUDACCDETVIN1PULLLOW_MASK 0x1
#define PMIC_RG_AUDACCDETVIN1PULLLOW_SHIFT 7
#define PMIC_RG_AUDACCDETTVDET_MASK 0x1
#define PMIC_RG_AUDACCDETTVDET_SHIFT 6
#define PMIC_AUDACCDETANASWCTRL_MASK 0x1
#define PMIC_AUDACCDETANASWCTRL_SHIFT 5
#define PMIC_AUDACCDETANASWCTRL_SEL_MASK 0x1
#define PMIC_AUDACCDETANASWCTRL_SEL_SHIFT 4
#define PMIC_ACCDET_CON0_RSV0_MASK 0x1
#define PMIC_ACCDET_CON0_RSV0_SHIFT 3
#define PMIC_RG_AUDACCDETVTHCAL_MASK 0x3
#define PMIC_RG_AUDACCDETVTHCAL_SHIFT 0
#define PMIC_ACCDET_SEQ_INIT_MASK 0x1
#define PMIC_ACCDET_SEQ_INIT_SHIFT 1
#define PMIC_ACCDET_EN_MASK 0x1
#define PMIC_ACCDET_EN_SHIFT 0
#define PMIC_ACCDET_MBIAS_PWM_IDLE_MASK 0x1
#define PMIC_ACCDET_MBIAS_PWM_IDLE_SHIFT 6
#define PMIC_ACCDET_VTH_PWM_IDLE_MASK 0x1
#define PMIC_ACCDET_VTH_PWM_IDLE_SHIFT 5
#define PMIC_ACCDET_CMP_PWM_IDLE_MASK 0x1
#define PMIC_ACCDET_CMP_PWM_IDLE_SHIFT 4
#define PMIC_ACCDET_MBIAS_PWM_EN_MASK 0x1
#define PMIC_ACCDET_MBIAS_PWM_EN_SHIFT 2
#define PMIC_ACCDET_VTH_PWM_EN_MASK 0x1
#define PMIC_ACCDET_VTH_PWM_EN_SHIFT 1
#define PMIC_ACCDET_CMP_PWM_EN_MASK 0x1
#define PMIC_ACCDET_CMP_PWM_EN_SHIFT 0
#define PMIC_ACCDET_PWM_WIDTH_MASK 0xFFFF
#define PMIC_ACCDET_PWM_WIDTH_SHIFT 0
#define PMIC_ACCDET_PWM_THRESH_MASK 0xFFFF
#define PMIC_ACCDET_PWM_THRESH_SHIFT 0
#define PMIC_ACCDET_FALL_DELAY_MASK 0x1
#define PMIC_ACCDET_FALL_DELAY_SHIFT 15
#define PMIC_ACCDET_RISE_DELAY_MASK 0x7FFF
#define PMIC_ACCDET_RISE_DELAY_SHIFT 0
#define PMIC_ACCDET_DEBOUNCE0_MASK 0xFFFF
#define PMIC_ACCDET_DEBOUNCE0_SHIFT 0
#define PMIC_ACCDET_DEBOUNCE1_MASK 0xFFFF
#define PMIC_ACCDET_DEBOUNCE1_SHIFT 0
#define PMIC_ACCDET_DEBOUNCE2_MASK 0xFFFF
#define PMIC_ACCDET_DEBOUNCE2_SHIFT 0
#define PMIC_ACCDET_DEBOUNCE3_MASK 0xFFFF
#define PMIC_ACCDET_DEBOUNCE3_SHIFT 0
#define PMIC_ACCDET_IVAL_SEL_MASK 0x1
#define PMIC_ACCDET_IVAL_SEL_SHIFT 15
#define PMIC_ACCDET_IVAL_MEM_IN_MASK 0x3
#define PMIC_ACCDET_IVAL_MEM_IN_SHIFT 8
#define PMIC_ACCDET_IVAL_SAM_IN_MASK 0x3
#define PMIC_ACCDET_IVAL_SAM_IN_SHIFT 4
#define PMIC_ACCDET_IVAL_CUR_IN_MASK 0x3
#define PMIC_ACCDET_IVAL_CUR_IN_SHIFT 0
#define PMIC_ACCDET_IRQ_CLR_MASK 0x1
#define PMIC_ACCDET_IRQ_CLR_SHIFT 8
#define PMIC_ACCDET_IRQ_MASK 0x1
#define PMIC_ACCDET_IRQ_SHIFT 0
#define PMIC_ACCDET_PWM_EN_SW_MASK 0x1
#define PMIC_ACCDET_PWM_EN_SW_SHIFT 15
#define PMIC_ACCDET_MBIAS_EN_SW_MASK 0x1
#define PMIC_ACCDET_MBIAS_EN_SW_SHIFT 14
#define PMIC_ACCDET_VTH_EN_SW_MASK 0x1
#define PMIC_ACCDET_VTH_EN_SW_SHIFT 13
#define PMIC_ACCDET_CMP_EN_SW_MASK 0x1
#define PMIC_ACCDET_CMP_EN_SW_SHIFT 12
#define PMIC_ACCDET_IN_SW_MASK 0x3
#define PMIC_ACCDET_IN_SW_SHIFT 8
#define PMIC_ACCDET_PWM_SEL_MASK 0x3
#define PMIC_ACCDET_PWM_SEL_SHIFT 6
#define PMIC_ACCDET_TEST_MODE5_MASK 0x1
#define PMIC_ACCDET_TEST_MODE5_SHIFT 5
#define PMIC_ACCDET_TEST_MODE4_MASK 0x1
#define PMIC_ACCDET_TEST_MODE4_SHIFT 4
#define PMIC_ACCDET_TEST_MODE3_MASK 0x1
#define PMIC_ACCDET_TEST_MODE3_SHIFT 3
#define PMIC_ACCDET_TEST_MODE2_MASK 0x1
#define PMIC_ACCDET_TEST_MODE2_SHIFT 2
#define PMIC_ACCDET_TEST_MODE1_MASK 0x1
#define PMIC_ACCDET_TEST_MODE1_SHIFT 1
#define PMIC_ACCDET_TEST_MODE0_MASK 0x1
#define PMIC_ACCDET_TEST_MODE0_SHIFT 0
#define PMIC_ACCDET_CMP_CLK_MASK 0x1
#define PMIC_ACCDET_CMP_CLK_SHIFT 14
#define PMIC_ACCDET_VTH_CLK_MASK 0x1
#define PMIC_ACCDET_VTH_CLK_SHIFT 13
#define PMIC_ACCDET_MBIAS_CLK_MASK 0x1
#define PMIC_ACCDET_MBIAS_CLK_SHIFT 12
#define PMIC_ACCDET_STATE_MASK 0x7
#define PMIC_ACCDET_STATE_SHIFT 8
#define PMIC_ACCDET_MEM_IN_MASK 0x3
#define PMIC_ACCDET_MEM_IN_SHIFT 6
#define PMIC_ACCDET_SAM_IN_MASK 0x3
#define PMIC_ACCDET_SAM_IN_SHIFT 4
#define PMIC_ACCDET_CUR_IN_MASK 0x3
#define PMIC_ACCDET_CUR_IN_SHIFT 2
#define PMIC_ACCDET_IN_MASK 0x3
#define PMIC_ACCDET_IN_SHIFT 0
#define PMIC_ACCDET_CUR_DEB_MASK 0xFFFF
#define PMIC_ACCDET_CUR_DEB_SHIFT 0
#define PMIC_ACCDET_RSV_CON0_MASK 0xFFFF
#define PMIC_ACCDET_RSV_CON0_SHIFT 0
#define PMIC_ACCDET_RSV_CON1_MASK 0xFFFF
#define PMIC_ACCDET_RSV_CON1_SHIFT 0
#define PMIC_RG_SPK_GAINL_MASK 0x3
#define PMIC_RG_SPK_GAINL_SHIFT 12
#define PMIC_SPK_OUT_STAGE_SEL_MASK 0x1
#define PMIC_SPK_OUT_STAGE_SEL_SHIFT 10
#define PMIC_SPK_THER_SHDN_L_EN_MASK 0x1
#define PMIC_SPK_THER_SHDN_L_EN_SHIFT 9
#define PMIC_SPK_OC_SHDN_DL_MASK 0x1
#define PMIC_SPK_OC_SHDN_DL_SHIFT 8
#define PMIC_SPK_TRIM_EN_L_MASK 0x1
#define PMIC_SPK_TRIM_EN_L_SHIFT 3
#define PMIC_SPKMODE_L_MASK 0x1
#define PMIC_SPKMODE_L_SHIFT 2
#define PMIC_SPK_EN_L_MASK 0x1
#define PMIC_SPK_EN_L_SHIFT 0
#define PMIC_SPK_TRIM_DONE_L_MASK 0x1
#define PMIC_SPK_TRIM_DONE_L_SHIFT 15
#define PMIC_SPK_OFFSET_L_MODE_MASK 0x1
#define PMIC_SPK_OFFSET_L_MODE_SHIFT 14
#define PMIC_SPK_LEAD_L_SW_MASK 0x1
#define PMIC_SPK_LEAD_L_SW_SHIFT 13
#define PMIC_SPK_OFFSET_L_SW_MASK 0x1F
#define PMIC_SPK_OFFSET_L_SW_SHIFT 8
#define PMIC_SPK_OFFSET_L_OV_MASK 0x1
#define PMIC_SPK_OFFSET_L_OV_SHIFT 7
#define PMIC_RG_SPK_OC_EN_L_MASK 0x1
#define PMIC_RG_SPK_OC_EN_L_SHIFT 10
#define PMIC_RG_SPKAB_OC_EN_L_MASK 0x1
#define PMIC_RG_SPKAB_OC_EN_L_SHIFT 9
#define PMIC_RG_SPK_TEST_EN_L_MASK 0x1
#define PMIC_RG_SPK_TEST_EN_L_SHIFT 8
#define PMIC_RG_SPK_DRC_EN_L_MASK 0x1
#define PMIC_RG_SPK_DRC_EN_L_SHIFT 7
#define PMIC_RG_SPKRCV_EN_L_MASK 0x1
#define PMIC_RG_SPKRCV_EN_L_SHIFT 6
#define PMIC_RG_SPKAB_OBIAS_L_MASK 0x3
#define PMIC_RG_SPKAB_OBIAS_L_SHIFT 4
#define PMIC_RG_SPK_SLEW_L_MASK 0x3
#define PMIC_RG_SPK_SLEW_L_SHIFT 2
#define PMIC_RG_SPK_FORCE_EN_L_MASK 0x1
#define PMIC_RG_SPK_FORCE_EN_L_SHIFT 1
#define PMIC_RG_SPK_INTG_RST_L_MASK 0x1
#define PMIC_RG_SPK_INTG_RST_L_SHIFT 0
#define PMIC_RG_SPK_GAINR_MASK 0x3
#define PMIC_RG_SPK_GAINR_SHIFT 12
#define PMIC_SPK_THER_SHDN_R_EN_MASK 0x1
#define PMIC_SPK_THER_SHDN_R_EN_SHIFT 9
#define PMIC_SPK_OC_SHDN_DR_MASK 0x1
#define PMIC_SPK_OC_SHDN_DR_SHIFT 8
#define PMIC_SPK_TRIM_EN_R_MASK 0x1
#define PMIC_SPK_TRIM_EN_R_SHIFT 3
#define PMIC_SPKMODE_R_MASK 0x1
#define PMIC_SPKMODE_R_SHIFT 2
#define PMIC_SPK_EN_R_MASK 0x1
#define PMIC_SPK_EN_R_SHIFT 0
#define PMIC_SPK_TRIM_DONE_R_MASK 0x1
#define PMIC_SPK_TRIM_DONE_R_SHIFT 15
#define PMIC_SPK_OFFSET_R_MODE_MASK 0x1
#define PMIC_SPK_OFFSET_R_MODE_SHIFT 14
#define PMIC_SPK_LEAD_R_SW_MASK 0x1
#define PMIC_SPK_LEAD_R_SW_SHIFT 13
#define PMIC_SPK_OFFSET_R_SW_MASK 0x1F
#define PMIC_SPK_OFFSET_R_SW_SHIFT 8
#define PMIC_SPK_OFFSET_R_OV_MASK 0x1
#define PMIC_SPK_OFFSET_R_OV_SHIFT 7
#define PMIC_RG_SPKPGA_GAINR_MASK 0xF
#define PMIC_RG_SPKPGA_GAINR_SHIFT 11
#define PMIC_RG_SPK_OC_EN_R_MASK 0x1
#define PMIC_RG_SPK_OC_EN_R_SHIFT 10
#define PMIC_RG_SPKAB_OC_EN_R_MASK 0x1
#define PMIC_RG_SPKAB_OC_EN_R_SHIFT 9
#define PMIC_RG_SPK_TEST_EN_R_MASK 0x1
#define PMIC_RG_SPK_TEST_EN_R_SHIFT 8
#define PMIC_RG_SPK_DRC_EN_R_MASK 0x1
#define PMIC_RG_SPK_DRC_EN_R_SHIFT 7
#define PMIC_RG_SPKRCV_EN_R_MASK 0x1
#define PMIC_RG_SPKRCV_EN_R_SHIFT 6
#define PMIC_RG_SPKAB_OBIAS_R_MASK 0x3
#define PMIC_RG_SPKAB_OBIAS_R_SHIFT 4
#define PMIC_RG_SPK_SLEW_R_MASK 0x3
#define PMIC_RG_SPK_SLEW_R_SHIFT 2
#define PMIC_RG_SPK_FORCE_EN_R_MASK 0x1
#define PMIC_RG_SPK_FORCE_EN_R_SHIFT 1
#define PMIC_RG_SPK_INTG_RST_R_MASK 0x1
#define PMIC_RG_SPK_INTG_RST_R_SHIFT 0
#define PMIC_SPK_AB_OC_L_DEG_MASK 0x1
#define PMIC_SPK_AB_OC_L_DEG_SHIFT 15
#define PMIC_SPK_D_OC_L_DEG_MASK 0x1
#define PMIC_SPK_D_OC_L_DEG_SHIFT 14
#define PMIC_SPK_AB_OC_R_DEG_MASK 0x1
#define PMIC_SPK_AB_OC_R_DEG_SHIFT 13
#define PMIC_SPK_D_OC_R_DEG_MASK 0x1
#define PMIC_SPK_D_OC_R_DEG_SHIFT 12
#define PMIC_SPK_OC_THD_MASK 0x3
#define PMIC_SPK_OC_THD_SHIFT 10
#define PMIC_SPK_OC_WND_MASK 0x3
#define PMIC_SPK_OC_WND_SHIFT 8
#define PMIC_SPK_TRIM_THD_MASK 0x3
#define PMIC_SPK_TRIM_THD_SHIFT 4
#define PMIC_SPK_TRIM_WND_MASK 0x7
#define PMIC_SPK_TRIM_WND_SHIFT 0
#define PMIC_SPK_TRIM_DIV_MASK 0x7
#define PMIC_SPK_TRIM_DIV_SHIFT 12
#define PMIC_SPK_TD3_MASK 0xF
#define PMIC_SPK_TD3_SHIFT 8
#define PMIC_SPK_TD2_MASK 0xF
#define PMIC_SPK_TD2_SHIFT 4
#define PMIC_SPK_TD1_MASK 0xF
#define PMIC_SPK_TD1_SHIFT 0
#define PMIC_RG_SPK_OCTH_D_MASK 0x1
#define PMIC_RG_SPK_OCTH_D_SHIFT 14
#define PMIC_RG_SPKAB_OVDRV_MASK 0x1
#define PMIC_RG_SPKAB_OVDRV_SHIFT 13
#define PMIC_RG_SPK_FBRC_EN_MASK 0x1
#define PMIC_RG_SPK_FBRC_EN_SHIFT 12
#define PMIC_RG_SPK_VCM_IBSEL_MASK 0x1
#define PMIC_RG_SPK_VCM_IBSEL_SHIFT 11
#define PMIC_RG_SPK_VCM_SEL_MASK 0x1
#define PMIC_RG_SPK_VCM_SEL_SHIFT 10
#define PMIC_RG_SPK_EN_VIEW_CLK_MASK 0x1
#define PMIC_RG_SPK_EN_VIEW_CLK_SHIFT 9
#define PMIC_RG_SPK_EN_VIEW_VCM_MASK 0x1
#define PMIC_RG_SPK_EN_VIEW_VCM_SHIFT 8
#define PMIC_RG_SPK_CCODE_MASK 0xF
#define PMIC_RG_SPK_CCODE_SHIFT 4
#define PMIC_RG_SPK_IBIAS_SEL_MASK 0x3
#define PMIC_RG_SPK_IBIAS_SEL_SHIFT 2
#define PMIC_RG_BTL_SET_MASK 0x3
#define PMIC_RG_BTL_SET_SHIFT 0
#define PMIC_SPK_TEST_MODE1_MASK 0x1
#define PMIC_SPK_TEST_MODE1_SHIFT 15
#define PMIC_SPK_TEST_MODE0_MASK 0x1
#define PMIC_SPK_TEST_MODE0_SHIFT 14
#define PMIC_SPK_VCM_FAST_EN_MASK 0x1
#define PMIC_SPK_VCM_FAST_EN_SHIFT 13
#define PMIC_SPK_RSV0_MASK 0x1
#define PMIC_SPK_RSV0_SHIFT 12
#define PMIC_RG_SPKPGA_GAINL_MASK 0xF
#define PMIC_RG_SPKPGA_GAINL_SHIFT 8
#define PMIC_RG_SPK_RSV_MASK 0xFF
#define PMIC_RG_SPK_RSV_SHIFT 0
#define PMIC_SPK_TD_DONE_MASK 0x7
#define PMIC_SPK_TD_DONE_SHIFT 4
#define PMIC_SPK_TD_WAIT_MASK 0x7
#define PMIC_SPK_TD_WAIT_SHIFT 0
#define PMIC_SPK_TRIM_STOP_L_SW_MASK 0x1
#define PMIC_SPK_TRIM_STOP_L_SW_SHIFT 15
#define PMIC_SPK_TRIM_STOP_R_SW_MASK 0x1
#define PMIC_SPK_TRIM_STOP_R_SW_SHIFT 14
#define PMIC_SPK_TRIM_EN_L_SW_MASK 0x1
#define PMIC_SPK_TRIM_EN_L_SW_SHIFT 13
#define PMIC_SPK_TRIM_EN_R_SW_MASK 0x1
#define PMIC_SPK_TRIM_EN_R_SW_SHIFT 12
#define PMIC_SPK_OUTSTG_EN_L_SW_MASK 0x1
#define PMIC_SPK_OUTSTG_EN_L_SW_SHIFT 11
#define PMIC_SPK_OUTSTG_EN_R_SW_MASK 0x1
#define PMIC_SPK_OUTSTG_EN_R_SW_SHIFT 10
#define PMIC_SPK_EN_L_SW_MASK 0x1
#define PMIC_SPK_EN_L_SW_SHIFT 9
#define PMIC_SPK_EN_R_SW_MASK 0x1
#define PMIC_SPK_EN_R_SW_SHIFT 8
#define PMIC_SPK_DEPOP_EN_L_SW_MASK 0x1
#define PMIC_SPK_DEPOP_EN_L_SW_SHIFT 7
#define PMIC_SPK_DEPOP_EN_R_SW_MASK 0x1
#define PMIC_SPK_DEPOP_EN_R_SW_SHIFT 6
#define PMIC_SPKMODE_L_SW_MASK 0x1
#define PMIC_SPKMODE_L_SW_SHIFT 5
#define PMIC_SPKMODE_R_SW_MASK 0x1
#define PMIC_SPKMODE_R_SW_SHIFT 4
#define PMIC_SPK_RST_L_SW_MASK 0x1
#define PMIC_SPK_RST_L_SW_SHIFT 3
#define PMIC_SPK_RST_R_SW_MASK 0x1
#define PMIC_SPK_RST_R_SW_SHIFT 2
#define PMIC_SPK_VCM_FAST_SW_MASK 0x1
#define PMIC_SPK_VCM_FAST_SW_SHIFT 1
#define PMIC_SPK_EN_MODE_MASK 0x1
#define PMIC_SPK_EN_MODE_SHIFT 0
#define PMIC_FG_SW_RSTCLR_MASK 0x1
#define PMIC_FG_SW_RSTCLR_SHIFT 15
#define PMIC_FG_CHARGE_RST_MASK 0x1
#define PMIC_FG_CHARGE_RST_SHIFT 14
#define PMIC_FG_TIME_RST_MASK 0x1
#define PMIC_FG_TIME_RST_SHIFT 13
#define PMIC_FG_OFFSET_RST_MASK 0x1
#define PMIC_FG_OFFSET_RST_SHIFT 12
#define PMIC_FG_SW_CLEAR_MASK 0x1
#define PMIC_FG_SW_CLEAR_SHIFT 11
#define PMIC_FG_LATCHDATA_ST_MASK 0x1
#define PMIC_FG_LATCHDATA_ST_SHIFT 10
#define PMIC_FG_SW_READ_PRE_MASK 0x1
#define PMIC_FG_SW_READ_PRE_SHIFT 9
#define PMIC_FG_SW_CR_MASK 0x1
#define PMIC_FG_SW_CR_SHIFT 8
#define PMIC_RG_FGCLKSRC_MASK 0x1
#define PMIC_RG_FGCLKSRC_SHIFT 7
#define PMIC_FG_AUTOCALRATE_MASK 0x7
#define PMIC_FG_AUTOCALRATE_SHIFT 4
#define PMIC_FG_CAL_MASK 0x3
#define PMIC_FG_CAL_SHIFT 2
#define PMIC_FG_VMODE_MASK 0x1
#define PMIC_FG_VMODE_SHIFT 1
#define PMIC_FG_ON_MASK 0x1
#define PMIC_FG_ON_SHIFT 0
#define PMIC_FG_CAR_35_32_MASK 0xF
#define PMIC_FG_CAR_35_32_SHIFT 0
#define PMIC_FG_CAR_31_16_MASK 0xFFFF
#define PMIC_FG_CAR_31_16_SHIFT 0
#define PMIC_FG_CAR_15_00_MASK 0xFFFF
#define PMIC_FG_CAR_15_00_SHIFT 0
#define PMIC_FG_NTER_29_16_MASK 0x3FFF
#define PMIC_FG_NTER_29_16_SHIFT 0
#define PMIC_FG_NTER_15_00_MASK 0xFFFF
#define PMIC_FG_NTER_15_00_SHIFT 0
#define PMIC_FG_BLTR_MASK 0xFFFF
#define PMIC_FG_BLTR_SHIFT 0
#define PMIC_FG_BFTR_MASK 0xFFFF
#define PMIC_FG_BFTR_SHIFT 0
#define PMIC_FG_CURRENT_OUT_MASK 0xFFFF
#define PMIC_FG_CURRENT_OUT_SHIFT 0
#define PMIC_FG_ADJUST_OFFSET_VALUE_MASK 0xFFFF
#define PMIC_FG_ADJUST_OFFSET_VALUE_SHIFT 0
#define PMIC_FG_OFFSET_MASK 0xFFFF
#define PMIC_FG_OFFSET_SHIFT 0
#define PMIC_RG_INPUTCLKSEL_MASK 0x3
#define PMIC_RG_INPUTCLKSEL_SHIFT 12
#define PMIC_RG_FGANALOGTEST_MASK 0xF
#define PMIC_RG_FGANALOGTEST_SHIFT 8
#define PMIC_RG_SPARE_MASK 0xFF
#define PMIC_RG_SPARE_SHIFT 0
#define PMIC_FG_ADC_AUTORST_MASK 0x1
#define PMIC_FG_ADC_AUTORST_SHIFT 9
#define PMIC_FG_ADJ_OFFSET_EN_MASK 0x1
#define PMIC_FG_ADJ_OFFSET_EN_SHIFT 8
#define PMIC_VOL_OSR_H_MASK 0x1
#define PMIC_VOL_OSR_H_SHIFT 7
#define PMIC_VOL_OSR_MASK 0x7
#define PMIC_VOL_OSR_SHIFT 4
#define PMIC_FG_OSR_H_MASK 0x1
#define PMIC_FG_OSR_H_SHIFT 3
#define PMIC_FG_OSR_MASK 0x7
#define PMIC_FG_OSR_SHIFT 0
#define PMIC_RG_FGVMODE_MASK 0x1
#define PMIC_RG_FGVMODE_SHIFT 15
#define PMIC_FG_RST_MASK 0x1
#define PMIC_FG_RST_SHIFT 14
#define PMIC_FGCAL_EN_MASK 0x1
#define PMIC_FGCAL_EN_SHIFT 13
#define PMIC_FGADC_EN_MASK 0x1
#define PMIC_FGADC_EN_SHIFT 12
#define PMIC_FG_SLP_EN_MASK 0x1
#define PMIC_FG_SLP_EN_SHIFT 8
#define PMIC_FG_ADC_RSTDETECT_MASK 0x1
#define PMIC_FG_ADC_RSTDETECT_SHIFT 7
#define PMIC_FG_H_INT_STS_MASK 0x1
#define PMIC_FG_H_INT_STS_SHIFT 5
#define PMIC_FG_L_INT_STS_MASK 0x1
#define PMIC_FG_L_INT_STS_SHIFT 4
#define PMIC_VOL_FIR1BYPASS_MASK 0x1
#define PMIC_VOL_FIR1BYPASS_SHIFT 2
#define PMIC_FG_FIR2BYPASS_MASK 0x1
#define PMIC_FG_FIR2BYPASS_SHIFT 1
#define PMIC_FG_FIR1BYPASS_MASK 0x1
#define PMIC_FG_FIR1BYPASS_SHIFT 0
#define PMIC_VOL_CURRENT_OUT_MASK 0xFFFF
#define PMIC_VOL_CURRENT_OUT_SHIFT 0
#define PMIC_FG_CIC2_MASK 0xFFFF
#define PMIC_FG_CIC2_SHIFT 0
#define PMIC_FG_SLP_CUR_TH_MASK 0xFFFF
#define PMIC_FG_SLP_CUR_TH_SHIFT 0
#define PMIC_FG_SLP_TIME_MASK 0xFF
#define PMIC_FG_SLP_TIME_SHIFT 0
#define PMIC_FG_DET_TIME_MASK 0xFF
#define PMIC_FG_DET_TIME_SHIFT 8
#define PMIC_FG_SRCVOLTEN_FTIME_MASK 0xFF
#define PMIC_FG_SRCVOLTEN_FTIME_SHIFT 0
#define PMIC_FG_TEST_MODE1_MASK 0x1
#define PMIC_FG_TEST_MODE1_SHIFT 15
#define PMIC_FG_TEST_MODE0_MASK 0x1
#define PMIC_FG_TEST_MODE0_SHIFT 14
#define PMIC_FG_RSV1_MASK 0x7
#define PMIC_FG_RSV1_SHIFT 5
#define PMIC_FG_VMODE_SW_MASK 0x1
#define PMIC_FG_VMODE_SW_SHIFT 4
#define PMIC_FG_FGADC_EN_SW_MASK 0x1
#define PMIC_FG_FGADC_EN_SW_SHIFT 3
#define PMIC_FG_FGCAL_EN_SW_MASK 0x1
#define PMIC_FG_FGCAL_EN_SW_SHIFT 2
#define PMIC_FG_RST_SW_MASK 0x1
#define PMIC_FG_RST_SW_SHIFT 1
#define PMIC_FG_MODE_MASK 0x1
#define PMIC_FG_MODE_SHIFT 0
#define PMIC_STMP_MODE_MASK 0x1
#define PMIC_STMP_MODE_SHIFT 12
#define PMIC_MIX_XOSC32_STP_CALI_MASK 0x1F
#define PMIC_MIX_XOSC32_STP_CALI_SHIFT 7
#define PMIC_MIX_XOSC32_STP_LPDRST_MASK 0x1
#define PMIC_MIX_XOSC32_STP_LPDRST_SHIFT 6
#define PMIC_MIX_XOSC32_STP_LPDEN_MASK 0x1
#define PMIC_MIX_XOSC32_STP_LPDEN_SHIFT 5
#define PMIC_MIX_XOSC32_STP_LPDTB_MASK 0x1
#define PMIC_MIX_XOSC32_STP_LPDTB_SHIFT 4
#define PMIC_MIX_XOSC32_STP_PWDB_MASK 0x1
#define PMIC_MIX_XOSC32_STP_PWDB_SHIFT 3
#define PMIC_MIX_XOSC32_STP_CPDTB_MASK 0x1
#define PMIC_MIX_XOSC32_STP_CPDTB_SHIFT 2
#define PMIC_MIX_EOSC32_OPT_MASK 0x3
#define PMIC_MIX_EOSC32_OPT_SHIFT 0
#define PMIC_mix_efuse_xosc32_enb_opt_MASK 0x1
#define PMIC_mix_efuse_xosc32_enb_opt_SHIFT 12
#define PMIC_mix_rtc_xosc32_enb_MASK 0x1
#define PMIC_mix_rtc_xosc32_enb_SHIFT 11
#define PMIC_mix_stp_rtc_ddlo_MASK 0x1
#define PMIC_mix_stp_rtc_ddlo_SHIFT 10
#define PMIC_mix_stp_bbwakeup_MASK 0x1
#define PMIC_mix_stp_bbwakeup_SHIFT 9
#define PMIC_MIX_EOSC32_VCT_EN_MASK 0x1
#define PMIC_MIX_EOSC32_VCT_EN_SHIFT 8
#define PMIC_MIX_EOSC32_STP_RSV_MASK 0x3
#define PMIC_MIX_EOSC32_STP_RSV_SHIFT 6
#define PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_MASK 0x1
#define PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_SHIFT 5
#define PMIC_MIX_RTC_STP_XOSC32_ENB_MASK 0x1
#define PMIC_MIX_RTC_STP_XOSC32_ENB_SHIFT 4
#define PMIC_MIX_PMU_STP_DDLO_VRTC_EN_MASK 0x1
#define PMIC_MIX_PMU_STP_DDLO_VRTC_EN_SHIFT 3
#define PMIC_MIX_PMU_STP_DDLO_VRTC_MASK 0x1
#define PMIC_MIX_PMU_STP_DDLO_VRTC_SHIFT 2
#define PMIC_MIX_DCXO_STP_LVSH_EN_MASK 0x1
#define PMIC_MIX_DCXO_STP_LVSH_EN_SHIFT 1
#define PMIC_MIX_EOSC32_STP_CHOP_EN_MASK 0x1
#define PMIC_MIX_EOSC32_STP_CHOP_EN_SHIFT 0
#define PMIC_RG_DC2AC_EN_VAUDP12_MASK 0x1
#define PMIC_RG_DC2AC_EN_VAUDP12_SHIFT 4
#define PMIC_RG_AUD_DAC_PWL_UP_VA28_MASK 0x1
#define PMIC_RG_AUD_DAC_PWL_UP_VA28_SHIFT 3
#define PMIC_RG_AUD_DAC_PWR_UP_VA28_MASK 0x1
#define PMIC_RG_AUD_DAC_PWR_UP_VA28_SHIFT 2
#define PMIC_RG_AUDDACRPWRUP_VAUDP12_MASK 0x1
#define PMIC_RG_AUDDACRPWRUP_VAUDP12_SHIFT 1
#define PMIC_RG_AUDDACLPWRUP_VAUDP12_MASK 0x1
#define PMIC_RG_AUDDACLPWRUP_VAUDP12_SHIFT 0
#define PMIC_RG_AUDHPRSCDISABLE_VAUDP12_MASK 0x1
#define PMIC_RG_AUDHPRSCDISABLE_VAUDP12_SHIFT 15
#define PMIC_RG_AUDHPLSCDISABLE_VAUDP12_MASK 0x1
#define PMIC_RG_AUDHPLSCDISABLE_VAUDP12_SHIFT 14
#define PMIC_RG_AUDHSSCDISABLE_VAUDP12_MASK 0x1
#define PMIC_RG_AUDHSSCDISABLE_VAUDP12_SHIFT 13
#define PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP12_MASK 0xF
#define PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP12_SHIFT 9
#define PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP12_MASK 0xF
#define PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP12_SHIFT 5
#define PMIC_RG_AUDHSMUXINPUTSEL_VAUDP12_MASK 0x3
#define PMIC_RG_AUDHSMUXINPUTSEL_VAUDP12_SHIFT 3
#define PMIC_RG_AUDHPRPWRUP_VAUDP12_MASK 0x1
#define PMIC_RG_AUDHPRPWRUP_VAUDP12_SHIFT 2
#define PMIC_RG_AUDHPLPWRUP_VAUDP12_MASK 0x1
#define PMIC_RG_AUDHPLPWRUP_VAUDP12_SHIFT 1
#define PMIC_RG_AUDHSPWRUP_VAUDP12_MASK 0x1
#define PMIC_RG_AUDHSPWRUP_VAUDP12_SHIFT 0
#define PMIC_RG_LINENOISEENH_VAUDP12_MASK 0x1
#define PMIC_RG_LINENOISEENH_VAUDP12_SHIFT 12
#define PMIC_RG_HPOUT_SHORTVCM_VAUDP12_MASK 0x1
#define PMIC_RG_HPOUT_SHORTVCM_VAUDP12_SHIFT 11
#define PMIC_RG_HPOUTPUTRESET0_VAUDP12_MASK 0x1
#define PMIC_RG_HPOUTPUTRESET0_VAUDP12_SHIFT 10
#define PMIC_RG_HPINPUTRESET0_VAUDP12_MASK 0x1
#define PMIC_RG_HPINPUTRESET0_VAUDP12_SHIFT 9
#define PMIC_RG_HPOUTPUTSTBENH_VAUDP12_MASK 0x1
#define PMIC_RG_HPOUTPUTSTBENH_VAUDP12_SHIFT 8
#define PMIC_RG_HPINPUTSTBENH_VAUDP12_MASK 0x1
#define PMIC_RG_HPINPUTSTBENH_VAUDP12_SHIFT 7
#define PMIC_RG_PRECHARGEBUF_EN_VAUDP12_MASK 0x1
#define PMIC_RG_PRECHARGEBUF_EN_VAUDP12_SHIFT 6
#define PMIC_RG_AUDBGBON_VAUDP12_MASK 0x1
#define PMIC_RG_AUDBGBON_VAUDP12_SHIFT 5
#define PMIC_RG_AUDHSSTARTUP_VAUDP12_MASK 0x1
#define PMIC_RG_AUDHSSTARTUP_VAUDP12_SHIFT 4
#define PMIC_RG_AUDHPSTARTUP_VAUDP12_MASK 0x1
#define PMIC_RG_AUDHPSTARTUP_VAUDP12_SHIFT 3
#define PMIC_RG_AUDHSBSCCURRENT_VAUDP12_MASK 0x1
#define PMIC_RG_AUDHSBSCCURRENT_VAUDP12_SHIFT 2
#define PMIC_RG_AUDHPRBSCCURRENT_VAUDP12_MASK 0x1
#define PMIC_RG_AUDHPRBSCCURRENT_VAUDP12_SHIFT 1
#define PMIC_RG_AUDHPLBSCCURRENT_VAUDP12_MASK 0x1
#define PMIC_RG_AUDHPLBSCCURRENT_VAUDP12_SHIFT 0
#define PMIC_RG_HSOUT_SHORTVCM_VAUDP12_MASK 0x1
#define PMIC_RG_HSOUT_SHORTVCM_VAUDP12_SHIFT 7
#define PMIC_RG_HPOUTSTB_RSEL_VAUDP12_MASK 0x7
#define PMIC_RG_HPOUTSTB_RSEL_VAUDP12_SHIFT 4
#define PMIC_RG_HSOUTPUTRESET0_VAUDP12_MASK 0x1
#define PMIC_RG_HSOUTPUTRESET0_VAUDP12_SHIFT 3
#define PMIC_RG_HSINPUTRESET0_VAUDP12_MASK 0x1
#define PMIC_RG_HSINPUTRESET0_VAUDP12_SHIFT 2
#define PMIC_RG_HSOUTPUTSTBENH_VAUDP12_MASK 0x1
#define PMIC_RG_HSOUTPUTSTBENH_VAUDP12_SHIFT 1
#define PMIC_RG_HSINPUTSTBENH_VAUDP12_MASK 0x1
#define PMIC_RG_HSINPUTSTBENH_VAUDP12_SHIFT 0
#define PMIC_RG_LINE_PULL0V_VAUDP12_MASK 0x3
#define PMIC_RG_LINE_PULL0V_VAUDP12_SHIFT 13
#define PMIC_RG_AUDHPRFINETRIM_VAUDP12_MASK 0x3
#define PMIC_RG_AUDHPRFINETRIM_VAUDP12_SHIFT 11
#define PMIC_RG_AUDHPLFINETRIM_VAUDP12_MASK 0x3
#define PMIC_RG_AUDHPLFINETRIM_VAUDP12_SHIFT 9
#define PMIC_RG_AUDHPTRIM_EN_VAUDP12_MASK 0x1
#define PMIC_RG_AUDHPTRIM_EN_VAUDP12_SHIFT 8
#define PMIC_RG_AUDHPRTRIM_VAUDP12_MASK 0xF
#define PMIC_RG_AUDHPRTRIM_VAUDP12_SHIFT 4
#define PMIC_RG_AUDHPLTRIM_VAUDP12_MASK 0xF
#define PMIC_RG_AUDHPLTRIM_VAUDP12_SHIFT 0
#define PMIC_RG_ABIDEC_RESERVED_VAUDP12_MASK 0xFF
#define PMIC_RG_ABIDEC_RESERVED_VAUDP12_SHIFT 8
#define PMIC_RG_ABIDEC_RESERVED_VA28_MASK 0xFF
#define PMIC_RG_ABIDEC_RESERVED_VA28_SHIFT 0
#define PMIC_RG_AUDIBIASPWRDN_VAUDP12_MASK 0x1
#define PMIC_RG_AUDIBIASPWRDN_VAUDP12_SHIFT 12
#define PMIC_RG_AUDBIASADJ_1_VAUDP12_MASK 0x3F
#define PMIC_RG_AUDBIASADJ_1_VAUDP12_SHIFT 6
#define PMIC_RG_AUDBIASADJ_0_VAUDP12_MASK 0x3F
#define PMIC_RG_AUDBIASADJ_0_VAUDP12_SHIFT 0
#define PMIC_RG_CHARGEOPTION_DEPOP_VA28_MASK 0x1
#define PMIC_RG_CHARGEOPTION_DEPOP_VA28_SHIFT 6
#define PMIC_RG_DEPOP_ISEL_VA28_MASK 0x3
#define PMIC_RG_DEPOP_ISEL_VA28_SHIFT 4
#define PMIC_RG_DEPOP_VCMGEN_EN_VA28_MASK 0x1
#define PMIC_RG_DEPOP_VCMGEN_EN_VA28_SHIFT 3
#define PMIC_RG_DEPOP_RSEL_VA28_MASK 0x3
#define PMIC_RG_DEPOP_RSEL_VA28_SHIFT 1
#define PMIC_RG_DEPOP_REN_VA28_MASK 0x1
#define PMIC_RG_DEPOP_REN_VA28_SHIFT 0
#define PMIC_RG_AUDIVRMUTE_VAUDP12_MASK 0x1
#define PMIC_RG_AUDIVRMUTE_VAUDP12_SHIFT 13
#define PMIC_RG_AUDIVRMUXSEL_VAUDP12_MASK 0x7
#define PMIC_RG_AUDIVRMUXSEL_VAUDP12_SHIFT 10
#define PMIC_RG_AUDIVRSTARTUP_VAUDP12_MASK 0x1
#define PMIC_RG_AUDIVRSTARTUP_VAUDP12_SHIFT 9
#define PMIC_RG_AUDIVRPWRUP_VAUDP12_MASK 0x1
#define PMIC_RG_AUDIVRPWRUP_VAUDP12_SHIFT 8
#define PMIC_RG_AUDIVLMUTE_VAUDP12_MASK 0x1
#define PMIC_RG_AUDIVLMUTE_VAUDP12_SHIFT 5
#define PMIC_RG_AUDIVLMUXSEL_VAUDP12_MASK 0x7
#define PMIC_RG_AUDIVLMUXSEL_VAUDP12_SHIFT 2
#define PMIC_RG_AUDIVLSTARTUP_VAUDP12_MASK 0x1
#define PMIC_RG_AUDIVLSTARTUP_VAUDP12_SHIFT 1
#define PMIC_RG_AUDIVLPWRUP_VAUDP12_MASK 0x1
#define PMIC_RG_AUDIVLPWRUP_VAUDP12_SHIFT 0
#define PMIC_RG_SEL_DELAY_VCORE_MASK 0x1
#define PMIC_RG_SEL_DELAY_VCORE_SHIFT 4
#define PMIC_RG_SEL_ENCODER_96K_VA28_MASK 0x1
#define PMIC_RG_SEL_ENCODER_96K_VA28_SHIFT 3
#define PMIC_RG_SEL_DECODER_96K_VA28_MASK 0x1
#define PMIC_RG_SEL_DECODER_96K_VA28_SHIFT 2
#define PMIC_RG_RSTB_ENCODER_VA28_MASK 0x1
#define PMIC_RG_RSTB_ENCODER_VA28_SHIFT 1
#define PMIC_RG_RSTB_DECODER_VA28_MASK 0x1
#define PMIC_RG_RSTB_DECODER_VA28_SHIFT 0
#define PMIC_RG_VA28REFGEN_EN_VA28_MASK 0x1
#define PMIC_RG_VA28REFGEN_EN_VA28_SHIFT 11
#define PMIC_RG_VA33REFGEN_EN_VA33_MASK 0x1
#define PMIC_RG_VA33REFGEN_EN_VA33_SHIFT 10
#define PMIC_RG_VBATREFGEN_EN_VBAT_MASK 0x1
#define PMIC_RG_VBATREFGEN_EN_VBAT_SHIFT 9
#define PMIC_RG_VBATPREREG_PDDIS_EN_VBAT_MASK 0x1
#define PMIC_RG_VBATPREREG_PDDIS_EN_VBAT_SHIFT 8
#define PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK 0x1
#define PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28_SHIFT 7
#define PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28_MASK 0x1
#define PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28_SHIFT 6
#define PMIC_RG_LCLDO_VOSEL_VA33_MASK 0x1
#define PMIC_RG_LCLDO_VOSEL_VA33_SHIFT 5
#define PMIC_RG_LCLDO_REMOTE_SENSE_VA33_MASK 0x1
#define PMIC_RG_LCLDO_REMOTE_SENSE_VA33_SHIFT 4
#define PMIC_RG_LCLDO_PDDIS_EN_VA33_MASK 0x1
#define PMIC_RG_LCLDO_PDDIS_EN_VA33_SHIFT 3
#define PMIC_RG_HCLDO_VOSEL_VA33_MASK 0x1
#define PMIC_RG_HCLDO_VOSEL_VA33_SHIFT 2
#define PMIC_RG_HCLDO_REMOTE_SENSE_VA33_MASK 0x1
#define PMIC_RG_HCLDO_REMOTE_SENSE_VA33_SHIFT 1
#define PMIC_RG_HCLDO_PDDIS_EN_VA33_MASK 0x1
#define PMIC_RG_HCLDO_PDDIS_EN_VA33_SHIFT 0
#define PMIC_RG_AUDPMU_RESERVED_VAUDP12_MASK 0xF
#define PMIC_RG_AUDPMU_RESERVED_VAUDP12_SHIFT 12
#define PMIC_RG_AUDPMU_RESERVED_VA28_MASK 0xF
#define PMIC_RG_AUDPMU_RESERVED_VA28_SHIFT 8
#define PMIC_RG_AUDPMU_RESERVED_VA33_MASK 0xF
#define PMIC_RG_AUDPMU_RESERVED_VA33_SHIFT 4
#define PMIC_RG_AUDPMU_RESERVED_VBAT_MASK 0xF
#define PMIC_RG_AUDPMU_RESERVED_VBAT_SHIFT 0
#define PMIC_DA_NVREG_EN_VAUDP12_MASK 0x1
#define PMIC_DA_NVREG_EN_VAUDP12_SHIFT 3
#define PMIC_RG_ACC_DCC_SEL_AUDGLB_VA28_MASK 0x1
#define PMIC_RG_ACC_DCC_SEL_AUDGLB_VA28_SHIFT 2
#define PMIC_RG_AUDGLB_PWRDN_VA28_MASK 0x1
#define PMIC_RG_AUDGLB_PWRDN_VA28_SHIFT 1
#define PMIC_RG_NVREG_PULL0V_VAUDP12_MASK 0x1
#define PMIC_RG_NVREG_PULL0V_VAUDP12_SHIFT 0
#define PMIC_RG_NCP_REMOTE_SENSE_VA18_MASK 0x1
#define PMIC_RG_NCP_REMOTE_SENSE_VA18_SHIFT 15
#define PMIC_DA_HCLDO_EN_VA33_MASK 0x1
#define PMIC_DA_HCLDO_EN_VA33_SHIFT 14
#define PMIC_DA_LCLDO_EN_VA33_MASK 0x1
#define PMIC_DA_LCLDO_EN_VA33_SHIFT 13
#define PMIC_DA_LCLDO_ENC_EN_VA28_MASK 0x1
#define PMIC_DA_LCLDO_ENC_EN_VA28_SHIFT 12
#define PMIC_DA_VBATPREREG_EN_VBAT_MASK 0x1
#define PMIC_DA_VBATPREREG_EN_VBAT_SHIFT 11
#define PMIC_RG_AUDPREAMPIDDTEST_MASK 0x3
#define PMIC_RG_AUDPREAMPIDDTEST_SHIFT 10
#define PMIC_RG_AUDPREAMPRPGATEST_MASK 0x1
#define PMIC_RG_AUDPREAMPRPGATEST_SHIFT 9
#define PMIC_RG_AUDPREAMPLPGATEST_MASK 0x1
#define PMIC_RG_AUDPREAMPLPGATEST_SHIFT 8
#define PMIC_RG_AUDPREAMPRINPUTSEL_MASK 0x7
#define PMIC_RG_AUDPREAMPRINPUTSEL_SHIFT 5
#define PMIC_RG_AUDPREAMPLINPUTSEL_MASK 0x7
#define PMIC_RG_AUDPREAMPLINPUTSEL_SHIFT 2
#define PMIC_RG_AUDPREAMPRON_MASK 0x1
#define PMIC_RG_AUDPREAMPRON_SHIFT 1
#define PMIC_RG_AUDPREAMPLON_MASK 0x1
#define PMIC_RG_AUDPREAMPLON_SHIFT 0
#define PMIC_RG_AUDADC3RDSTAGERESET_MASK 0x1
#define PMIC_RG_AUDADC3RDSTAGERESET_SHIFT 14
#define PMIC_RG_AUDADC2NDSTAGERESET_MASK 0x1
#define PMIC_RG_AUDADC2NDSTAGERESET_SHIFT 13
#define PMIC_RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3
#define PMIC_RG_AUDADC2NDSTAGEIDDTEST_SHIFT 11
#define PMIC_RG_AUDADC1STSTAGEIDDTEST_MASK 0x3
#define PMIC_RG_AUDADC1STSTAGEIDDTEST_SHIFT 9
#define PMIC_RG_AUDADCCLKSEL_MASK 0x1
#define PMIC_RG_AUDADCCLKSEL_SHIFT 8
#define PMIC_RG_AUDADCRINPUTSEL_MASK 0x7
#define PMIC_RG_AUDADCRINPUTSEL_SHIFT 5
#define PMIC_RG_AUDADCLINPUTSEL_MASK 0x7
#define PMIC_RG_AUDADCLINPUTSEL_SHIFT 2
#define PMIC_RG_AUDADCRPWRUP_MASK 0x1
#define PMIC_RG_AUDADCRPWRUP_SHIFT 1
#define PMIC_RG_AUDADCLPWRUP_MASK 0x1
#define PMIC_RG_AUDADCLPWRUP_SHIFT 0
#define PMIC_RG_AUDRCTUNELSEL_MASK 0x1
#define PMIC_RG_AUDRCTUNELSEL_SHIFT 13
#define PMIC_RG_AUDRCTUNEL_MASK 0x1F
#define PMIC_RG_AUDRCTUNEL_SHIFT 8
#define PMIC_RG_AUDADCFFBYPASS_MASK 0x1
#define PMIC_RG_AUDADCFFBYPASS_SHIFT 7
#define PMIC_RG_AUDADCBYPASS_MASK 0x1
#define PMIC_RG_AUDADCBYPASS_SHIFT 6
#define PMIC_RG_AUDADCFLASHIDDTEST_MASK 0x3
#define PMIC_RG_AUDADCFLASHIDDTEST_SHIFT 4
#define PMIC_RG_AUDADCREFBUFIDDTEST_MASK 0x3
#define PMIC_RG_AUDADCREFBUFIDDTEST_SHIFT 2
#define PMIC_RG_AUDADCDACIDDTEST_MASK 0x3
#define PMIC_RG_AUDADCDACIDDTEST_SHIFT 0
#define PMIC_RG_AUDADCDACFBCURRENT_MASK 0x1
#define PMIC_RG_AUDADCDACFBCURRENT_SHIFT 7
#define PMIC_RG_AUDADCNODEM_MASK 0x1
#define PMIC_RG_AUDADCNODEM_SHIFT 6
#define PMIC_RG_AUDRCTUNERSEL_MASK 0x1
#define PMIC_RG_AUDRCTUNERSEL_SHIFT 5
#define PMIC_RG_AUDRCTUNER_MASK 0x1F
#define PMIC_RG_AUDRCTUNER_SHIFT 0
#define PMIC_RG_AUDADCTESTDATA_MASK 0xFFFF
#define PMIC_RG_AUDADCTESTDATA_SHIFT 0
#define PMIC_RG_AUDADCDACNRZ_MASK 0x1
#define PMIC_RG_AUDADCDACNRZ_SHIFT 4
#define PMIC_RG_AUDADCFSRESET_MASK 0x1
#define PMIC_RG_AUDADCFSRESET_SHIFT 3
#define PMIC_RG_AUDADCDACTEST_MASK 0x1
#define PMIC_RG_AUDADCDACTEST_SHIFT 2
#define PMIC_RG_AUDADCNOPATEST_MASK 0x1
#define PMIC_RG_AUDADCNOPATEST_SHIFT 1
#define PMIC_RG_AUDADCWIDECM_MASK 0x1
#define PMIC_RG_AUDADCWIDECM_SHIFT 0
#define PMIC_RG_AUDSPAREVA18_MASK 0xFF
#define PMIC_RG_AUDSPAREVA18_SHIFT 8
#define PMIC_RG_AUDSPAREVA28_MASK 0xFF
#define PMIC_RG_AUDSPAREVA28_SHIFT 0
#define PMIC_RG_AUDSPAREVAUDP_MASK 0xF
#define PMIC_RG_AUDSPAREVAUDP_SHIFT 4
#define PMIC_RG_AUDSPAREVMIC_MASK 0xF
#define PMIC_RG_AUDSPAREVMIC_SHIFT 0
#define PMIC_RG_AUDMICBIASVREF_MASK 0x3
#define PMIC_RG_AUDMICBIASVREF_SHIFT 9
#define PMIC_RG_AUDPWDBMICBIAS_MASK 0x1
#define PMIC_RG_AUDPWDBMICBIAS_SHIFT 8
#define PMIC_RG_AUDDIGMICBIAS_MASK 0x3
#define PMIC_RG_AUDDIGMICBIAS_SHIFT 6
#define PMIC_RG_AUDDIGMICNDUTY_MASK 0x3
#define PMIC_RG_AUDDIGMICNDUTY_SHIFT 4
#define PMIC_RG_AUDDIGMICPDUTY_MASK 0x3
#define PMIC_RG_AUDDIGMICPDUTY_SHIFT 2
#define PMIC_RG_AUDDIGMICEN_MASK 0x1
#define PMIC_RG_AUDDIGMICEN_SHIFT 0
#define PMIC_RG_AUDLSBUFRMUTE_MASK 0x1
#define PMIC_RG_AUDLSBUFRMUTE_SHIFT 15
#define PMIC_RG_AUDLSBUFRGAIN_MASK 0x7
#define PMIC_RG_AUDLSBUFRGAIN_SHIFT 9
#define PMIC_RG_AUDLSBUFLMUTE_MASK 0x1
#define PMIC_RG_AUDLSBUFLMUTE_SHIFT 8
#define PMIC_RG_AUDLSBUFLGAIN_MASK 0x7
#define PMIC_RG_AUDLSBUFLGAIN_SHIFT 2
#define PMIC_RG_AUDLSBUFRPWRUP_MASK 0x1
#define PMIC_RG_AUDLSBUFRPWRUP_SHIFT 1
#define PMIC_RG_AUDLSBUFLPWRUP_MASK 0x1
#define PMIC_RG_AUDLSBUFLPWRUP_SHIFT 0
#define PMIC_RG_AUDLSBUF2IDDTEST_MASK 0x3
#define PMIC_RG_AUDLSBUF2IDDTEST_SHIFT 8
#define PMIC_RG_AUDLSBUFIDDTEST_MASK 0x3
#define PMIC_RG_AUDLSBUFIDDTEST_SHIFT 6
#define PMIC_RG_AUDLSBUFRINPUTSEL_MASK 0x7
#define PMIC_RG_AUDLSBUFRINPUTSEL_SHIFT 3
#define PMIC_RG_AUDLSBUFLINPUTSEL_MASK 0x7
#define PMIC_RG_AUDLSBUFLINPUTSEL_SHIFT 0
#define PMIC_RG_AUDENCSPAREVA18_MASK 0xFF
#define PMIC_RG_AUDENCSPAREVA18_SHIFT 8
#define PMIC_RG_AUDENCSPAREVA28_MASK 0xFF
#define PMIC_RG_AUDENCSPAREVA28_SHIFT 0
#define PMIC_RG_CLKSQ_MONEN_VA28_MASK 0x1
#define PMIC_RG_CLKSQ_MONEN_VA28_SHIFT 0
#define PMIC_RG_AUDENC_reserved_MASK 0xFF
#define PMIC_RG_AUDENC_reserved_SHIFT 8
#define PMIC_RG_AUDPREAMPR_reserved_MASK 0x1
#define PMIC_RG_AUDPREAMPR_reserved_SHIFT 7
#define PMIC_RG_AUDPREAMPRGAIN_MASK 0x7
#define PMIC_RG_AUDPREAMPRGAIN_SHIFT 4
#define PMIC_RG_AUDPREAMPL_reserved_MASK 0x1
#define PMIC_RG_AUDPREAMPL_reserved_SHIFT 3
#define PMIC_RG_AUDPREAMPLGAIN_MASK 0x7
#define PMIC_RG_AUDPREAMPLGAIN_SHIFT 0
#define PMIC_RG_AUDZCDMUXSEL_VAUDP12_MASK 0x7
#define PMIC_RG_AUDZCDMUXSEL_VAUDP12_SHIFT 8
#define PMIC_RG_AUDZCDCLKSEL_VAUDP12_MASK 0x1
#define PMIC_RG_AUDZCDCLKSEL_VAUDP12_SHIFT 7
#define PMIC_RG_AUDZCDTIMEOUTMODESEL_MASK 0x1
#define PMIC_RG_AUDZCDTIMEOUTMODESEL_SHIFT 6
#define PMIC_RG_AUDZCDGAINSTEPSIZE_MASK 0x3
#define PMIC_RG_AUDZCDGAINSTEPSIZE_SHIFT 4
#define PMIC_RG_AUDZCDGAINSTEPTIME_MASK 0x7
#define PMIC_RG_AUDZCDGAINSTEPTIME_SHIFT 1
#define PMIC_RG_AUDZCDENABLE_MASK 0x1
#define PMIC_RG_AUDZCDENABLE_SHIFT 0
#define PMIC_RG_AUDLINEGAIN_MASK 0xF
#define PMIC_RG_AUDLINEGAIN_SHIFT 0
#define PMIC_RG_AUDHPRGAIN_MASK 0xF
#define PMIC_RG_AUDHPRGAIN_SHIFT 8
#define PMIC_RG_AUDHPLGAIN_MASK 0xF
#define PMIC_RG_AUDHPLGAIN_SHIFT 0
#define PMIC_RG_AUDHSGAIN_MASK 0xF
#define PMIC_RG_AUDHSGAIN_SHIFT 0
#define PMIC_RG_AUDIVRGAIN_MASK 0x7
#define PMIC_RG_AUDIVRGAIN_SHIFT 8
#define PMIC_RG_AUDIVLGAIN_MASK 0x7
#define PMIC_RG_AUDIVLGAIN_SHIFT 0
#define PMIC_RG_AUDINTGAIN2_MASK 0x3F
#define PMIC_RG_AUDINTGAIN2_SHIFT 8
#define PMIC_RG_AUDINTGAIN1_MASK 0x3F
#define PMIC_RG_AUDINTGAIN1_SHIFT 0
#define PMIC_RG_DIVCKS_CHG_MASK 0x1
#define PMIC_RG_DIVCKS_CHG_SHIFT 13
#define PMIC_RG_DIVCKS_ON_MASK 0x1
#define PMIC_RG_DIVCKS_ON_SHIFT 12
#define PMIC_RG_DIVCKS_PRG_MASK 0x1FF
#define PMIC_RG_DIVCKS_PRG_SHIFT 0
#define PMIC_RG_PWD_NCP_MASK 0x1
#define PMIC_RG_PWD_NCP_SHIFT 0
#define PMIC_RG_DCXO_S2A_LOADC2_MASK 0x1
#define PMIC_RG_DCXO_S2A_LOADC2_SHIFT 14
#define PMIC_RG_DCXO_S2A_LDO_AFE_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_LDO_AFE_EN_SHIFT 13
#define PMIC_RG_DCXO_S2A_LDO_BB_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_LDO_BB_EN_SHIFT 12
#define PMIC_RG_DCXO_S2A_RF2_RCTB_MASK 0x1
#define PMIC_RG_DCXO_S2A_RF2_RCTB_SHIFT 11
#define PMIC_RG_DCXO_S2A_LDO_RF2_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_LDO_RF2_EN_SHIFT 10
#define PMIC_RG_DCXO_S2A_RF1_RCTB_MASK 0x1
#define PMIC_RG_DCXO_S2A_RF1_RCTB_SHIFT 9
#define PMIC_RG_DCXO_S2A_LDO_RF1_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_LDO_RF1_EN_SHIFT 8
#define PMIC_RG_DCXO_S2A_ACL_TARGET_MASK 0xF
#define PMIC_RG_DCXO_S2A_ACL_TARGET_SHIFT 4
#define PMIC_RG_DCXO_S2A_ACL_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_ACL_EN_SHIFT 3
#define PMIC_RG_DCXO_S2A_LDO_TOP_BYP_MASK 0x1
#define PMIC_RG_DCXO_S2A_LDO_TOP_BYP_SHIFT 2
#define PMIC_RG_DCXO_S2A_LDO_TOP_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_LDO_TOP_EN_SHIFT 1
#define PMIC_RG_DCXO_S2A_BANDGAP_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_BANDGAP_EN_SHIFT 0
#define PMIC_RG_DCXO_S2A_RSV_MASK 0x3
#define PMIC_RG_DCXO_S2A_RSV_SHIFT 14
#define PMIC_RG_DCXO_S2A_TMP1_C2_MASK 0xFF
#define PMIC_RG_DCXO_S2A_TMP1_C2_SHIFT 6
#define PMIC_RG_DCXO_S2A_TMP1_C1_MASK 0x7
#define PMIC_RG_DCXO_S2A_TMP1_C1_SHIFT 3
#define PMIC_RG_DCXO_S2A_TMP1_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP1_TIELOW_EN_SHIFT 2
#define PMIC_RG_DCXO_S2A_TMP1_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP1_PREBUF_EN_SHIFT 1
#define PMIC_RG_DCXO_S2A_TMP1_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP1_LDO_FPM_EN_SHIFT 0
#define PMIC_RG_DCXO_S2A_TMP1_FPMBUF_BIAS_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP1_FPMBUF_BIAS_EN_SHIFT 12
#define PMIC_RG_DCXO_S2A_TMP1_CAP_LOW_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP1_CAP_LOW_SHIFT 11
#define PMIC_RG_DCXO_S2A_TMP1_CAP_HIGH_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP1_CAP_HIGH_SHIFT 10
#define PMIC_RG_DCXO_S2A_TMP1_RSV_MASK 0x3
#define PMIC_RG_DCXO_S2A_TMP1_RSV_SHIFT 8
#define PMIC_RG_DCXO_S2A_TMP1_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_S2A_TMP1_ICONT_SHIFT 0
#define PMIC_RG_DCXO_S2A_TMP2_C2_MASK 0xFF
#define PMIC_RG_DCXO_S2A_TMP2_C2_SHIFT 6
#define PMIC_RG_DCXO_S2A_TMP2_C1_MASK 0x7
#define PMIC_RG_DCXO_S2A_TMP2_C1_SHIFT 3
#define PMIC_RG_DCXO_S2A_TMP2_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP2_TIELOW_EN_SHIFT 2
#define PMIC_RG_DCXO_S2A_TMP2_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP2_PREBUF_EN_SHIFT 1
#define PMIC_RG_DCXO_S2A_TMP2_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP2_LDO_FPM_EN_SHIFT 0
#define PMIC_RG_DCXO_S2A_TMP2_FPMBUF_BIAS_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP2_FPMBUF_BIAS_EN_SHIFT 12
#define PMIC_RG_DCXO_S2A_TMP2_CAP_LOW_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP2_CAP_LOW_SHIFT 11
#define PMIC_RG_DCXO_S2A_TMP2_CAP_HIGH_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP2_CAP_HIGH_SHIFT 10
#define PMIC_RG_DCXO_S2A_TMP2_RSV_MASK 0x3
#define PMIC_RG_DCXO_S2A_TMP2_RSV_SHIFT 8
#define PMIC_RG_DCXO_S2A_TMP2_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_S2A_TMP2_ICONT_SHIFT 0
#define PMIC_RG_DCXO_S2A_TMP3_C2_MASK 0xFF
#define PMIC_RG_DCXO_S2A_TMP3_C2_SHIFT 6
#define PMIC_RG_DCXO_S2A_TMP3_C1_MASK 0x7
#define PMIC_RG_DCXO_S2A_TMP3_C1_SHIFT 3
#define PMIC_RG_DCXO_S2A_TMP3_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP3_TIELOW_EN_SHIFT 2
#define PMIC_RG_DCXO_S2A_TMP3_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP3_PREBUF_EN_SHIFT 1
#define PMIC_RG_DCXO_S2A_TMP3_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP3_LDO_FPM_EN_SHIFT 0
#define PMIC_RG_DCXO_S2A_TMP3_FPMBUF_BIAS_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP3_FPMBUF_BIAS_EN_SHIFT 12
#define PMIC_RG_DCXO_S2A_TMP3_CAP_LOW_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP3_CAP_LOW_SHIFT 11
#define PMIC_RG_DCXO_S2A_TMP3_CAP_HIGH_MASK 0x1
#define PMIC_RG_DCXO_S2A_TMP3_CAP_HIGH_SHIFT 10
#define PMIC_RG_DCXO_S2A_TMP3_RSV_MASK 0x3
#define PMIC_RG_DCXO_S2A_TMP3_RSV_SHIFT 8
#define PMIC_RG_DCXO_S2A_TMP3_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_S2A_TMP3_ICONT_SHIFT 0
#define PMIC_RG_DCXO_S2A_FINAL_C2_MASK 0xFF
#define PMIC_RG_DCXO_S2A_FINAL_C2_SHIFT 6
#define PMIC_RG_DCXO_S2A_FINAL_C1_MASK 0x7
#define PMIC_RG_DCXO_S2A_FINAL_C1_SHIFT 3
#define PMIC_RG_DCXO_S2A_FINAL_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_FINAL_TIELOW_EN_SHIFT 2
#define PMIC_RG_DCXO_S2A_FINAL_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_FINAL_PREBUF_EN_SHIFT 1
#define PMIC_RG_DCXO_S2A_FINAL_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_FINAL_LDO_FPM_EN_SHIFT 0
#define PMIC_RG_DCXO_S2A_FINAL_FPMBUF_BIAS_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_FINAL_FPMBUF_BIAS_EN_SHIFT 12
#define PMIC_RG_DCXO_S2A_FINAL_CAP_LOW_MASK 0x1
#define PMIC_RG_DCXO_S2A_FINAL_CAP_LOW_SHIFT 11
#define PMIC_RG_DCXO_S2A_FINAL_CAP_HIGH_MASK 0x1
#define PMIC_RG_DCXO_S2A_FINAL_CAP_HIGH_SHIFT 10
#define PMIC_RG_DCXO_S2A_FINAL_RSV_MASK 0x3
#define PMIC_RG_DCXO_S2A_FINAL_RSV_SHIFT 8
#define PMIC_RG_DCXO_S2A_FINAL_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_S2A_FINAL_ICONT_SHIFT 0
#define PMIC_RG_DCXO_A2S_LOADC2_MASK 0x1
#define PMIC_RG_DCXO_A2S_LOADC2_SHIFT 14
#define PMIC_RG_DCXO_A2S_LDO_AFE_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_LDO_AFE_EN_SHIFT 13
#define PMIC_RG_DCXO_A2S_LDO_BB_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_LDO_BB_EN_SHIFT 12
#define PMIC_RG_DCXO_A2S_RF2_RCTB_MASK 0x1
#define PMIC_RG_DCXO_A2S_RF2_RCTB_SHIFT 11
#define PMIC_RG_DCXO_A2S_LDO_RF2_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_LDO_RF2_EN_SHIFT 10
#define PMIC_RG_DCXO_A2S_RF1_RCTB_MASK 0x1
#define PMIC_RG_DCXO_A2S_RF1_RCTB_SHIFT 9
#define PMIC_RG_DCXO_A2S_LDO_RF1_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_LDO_RF1_EN_SHIFT 8
#define PMIC_RG_DCXO_A2S_ACL_TARGET_MASK 0xF
#define PMIC_RG_DCXO_A2S_ACL_TARGET_SHIFT 4
#define PMIC_RG_DCXO_A2S_ACL_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_ACL_EN_SHIFT 3
#define PMIC_RG_DCXO_A2S_LDO_TOP_BYP_MASK 0x1
#define PMIC_RG_DCXO_A2S_LDO_TOP_BYP_SHIFT 2
#define PMIC_RG_DCXO_A2S_LDO_TOP_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_LDO_TOP_EN_SHIFT 1
#define PMIC_RG_DCXO_A2S_BANDGAP_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_BANDGAP_EN_SHIFT 0
#define PMIC_RG_DCXO_A2S_RSV_MASK 0x3
#define PMIC_RG_DCXO_A2S_RSV_SHIFT 14
#define PMIC_RG_DCXO_A2S_TMP1_C2_MASK 0xFF
#define PMIC_RG_DCXO_A2S_TMP1_C2_SHIFT 6
#define PMIC_RG_DCXO_A2S_TMP1_C1_MASK 0x7
#define PMIC_RG_DCXO_A2S_TMP1_C1_SHIFT 3
#define PMIC_RG_DCXO_A2S_TMP1_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_TMP1_TIELOW_EN_SHIFT 2
#define PMIC_RG_DCXO_A2S_TMP1_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_TMP1_PREBUF_EN_SHIFT 1
#define PMIC_RG_DCXO_A2S_TMP1_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_TMP1_LDO_FPM_EN_SHIFT 0
#define PMIC_RG_DCXO_A2S_TMP1_FPMBUF_BIAS_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_TMP1_FPMBUF_BIAS_EN_SHIFT 10
#define PMIC_RG_DCXO_A2S_TMP1_RSV_MASK 0x3
#define PMIC_RG_DCXO_A2S_TMP1_RSV_SHIFT 8
#define PMIC_RG_DCXO_A2S_TMP1_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_A2S_TMP1_ICONT_SHIFT 0
#define PMIC_RG_DCXO_A2S_TMP2_C2_MASK 0xFF
#define PMIC_RG_DCXO_A2S_TMP2_C2_SHIFT 6
#define PMIC_RG_DCXO_A2S_TMP2_C1_MASK 0x7
#define PMIC_RG_DCXO_A2S_TMP2_C1_SHIFT 3
#define PMIC_RG_DCXO_A2S_TMP2_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_TMP2_TIELOW_EN_SHIFT 2
#define PMIC_RG_DCXO_A2S_TMP2_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_TMP2_PREBUF_EN_SHIFT 1
#define PMIC_RG_DCXO_A2S_TMP2_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_TMP2_LDO_FPM_EN_SHIFT 0
#define PMIC_RG_DCXO_A2S_TMP2_FPMBUF_BIAS_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_TMP2_FPMBUF_BIAS_EN_SHIFT 10
#define PMIC_RG_DCXO_A2S_TMP2_RSV_MASK 0x3
#define PMIC_RG_DCXO_A2S_TMP2_RSV_SHIFT 8
#define PMIC_RG_DCXO_A2S_TMP2_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_A2S_TMP2_ICONT_SHIFT 0
#define PMIC_RG_DCXO_A2S_TMP3_C2_MASK 0xFF
#define PMIC_RG_DCXO_A2S_TMP3_C2_SHIFT 6
#define PMIC_RG_DCXO_A2S_TMP3_C1_MASK 0x7
#define PMIC_RG_DCXO_A2S_TMP3_C1_SHIFT 3
#define PMIC_RG_DCXO_A2S_TMP3_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_TMP3_TIELOW_EN_SHIFT 2
#define PMIC_RG_DCXO_A2S_TMP3_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_TMP3_PREBUF_EN_SHIFT 1
#define PMIC_RG_DCXO_A2S_TMP3_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_TMP3_LDO_FPM_EN_SHIFT 0
#define PMIC_RG_DCXO_A2S_TMP3_FPMBUF_BIAS_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_TMP3_FPMBUF_BIAS_EN_SHIFT 10
#define PMIC_RG_DCXO_A2S_TMP3_RSV_MASK 0x3
#define PMIC_RG_DCXO_A2S_TMP3_RSV_SHIFT 8
#define PMIC_RG_DCXO_A2S_TMP3_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_A2S_TMP3_ICONT_SHIFT 0
#define PMIC_RG_DCXO_A2S_FINAL_C2_MASK 0xFF
#define PMIC_RG_DCXO_A2S_FINAL_C2_SHIFT 6
#define PMIC_RG_DCXO_A2S_FINAL_C1_MASK 0x7
#define PMIC_RG_DCXO_A2S_FINAL_C1_SHIFT 3
#define PMIC_RG_DCXO_A2S_FINAL_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_FINAL_TIELOW_EN_SHIFT 2
#define PMIC_RG_DCXO_A2S_FINAL_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_FINAL_PREBUF_EN_SHIFT 1
#define PMIC_RG_DCXO_A2S_FINAL_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_FINAL_LDO_FPM_EN_SHIFT 0
#define PMIC_RG_DCXO_A2S_FINAL_FPMBUF_BIAS_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_FINAL_FPMBUF_BIAS_EN_SHIFT 10
#define PMIC_RG_DCXO_A2S_FINAL_RSV_MASK 0x3
#define PMIC_RG_DCXO_A2S_FINAL_RSV_SHIFT 8
#define PMIC_RG_DCXO_A2S_FINAL_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_A2S_FINAL_ICONT_SHIFT 0
#define PMIC_RG_DCXO_POR2_LDO_RF2_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_LDO_RF2_EN_SHIFT 15
#define PMIC_RG_DCXO_POR2_RF1_RCTB_MASK 0x1
#define PMIC_RG_DCXO_POR2_RF1_RCTB_SHIFT 14
#define PMIC_RG_DCXO_POR2_LDO_RF1_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_LDO_RF1_EN_SHIFT 13
#define PMIC_RG_DCXO_POR2_ACL_TARGET_MASK 0xF
#define PMIC_RG_DCXO_POR2_ACL_TARGET_SHIFT 9
#define PMIC_RG_DCXO_POR2_ACL_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_ACL_EN_SHIFT 8
#define PMIC_RG_DCXO_POR2_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_TIELOW_EN_SHIFT 7
#define PMIC_RG_DCXO_POR2_DIGBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_DIGBUF_EN_SHIFT 6
#define PMIC_RG_DCXO_POR2_STARTUP_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_STARTUP_EN_SHIFT 5
#define PMIC_RG_DCXO_POR2_CURRENT_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_CURRENT_EN_SHIFT 4
#define PMIC_RG_DCXO_POR2_LDO_TOP_BYP_MASK 0x1
#define PMIC_RG_DCXO_POR2_LDO_TOP_BYP_SHIFT 3
#define PMIC_RG_DCXO_POR2_LDO_TOP_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_LDO_TOP_EN_SHIFT 2
#define PMIC_RG_DCXO_POR2_BANDGAP_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_BANDGAP_EN_SHIFT 1
#define PMIC_RG_DCXO_POR2_RESET_MASK 0x1
#define PMIC_RG_DCXO_POR2_RESET_SHIFT 0
#define PMIC_RG_DCXO_POR2_C2_MASK 0xFF
#define PMIC_RG_DCXO_POR2_C2_SHIFT 8
#define PMIC_RG_DCXO_POR2_RSV_MASK 0x3
#define PMIC_RG_DCXO_POR2_RSV_SHIFT 6
#define PMIC_RG_DCXO_POR2_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_PREBUF_EN_SHIFT 5
#define PMIC_RG_DCXO_POR2_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_LDO_FPM_EN_SHIFT 4
#define PMIC_RG_DCXO_POR2_LOADC2_MASK 0x1
#define PMIC_RG_DCXO_POR2_LOADC2_SHIFT 3
#define PMIC_RG_DCXO_POR2_LDO_AFE_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_LDO_AFE_EN_SHIFT 2
#define PMIC_RG_DCXO_POR2_LDO_BB_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_LDO_BB_EN_SHIFT 1
#define PMIC_RG_DCXO_POR2_RF2_RCTB_MASK 0x1
#define PMIC_RG_DCXO_POR2_RF2_RCTB_SHIFT 0
#define PMIC_RG_DCXO_POR2_FPMBUF_BIAS_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_FPMBUF_BIAS_EN_SHIFT 15
#define PMIC_RG_DCXO_POR2_LDO_BUFTOP_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_LDO_BUFTOP_EN_SHIFT 14
#define PMIC_RG_DCXO_POR2_LDO_FPM_RCTB_MASK 0x1
#define PMIC_RG_DCXO_POR2_LDO_FPM_RCTB_SHIFT 13
#define PMIC_RG_DCXO_POR2_BANDGAP_RCTB_MASK 0x1
#define PMIC_RG_DCXO_POR2_BANDGAP_RCTB_SHIFT 12
#define PMIC_RG_DCXO_POR2_CURRENT_RCTB_MASK 0x1
#define PMIC_RG_DCXO_POR2_CURRENT_RCTB_SHIFT 11
#define PMIC_RG_DCXO_POR2_C1_MASK 0x7
#define PMIC_RG_DCXO_POR2_C1_SHIFT 8
#define PMIC_RG_DCXO_POR2_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_POR2_ICONT_SHIFT 0
#define PMIC_RG_DCXO_POR2_TMP1_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP1_TIELOW_EN_SHIFT 13
#define PMIC_RG_DCXO_POR2_TMP1_C2_MASK 0xFF
#define PMIC_RG_DCXO_POR2_TMP1_C2_SHIFT 5
#define PMIC_RG_DCXO_POR2_TMP1_C1_MASK 0x7
#define PMIC_RG_DCXO_POR2_TMP1_C1_SHIFT 2
#define PMIC_RG_DCXO_POR2_TMP1_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP1_PREBUF_EN_SHIFT 1
#define PMIC_RG_DCXO_POR2_TMP1_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP1_LDO_FPM_EN_SHIFT 0
#define PMIC_RG_DCXO_POR2_TMP1_FPMBUF_BIAS_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP1_FPMBUF_BIAS_EN_SHIFT 12
#define PMIC_RG_DCXO_POR2_TMP1_CAP_LOW_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP1_CAP_LOW_SHIFT 11
#define PMIC_RG_DCXO_POR2_TMP1_CAP_HIGH_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP1_CAP_HIGH_SHIFT 10
#define PMIC_RG_DCXO_POR2_TMP1_RSV_MASK 0x3
#define PMIC_RG_DCXO_POR2_TMP1_RSV_SHIFT 8
#define PMIC_RG_DCXO_POR2_TMP1_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_POR2_TMP1_ICONT_SHIFT 0
#define PMIC_RG_DCXO_POR2_TMP2_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP2_TIELOW_EN_SHIFT 13
#define PMIC_RG_DCXO_POR2_TMP2_C2_MASK 0xFF
#define PMIC_RG_DCXO_POR2_TMP2_C2_SHIFT 5
#define PMIC_RG_DCXO_POR2_TMP2_C1_MASK 0x7
#define PMIC_RG_DCXO_POR2_TMP2_C1_SHIFT 2
#define PMIC_RG_DCXO_POR2_TMP2_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP2_PREBUF_EN_SHIFT 1
#define PMIC_RG_DCXO_POR2_TMP2_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP2_LDO_FPM_EN_SHIFT 0
#define PMIC_RG_DCXO_POR2_TMP2_FPMBUF_BIAS_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP2_FPMBUF_BIAS_EN_SHIFT 12
#define PMIC_RG_DCXO_POR2_TMP2_CAP_LOW_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP2_CAP_LOW_SHIFT 11
#define PMIC_RG_DCXO_POR2_TMP2_CAP_HIGH_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP2_CAP_HIGH_SHIFT 10
#define PMIC_RG_DCXO_POR2_TMP2_RSV_MASK 0x3
#define PMIC_RG_DCXO_POR2_TMP2_RSV_SHIFT 8
#define PMIC_RG_DCXO_POR2_TMP2_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_POR2_TMP2_ICONT_SHIFT 0
#define PMIC_RG_DCXO_POR2_TMP3_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP3_TIELOW_EN_SHIFT 13
#define PMIC_RG_DCXO_POR2_TMP3_C2_MASK 0xFF
#define PMIC_RG_DCXO_POR2_TMP3_C2_SHIFT 5
#define PMIC_RG_DCXO_POR2_TMP3_C1_MASK 0x7
#define PMIC_RG_DCXO_POR2_TMP3_C1_SHIFT 2
#define PMIC_RG_DCXO_POR2_TMP3_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP3_PREBUF_EN_SHIFT 1
#define PMIC_RG_DCXO_POR2_TMP3_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP3_LDO_FPM_EN_SHIFT 0
#define PMIC_RG_DCXO_POR2_TMP3_FPMBUF_BIAS_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP3_FPMBUF_BIAS_EN_SHIFT 12
#define PMIC_RG_DCXO_POR2_TMP3_CAP_LOW_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP3_CAP_LOW_SHIFT 11
#define PMIC_RG_DCXO_POR2_TMP3_CAP_HIGH_MASK 0x1
#define PMIC_RG_DCXO_POR2_TMP3_CAP_HIGH_SHIFT 10
#define PMIC_RG_DCXO_POR2_TMP3_RSV_MASK 0x3
#define PMIC_RG_DCXO_POR2_TMP3_RSV_SHIFT 8
#define PMIC_RG_DCXO_POR2_TMP3_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_POR2_TMP3_ICONT_SHIFT 0
#define PMIC_RG_DCXO_POR2_FINAL_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_FINAL_TIELOW_EN_SHIFT 13
#define PMIC_RG_DCXO_POR2_FINAL_C2_MASK 0xFF
#define PMIC_RG_DCXO_POR2_FINAL_C2_SHIFT 5
#define PMIC_RG_DCXO_POR2_FINAL_C1_MASK 0x7
#define PMIC_RG_DCXO_POR2_FINAL_C1_SHIFT 2
#define PMIC_RG_DCXO_POR2_FINAL_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_FINAL_PREBUF_EN_SHIFT 1
#define PMIC_RG_DCXO_POR2_FINAL_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_FINAL_LDO_FPM_EN_SHIFT 0
#define PMIC_RG_DCXO_POR2_FINAL_FPMBUF_BIAS_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_FINAL_FPMBUF_BIAS_EN_SHIFT 12
#define PMIC_RG_DCXO_POR2_FINAL_CAP_LOW_MASK 0x1
#define PMIC_RG_DCXO_POR2_FINAL_CAP_LOW_SHIFT 11
#define PMIC_RG_DCXO_POR2_FINAL_CAP_HIGH_MASK 0x1
#define PMIC_RG_DCXO_POR2_FINAL_CAP_HIGH_SHIFT 10
#define PMIC_RG_DCXO_POR2_FINAL_RSV_MASK 0x3
#define PMIC_RG_DCXO_POR2_FINAL_RSV_SHIFT 8
#define PMIC_RG_DCXO_POR2_FINAL_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_POR2_FINAL_ICONT_SHIFT 0
#define PMIC_RG_DCXO_LDO_BUFTOP_EN_MASK 0x1
#define PMIC_RG_DCXO_LDO_BUFTOP_EN_SHIFT 15
#define PMIC_RG_DCXO_LDO_RF2_REG_EN_MASK 0x1
#define PMIC_RG_DCXO_LDO_RF2_REG_EN_SHIFT 14
#define PMIC_RG_DCXO_LDO_RF1_REG_EN_MASK 0x1
#define PMIC_RG_DCXO_LDO_RF1_REG_EN_SHIFT 13
#define PMIC_RG_DCXO_LDO_DBB_REG_EN_MASK 0x1
#define PMIC_RG_DCXO_LDO_DBB_REG_EN_SHIFT 12
#define PMIC_RG_DCXO_C1_MASK 0x7
#define PMIC_RG_DCXO_C1_SHIFT 9
#define PMIC_RG_DCXO_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_PREBUF_EN_SHIFT 8
#define PMIC_RG_DCXO_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_LDO_FPM_EN_SHIFT 7
#define PMIC_RG_DCXO_DIGBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_DIGBUF_EN_SHIFT 6
#define PMIC_RG_DCXO_STARTUP_EN_MASK 0x1
#define PMIC_RG_DCXO_STARTUP_EN_SHIFT 5
#define PMIC_RG_DCXO_CURRENT_EN_MASK 0x1
#define PMIC_RG_DCXO_CURRENT_EN_SHIFT 4
#define PMIC_RG_DCXO_LDO_TOP_BYP_MASK 0x1
#define PMIC_RG_DCXO_LDO_TOP_BYP_SHIFT 3
#define PMIC_RG_DCXO_LDO_TOP_EN_MASK 0x1
#define PMIC_RG_DCXO_LDO_TOP_EN_SHIFT 2
#define PMIC_RG_DCXO_BANDGAP_EN_MASK 0x1
#define PMIC_RG_DCXO_BANDGAP_EN_SHIFT 1
#define PMIC_RG_DCXO_RESET_MASK 0x1
#define PMIC_RG_DCXO_RESET_SHIFT 0
#define PMIC_RG_DCXO_ICONT_MASK 0xFF
#define PMIC_RG_DCXO_ICONT_SHIFT 8
#define PMIC_RG_DCXO_C2_MASK 0xFF
#define PMIC_RG_DCXO_C2_SHIFT 0
#define PMIC_RG_DCXO_C2_UNTRIM_MASK 0x1
#define PMIC_RG_DCXO_C2_UNTRIM_SHIFT 15
#define PMIC_RG_DCXO_RSV_MASK 0x7
#define PMIC_RG_DCXO_RSV_SHIFT 12
#define PMIC_RG_DCXO_ACL_TARGET_MASK 0xF
#define PMIC_RG_DCXO_ACL_TARGET_SHIFT 8
#define PMIC_RG_DCXO_ACL_EN_MASK 0x1
#define PMIC_RG_DCXO_ACL_EN_SHIFT 7
#define PMIC_RG_DCXO_LDO_AFE_EN_MASK 0x1
#define PMIC_RG_DCXO_LDO_AFE_EN_SHIFT 6
#define PMIC_RG_DCXO_LDO_BB_EN_MASK 0x1
#define PMIC_RG_DCXO_LDO_BB_EN_SHIFT 5
#define PMIC_RG_DCXO_LDO_RF2_RCTB_MASK 0x1
#define PMIC_RG_DCXO_LDO_RF2_RCTB_SHIFT 4
#define PMIC_RG_DCXO_LDO_RF2_EN_MASK 0x1
#define PMIC_RG_DCXO_LDO_RF2_EN_SHIFT 3
#define PMIC_RG_DCXO_LDO_RF1_RCTB_MASK 0x1
#define PMIC_RG_DCXO_LDO_RF1_RCTB_SHIFT 2
#define PMIC_RG_DCXO_LDO_RF1_EN_MASK 0x1
#define PMIC_RG_DCXO_LDO_RF1_EN_SHIFT 1
#define PMIC_RG_DCXO_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_TIELOW_EN_SHIFT 0
#define PMIC_RG_DCXO_LDO_FPM_RCTB_MASK 0x1
#define PMIC_RG_DCXO_LDO_FPM_RCTB_SHIFT 15
#define PMIC_RG_DCXO_BANDGAP_RCTB_MASK 0x1
#define PMIC_RG_DCXO_BANDGAP_RCTB_SHIFT 14
#define PMIC_RG_DCXO_CURRENT_RCTB_MASK 0x1
#define PMIC_RG_DCXO_CURRENT_RCTB_SHIFT 13
#define PMIC_RG_DCXO_FPMBUF_BIAS_EN_SYNC_MASK 0x1
#define PMIC_RG_DCXO_FPMBUF_BIAS_EN_SYNC_SHIFT 12
#define PMIC_RG_DCXO_CAP_LOW_SYNC_MASK 0x1
#define PMIC_RG_DCXO_CAP_LOW_SYNC_SHIFT 11
#define PMIC_RG_DCXO_CAP_HIGH_SYNC_MASK 0x1
#define PMIC_RG_DCXO_CAP_HIGH_SYNC_SHIFT 10
#define PMIC_RG_DCXO_C1C2_SYNC_EN_MASK 0x1
#define PMIC_RG_DCXO_C1C2_SYNC_EN_SHIFT 9
#define PMIC_RG_DCXO_SYNC_EN_MASK 0x1
#define PMIC_RG_DCXO_SYNC_EN_SHIFT 8
#define PMIC_RG_DCXO_FSM_C2_MASK 0xFF
#define PMIC_RG_DCXO_FSM_C2_SHIFT 0
#define PMIC_RG_DCXO_MANUAL_LDO_RF2_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_LDO_RF2_EN_SHIFT 15
#define PMIC_RG_DCXO_MANUAL_LDO_RF1_RCTB_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_LDO_RF1_RCTB_SHIFT 14
#define PMIC_RG_DCXO_MANUAL_LDO_RF1_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_LDO_RF1_EN_SHIFT 13
#define PMIC_RG_DCXO_MANUAL_TIELOW_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_TIELOW_EN_SHIFT 12
#define PMIC_RG_DCXO_MANUAL_ICONT_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_ICONT_SHIFT 11
#define PMIC_RG_DCXO_MANUAL_C2_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_C2_SHIFT 10
#define PMIC_RG_DCXO_MANUAL_C1_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_C1_SHIFT 9
#define PMIC_RG_DCXO_MANUAL_PREBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_PREBUF_EN_SHIFT 8
#define PMIC_RG_DCXO_MANUAL_LDO_FPM_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_LDO_FPM_EN_SHIFT 7
#define PMIC_RG_DCXO_MANUAL_DIGBUF_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_DIGBUF_EN_SHIFT 6
#define PMIC_RG_DCXO_MANUAL_STARTUP_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_STARTUP_EN_SHIFT 5
#define PMIC_RG_DCXO_MANUAL_CURRENT_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_CURRENT_EN_SHIFT 4
#define PMIC_RG_DCXO_MANUAL_LDO_TOP_BYP_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_LDO_TOP_BYP_SHIFT 3
#define PMIC_RG_DCXO_MANUAL_LDO_TOP_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_LDO_TOP_EN_SHIFT 2
#define PMIC_RG_DCXO_MANUAL_BANDGAP_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_BANDGAP_EN_SHIFT 1
#define PMIC_RG_DCXO_MANUAL_RESET_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_RESET_SHIFT 0
#define PMIC_RG_DCXO_MANUAL_LDO_FPM_RCTB_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_LDO_FPM_RCTB_SHIFT 15
#define PMIC_RG_DCXO_MANUAL_BANDGAP_RCTB_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_BANDGAP_RCTB_SHIFT 14
#define PMIC_RG_DCXO_MANUAL_CURRENT_RCTB_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_CURRENT_RCTB_SHIFT 13
#define PMIC_RG_DCXO_MANUAL_FPMBUF_BIAS_EN_SYNC_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_FPMBUF_BIAS_EN_SYNC_SHIFT 12
#define PMIC_RG_DCXO_MANUAL_CAP_LOW_SYNC_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_CAP_LOW_SYNC_SHIFT 11
#define PMIC_RG_DCXO_MANUAL_CAP_HIGH_SYNC_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_CAP_HIGH_SYNC_SHIFT 10
#define PMIC_RG_DCXO_MANUAL_C1C2_SYNC_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_C1C2_SYNC_EN_SHIFT 9
#define PMIC_RG_DCXO_MANUAL_SYNC_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_SYNC_EN_SHIFT 8
#define PMIC_RG_DCXO_MANUAL_RSV_MASK 0x7
#define PMIC_RG_DCXO_MANUAL_RSV_SHIFT 5
#define PMIC_RG_DCXO_MANUAL_ACL_TARGET_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_ACL_TARGET_SHIFT 4
#define PMIC_RG_DCXO_MANUAL_ACL_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_ACL_EN_SHIFT 3
#define PMIC_RG_DCXO_MANUAL_LDO_AFE_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_LDO_AFE_EN_SHIFT 2
#define PMIC_RG_DCXO_MANUAL_LDO_BB_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_LDO_BB_EN_SHIFT 1
#define PMIC_RG_DCXO_MANUAL_LDO_RF2_RCTB_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_LDO_RF2_RCTB_SHIFT 0
#define PMIC_RG_DCXO_MANUAL_LDO_BUFTOP_EN_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_LDO_BUFTOP_EN_SHIFT 0
#define PMIC_RG_DCXO_LDO_RF1_V_MASK 0x3
#define PMIC_RG_DCXO_LDO_RF1_V_SHIFT 14
#define PMIC_RG_DCXO_LDO_LPM_V_MASK 0x3
#define PMIC_RG_DCXO_LDO_LPM_V_SHIFT 12
#define PMIC_RG_DCXO_LDO_FPM_V_MASK 0x3
#define PMIC_RG_DCXO_LDO_FPM_V_SHIFT 10
#define PMIC_RG_DCXO_LDO_TOP_V_MASK 0x3
#define PMIC_RG_DCXO_LDO_TOP_V_SHIFT 8
#define PMIC_RG_DCXO_VG_V_MASK 0x3
#define PMIC_RG_DCXO_VG_V_SHIFT 6
#define PMIC_RG_DCXO_LDO_AFE_BYP_MASK 0x1
#define PMIC_RG_DCXO_LDO_AFE_BYP_SHIFT 5
#define PMIC_RG_DCXO_LDO_BB_BYP_MASK 0x1
#define PMIC_RG_DCXO_LDO_BB_BYP_SHIFT 4
#define PMIC_RG_DCXO_LDO_RF2_BYP_MASK 0x1
#define PMIC_RG_DCXO_LDO_RF2_BYP_SHIFT 3
#define PMIC_RG_DCXO_LDO_RF1_BYP_MASK 0x1
#define PMIC_RG_DCXO_LDO_RF1_BYP_SHIFT 2
#define PMIC_RG_DCXO_LDO_LPM_BYP_MASK 0x1
#define PMIC_RG_DCXO_LDO_LPM_BYP_SHIFT 1
#define PMIC_RG_DCXO_LDO_LPM_EN_MASK 0x1
#define PMIC_RG_DCXO_LDO_LPM_EN_SHIFT 0
#define PMIC_RG_DCXO_TEST_EN_MASK 0x1
#define PMIC_RG_DCXO_TEST_EN_SHIFT 15
#define PMIC_RG_DCXO_ATTEN_AFE_MASK 0x3
#define PMIC_RG_DCXO_ATTEN_AFE_SHIFT 13
#define PMIC_RG_DCXO_ATTEN_BB_MASK 0x3
#define PMIC_RG_DCXO_ATTEN_BB_SHIFT 11
#define PMIC_RG_DCXO_ATTEN_RF2_MASK 0x3
#define PMIC_RG_DCXO_ATTEN_RF2_SHIFT 9
#define PMIC_RG_DCXO_ATTEN_RF1_MASK 0x7
#define PMIC_RG_DCXO_ATTEN_RF1_SHIFT 6
#define PMIC_RG_DCXO_LDO_AFE_V_MASK 0x3
#define PMIC_RG_DCXO_LDO_AFE_V_SHIFT 4
#define PMIC_RG_DCXO_LDO_BB_V_MASK 0x3
#define PMIC_RG_DCXO_LDO_BB_V_SHIFT 2
#define PMIC_RG_DCXO_LDO_RF2_V_MASK 0x3
#define PMIC_RG_DCXO_LDO_RF2_V_SHIFT 0
#define PMIC_RG_DCXO_TEST_SEL_MASK 0xFFFF
#define PMIC_RG_DCXO_TEST_SEL_SHIFT 0
#define PMIC_RG_DCXO_FLOAT_CAP_MASK 0x1
#define PMIC_RG_DCXO_FLOAT_CAP_SHIFT 15
#define PMIC_RG_DCXO_SYNC_CKINV_MASK 0x1
#define PMIC_RG_DCXO_SYNC_CKINV_SHIFT 14
#define PMIC_RG_DCXO_SYNC_BYP_MASK 0x1
#define PMIC_RG_DCXO_SYNC_BYP_SHIFT 13
#define PMIC_RG_DCXO_LDO_FPM_BYP_MASK 0x1
#define PMIC_RG_DCXO_LDO_FPM_BYP_SHIFT 12
#define PMIC_RG_DCXO_LDO_BUFTOP_V_MASK 0x3
#define PMIC_RG_DCXO_LDO_BUFTOP_V_SHIFT 10
#define PMIC_RG_DCXO_LDO_BUFTOP_BYP_MASK 0x1
#define PMIC_RG_DCXO_LDO_BUFTOP_BYP_SHIFT 9
#define PMIC_RG_DCXO_AUDIO_TEST_EN_MASK 0x1
#define PMIC_RG_DCXO_AUDIO_TEST_EN_SHIFT 8
#define PMIC_RG_DCXO_RESERVED_MASK 0xFF
#define PMIC_RG_DCXO_RESERVED_SHIFT 0
#define PMIC_RG_DCXO_RESERVED1_MASK 0xF
#define PMIC_RG_DCXO_RESERVED1_SHIFT 12
#define PMIC_RG_DCXO_RESERVED0_MASK 0xF
#define PMIC_RG_DCXO_RESERVED0_SHIFT 8
#define PMIC_RG_DCXO_FPMBUF_BIASR_MASK 0x3
#define PMIC_RG_DCXO_FPMBUF_BIASR_SHIFT 6
#define PMIC_RG_DCXO_AFE_CKINV_MASK 0x1
#define PMIC_RG_DCXO_AFE_CKINV_SHIFT 5
#define PMIC_RG_DCXO_BB_CKINV_MASK 0x1
#define PMIC_RG_DCXO_BB_CKINV_SHIFT 4
#define PMIC_RG_DCXO_RF2_CKINV_MASK 0x1
#define PMIC_RG_DCXO_RF2_CKINV_SHIFT 3
#define PMIC_RG_DCXO_BUFMODE_MASK 0x1
#define PMIC_RG_DCXO_BUFMODE_SHIFT 2
#define PMIC_RG_DCXO_C1C2_SYNC_CKINV_MASK 0x1
#define PMIC_RG_DCXO_C1C2_SYNC_CKINV_SHIFT 1
#define PMIC_RG_DCXO_C1C2_SYNC_BYP_MASK 0x1
#define PMIC_RG_DCXO_C1C2_SYNC_BYP_SHIFT 0
#define PMIC_RG_DCXO_FT_TRIM_OPTION_MASK 0x7
#define PMIC_RG_DCXO_FT_TRIM_OPTION_SHIFT 12
#define PMIC_RG_DCXO_FT_FREQ_TRIM_START_MASK 0x1
#define PMIC_RG_DCXO_FT_FREQ_TRIM_START_SHIFT 11
#define PMIC_RG_DCXO_ACL_BIT_SWAP_MASK 0x1
#define PMIC_RG_DCXO_ACL_BIT_SWAP_SHIFT 10
#define PMIC_RG_DCXO_ACL_BIT_END_MASK 0x7
#define PMIC_RG_DCXO_ACL_BIT_END_SHIFT 7
#define PMIC_RG_DCXO_ACL_BIT_START_MASK 0x7
#define PMIC_RG_DCXO_ACL_BIT_START_SHIFT 4
#define PMIC_RG_DCXO_MANUAL_ACL_START_MASK 0x1
#define PMIC_RG_DCXO_MANUAL_ACL_START_SHIFT 3
#define PMIC_RG_DCXO_OFF_32K_OUTPUT_MASK 0x1
#define PMIC_RG_DCXO_OFF_32K_OUTPUT_SHIFT 2
#define PMIC_RG_DCXO_TEST_SLEEP_MODE_MASK 0x1
#define PMIC_RG_DCXO_TEST_SLEEP_MODE_SHIFT 1
#define PMIC_RG_DCXO_TEST_MODE_MASK 0x1
#define PMIC_RG_DCXO_TEST_MODE_SHIFT 0
#define PMIC_RG_DCXO_CK_CHG_DELAY_MASK 0xFF
#define PMIC_RG_DCXO_CK_CHG_DELAY_SHIFT 8
#define PMIC_RG_DCXO_FT_FREQ_TRIM_STEP_START_MASK 0x1
#define PMIC_RG_DCXO_FT_FREQ_TRIM_STEP_START_SHIFT 7
#define PMIC_RG_DCXO_FT_FREQ_TRIM_MANUAL_MASK 0x1
#define PMIC_RG_DCXO_FT_FREQ_TRIM_MANUAL_SHIFT 6
#define PMIC_RG_DCXO_FT_TRIM_BIT_END_MASK 0x7
#define PMIC_RG_DCXO_FT_TRIM_BIT_END_SHIFT 3
#define PMIC_RG_DCXO_FT_TRIM_BIT_START_MASK 0x7
#define PMIC_RG_DCXO_FT_TRIM_BIT_START_SHIFT 0
#define PMIC_RG_DCXO_32K_RESIDUAL_MASK 0x3FFF
#define PMIC_RG_DCXO_32K_RESIDUAL_SHIFT 0
#define PMIC_RG_DCXO_S2A_LDO_BUFTOP_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_LDO_BUFTOP_EN_SHIFT 12
#define PMIC_RG_DCXO_S2A_LDO_FPM_RCTB_MASK 0x1
#define PMIC_RG_DCXO_S2A_LDO_FPM_RCTB_SHIFT 11
#define PMIC_RG_DCXO_S2A_BANDGAP_RCTB_MASK 0x1
#define PMIC_RG_DCXO_S2A_BANDGAP_RCTB_SHIFT 10
#define PMIC_RG_DCXO_S2A_CURRENT_RCTB_MASK 0x1
#define PMIC_RG_DCXO_S2A_CURRENT_RCTB_SHIFT 9
#define PMIC_RG_DCXO_S2A_C1C2_SYNC_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_C1C2_SYNC_EN_SHIFT 8
#define PMIC_RG_DCXO_S2A_SYNC_EN_MASK 0x1
#define PMIC_RG_DCXO_S2A_SYNC_EN_SHIFT 7
#define PMIC_RG_DCXO_S2A_ACL_BIT_SWAP_MASK 0x1
#define PMIC_RG_DCXO_S2A_ACL_BIT_SWAP_SHIFT 6
#define PMIC_RG_DCXO_S2A_ACL_BIT_END_MASK 0x7
#define PMIC_RG_DCXO_S2A_ACL_BIT_END_SHIFT 3
#define PMIC_RG_DCXO_S2A_ACL_BIT_START_MASK 0x7
#define PMIC_RG_DCXO_S2A_ACL_BIT_START_SHIFT 0
#define PMIC_RG_DCXO_A2S_LDO_BUFTOP_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_LDO_BUFTOP_EN_SHIFT 14
#define PMIC_RG_DCXO_A2S_LDO_FPM_RCTB_MASK 0x1
#define PMIC_RG_DCXO_A2S_LDO_FPM_RCTB_SHIFT 13
#define PMIC_RG_DCXO_A2S_BANDGAP_RCTB_MASK 0x1
#define PMIC_RG_DCXO_A2S_BANDGAP_RCTB_SHIFT 12
#define PMIC_RG_DCXO_A2S_CURRENT_RCTB_MASK 0x1
#define PMIC_RG_DCXO_A2S_CURRENT_RCTB_SHIFT 11
#define PMIC_RG_DCXO_A2S_CAP_LOW_MASK 0x1
#define PMIC_RG_DCXO_A2S_CAP_LOW_SHIFT 10
#define PMIC_RG_DCXO_A2S_CAP_HIGH_MASK 0x1
#define PMIC_RG_DCXO_A2S_CAP_HIGH_SHIFT 9
#define PMIC_RG_DCXO_A2S_C1C2_SYNC_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_C1C2_SYNC_EN_SHIFT 8
#define PMIC_RG_DCXO_A2S_SYNC_EN_MASK 0x1
#define PMIC_RG_DCXO_A2S_SYNC_EN_SHIFT 7
#define PMIC_RG_DCXO_A2S_ACL_BIT_SWAP_MASK 0x1
#define PMIC_RG_DCXO_A2S_ACL_BIT_SWAP_SHIFT 6
#define PMIC_RG_DCXO_A2S_ACL_BIT_END_MASK 0x7
#define PMIC_RG_DCXO_A2S_ACL_BIT_END_SHIFT 3
#define PMIC_RG_DCXO_A2S_ACL_BIT_START_MASK 0x7
#define PMIC_RG_DCXO_A2S_ACL_BIT_START_SHIFT 0
#define PMIC_RG_DCXO_POR2_CAP_LOW_MASK 0x1
#define PMIC_RG_DCXO_POR2_CAP_LOW_SHIFT 13
#define PMIC_RG_DCXO_POR2_CAP_HIGH_MASK 0x1
#define PMIC_RG_DCXO_POR2_CAP_HIGH_SHIFT 12
#define PMIC_RG_DCXO_POR2_C1C2_SYNC_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_C1C2_SYNC_EN_SHIFT 11
#define PMIC_RG_DCXO_POR2_SYNC_EN_MASK 0x1
#define PMIC_RG_DCXO_POR2_SYNC_EN_SHIFT 10
#define PMIC_RG_DCXO_POR2_POR_LENGTH_OPTION_MASK 0x3
#define PMIC_RG_DCXO_POR2_POR_LENGTH_OPTION_SHIFT 8
#define PMIC_RG_DCXO_POR2_ACL_BIT_SWAP_MASK 0x1
#define PMIC_RG_DCXO_POR2_ACL_BIT_SWAP_SHIFT 6
#define PMIC_RG_DCXO_POR2_ACL_BIT_END_MASK 0x7
#define PMIC_RG_DCXO_POR2_ACL_BIT_END_SHIFT 3
#define PMIC_RG_DCXO_POR2_ACL_BIT_START_MASK 0x7
#define PMIC_RG_DCXO_POR2_ACL_BIT_START_SHIFT 0
#define PMIC_RG_DCXO_FT_TRIM_LENGTH_OPTION_MASK 0xFF
#define PMIC_RG_DCXO_FT_TRIM_LENGTH_OPTION_SHIFT 0
#define PMIC_RGS_DCXO_C2_MASK 0xFF
#define PMIC_RGS_DCXO_C2_SHIFT 8
#define PMIC_RGS_DCXO_ICONT_MASK 0xFF
#define PMIC_RGS_DCXO_ICONT_SHIFT 0
#define PMIC_RGS_DCXO_TRIM2_C2_MASK 0xFF
#define PMIC_RGS_DCXO_TRIM2_C2_SHIFT 8
#define PMIC_RGS_DCXO_TRIM1_C2_MASK 0xFF
#define PMIC_RGS_DCXO_TRIM1_C2_SHIFT 0
#define PMIC_RGS_DCXO_FT_FREQ_TRIM_STEP_VALUE_MASK 0x1
#define PMIC_RGS_DCXO_FT_FREQ_TRIM_STEP_VALUE_SHIFT 5
#define PMIC_RGS_DCXO_FT_FREQ_TRIM_STEP_END_MASK 0x1
#define PMIC_RGS_DCXO_FT_FREQ_TRIM_STEP_END_SHIFT 4
#define PMIC_RGS_DCXO_FT_FREQ_TRIM_END_MASK 0x1
#define PMIC_RGS_DCXO_FT_FREQ_TRIM_END_SHIFT 3
#define PMIC_RGS_DCXO_MANUAL_ACL_END_MASK 0x1
#define PMIC_RGS_DCXO_MANUAL_ACL_END_SHIFT 2
#define PMIC_RGS_DCXO_XTAL_MODE_MASK 0x1
#define PMIC_RGS_DCXO_XTAL_MODE_SHIFT 1
#define PMIC_RGS_DCXO_TRIM_SEL_MASK 0x1
#define PMIC_RGS_DCXO_TRIM_SEL_SHIFT 0

#endif /* _MT6397_PMIC_UPMU_HW_H_ */