projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 6fa3eb70 S |
1 | #ifndef _MT_SPM_ |
| 2 | #define _MT_SPM_ | |
| 3 | ||
| 4 | #include <linux/kernel.h> | |
| 5 | #include <linux/interrupt.h> | |
| 6 | ||
| 7 | #include <mach/mt_reg_base.h> | |
| 8 | #include <mach/sync_write.h> | |
| 9 | #include <mach/irqs.h> | |
| 10 | ||
| 11 | /* | |
| 12 | * for SPM register control | |
| 13 | */ | |
| 14 | #define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x0000) | |
| 15 | #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x0010) | |
| 16 | #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x0014) | |
| 17 | #define SPM_CLK_SETTLE (SPM_BASE + 0x0100) | |
| 18 | #define SPM_FC0_PWR_CON (SPM_BASE + 0x0200) | |
| 19 | #define SPM_CPU_PWR_CON (SPM_BASE + 0x0208) | |
| 20 | #define SPM_VDE_PWR_CON (SPM_BASE + 0x0210) | |
| 21 | #define SPM_MFG_PWR_CON (SPM_BASE + 0x0214) | |
| 22 | #define SPM_FC1_PWR_CON (SPM_BASE + 0x0218) | |
| 23 | #define SPM_FC2_PWR_CON (SPM_BASE + 0x021c) | |
| 24 | #define SPM_FC3_PWR_CON (SPM_BASE + 0x0220) | |
| 25 | #define SPM_IFR_PWR_CON (SPM_BASE + 0x0234) | |
| 26 | #define SPM_ISP_PWR_CON (SPM_BASE + 0x0238) | |
| 27 | #define SPM_DIS_PWR_CON (SPM_BASE + 0x023c) | |
| 28 | #define SPM_DPY_PWR_CON (SPM_BASE + 0x0240) | |
| 29 | #define SPM_CPU_L2_DAT_PDN (SPM_BASE + 0x0244) | |
| 30 | #define SPM_CPU_L2_DAT_SLEEP_B (SPM_BASE + 0x0248) | |
| 31 | #define SPM_MP_CORE0_AUX (SPM_BASE + 0x024c) | |
| 32 | #define SPM_MP_CORE1_AUX (SPM_BASE + 0x0250) | |
| 33 | #define SPM_MP_CORE2_AUX (SPM_BASE + 0x0254) | |
| 34 | #define SPM_MP_CORE3_AUX (SPM_BASE + 0x0258) | |
| 35 | #define SPM_CPU_FC0_L1_PDN (SPM_BASE + 0x025c) | |
| 36 | #define SPM_CPU_FC1_L1_PDN (SPM_BASE + 0x0264) | |
| 37 | #define SPM_CPU_FC2_L1_PDN (SPM_BASE + 0x026c) | |
| 38 | #define SPM_CPU_FC3_L1_PDN (SPM_BASE + 0x0274) | |
| 39 | #define SPM_IFR_FH_SRAM_CTRL (SPM_BASE + 0x027c) | |
| 40 | #define SPM_CONN_PWR_CON (SPM_BASE + 0x0280) | |
| 41 | #define SPM_MD_PWR_CON (SPM_BASE + 0x0284) | |
| 42 | #define SPM_MCU_PWR_CON (SPM_BASE + 0x0290) | |
| 43 | #define SPM_IFR_SRAMROM_CON (SPM_BASE + 0x0294) | |
| 44 | #define SPM_PCM_CON0 (SPM_BASE + 0x0310) | |
| 45 | #define SPM_PCM_CON1 (SPM_BASE + 0x0314) | |
| 46 | #define SPM_PCM_IM_PTR (SPM_BASE + 0x0318) | |
| 47 | #define SPM_PCM_IM_LEN (SPM_BASE + 0x031c) | |
| 48 | #define SPM_PCM_REG_DATA_INI (SPM_BASE + 0x0320) | |
| 49 | #define SPM_PCM_EVENT_VECTOR0 (SPM_BASE + 0x0340) | |
| 50 | #define SPM_PCM_EVENT_VECTOR1 (SPM_BASE + 0x0344) | |
| 51 | #define SPM_PCM_EVENT_VECTOR2 (SPM_BASE + 0x0348) | |
| 52 | #define SPM_PCM_EVENT_VECTOR3 (SPM_BASE + 0x034c) | |
| 53 | #define SPM_PCM_MAS_PAUSE_MASK (SPM_BASE + 0x0354) | |
| 54 | #define SPM_PCM_PWR_IO_EN (SPM_BASE + 0x0358) | |
| 55 | #define SPM_PCM_TIMER_VAL (SPM_BASE + 0x035c) | |
| 56 | #define SPM_PCM_TIMER_OUT (SPM_BASE + 0x0360) | |
| 57 | #define SPM_PCM_REG0_DATA (SPM_BASE + 0x0380) | |
| 58 | #define SPM_PCM_REG1_DATA (SPM_BASE + 0x0384) | |
| 59 | #define SPM_PCM_REG2_DATA (SPM_BASE + 0x0388) | |
| 60 | #define SPM_PCM_REG3_DATA (SPM_BASE + 0x038c) | |
| 61 | #define SPM_PCM_REG4_DATA (SPM_BASE + 0x0390) | |
| 62 | #define SPM_PCM_REG5_DATA (SPM_BASE + 0x0394) | |
| 63 | #define SPM_PCM_REG6_DATA (SPM_BASE + 0x0398) | |
| 64 | #define SPM_PCM_REG7_DATA (SPM_BASE + 0x039c) | |
| 65 | #define SPM_PCM_REG8_DATA (SPM_BASE + 0x03a0) | |
| 66 | #define SPM_PCM_REG9_DATA (SPM_BASE + 0x03a4) | |
| 67 | #define SPM_PCM_REG10_DATA (SPM_BASE + 0x03a8) | |
| 68 | #define SPM_PCM_REG11_DATA (SPM_BASE + 0x03ac) | |
| 69 | #define SPM_PCM_REG12_DATA (SPM_BASE + 0x03b0) | |
| 70 | #define SPM_PCM_REG13_DATA (SPM_BASE + 0x03b4) | |
| 71 | #define SPM_PCM_REG14_DATA (SPM_BASE + 0x03b8) | |
| 72 | #define SPM_PCM_REG15_DATA (SPM_BASE + 0x03bc) | |
| 73 | #define SPM_PCM_EVENT_REG_STA (SPM_BASE + 0x03c0) | |
| 74 | #define SPM_PCM_FSM_STA (SPM_BASE + 0x03c4) | |
| 75 | #define SPM_PCM_IM_HOST_RW_PTR (SPM_BASE + 0x03c8) | |
| 76 | #define SPM_PCM_IM_HOST_RW_DAT (SPM_BASE + 0x03cc) | |
| 77 | #define SPM_PCM_EVENT_VECTOR4 (SPM_BASE + 0x03d0) | |
| 78 | #define SPM_PCM_EVENT_VECTOR5 (SPM_BASE + 0x03d4) | |
| 79 | #define SPM_PCM_EVENT_VECTOR6 (SPM_BASE + 0x03d8) | |
| 80 | #define SPM_PCM_EVENT_VECTOR7 (SPM_BASE + 0x03dc) | |
| 81 | #define SPM_PCM_SW_INT_SEL (SPM_BASE + 0x03e0) | |
| 82 | #define SPM_PCM_SW_INT_CLEAR (SPM_BASE + 0x03e4) | |
| 83 | #define SPM_CLK_CON (SPM_BASE + 0x0400) | |
| 84 | #define SPM_APMCU_PWRCTL (SPM_BASE + 0x0600) | |
| 85 | #define SPM_AP_DVFS_CON_SET (SPM_BASE + 0x0604) | |
| 86 | #define SPM_AP_STANBY_CON (SPM_BASE + 0x0608) | |
| 87 | #define SPM_PWR_STATUS (SPM_BASE + 0x060c) | |
| 88 | #define SPM_PWR_STATUS_S (SPM_BASE + 0x0610) | |
| 89 | #define SPM_SLEEP_TIMER_STA (SPM_BASE + 0x0720) | |
| 90 | #define SPM_SLEEP_TWAM_CON (SPM_BASE + 0x0760) | |
| 91 | #define SPM_SLEEP_TWAM_STATUS0 (SPM_BASE + 0x0764) | |
| 92 | #define SPM_SLEEP_TWAM_STATUS1 (SPM_BASE + 0x0768) | |
| 93 | #define SPM_SLEEP_TWAM_STATUS2 (SPM_BASE + 0x076c) | |
| 94 | #define SPM_SLEEP_TWAM_STATUS3 (SPM_BASE + 0x0770) | |
| 95 | #define SPM_SLEEP_WAKEUP_EVENT_MASK (SPM_BASE + 0x0810) | |
| 96 | #define SPM_SLEEP_CPU_WAKEUP_EVENT (SPM_BASE + 0x0814) | |
| 97 | #define SPM_PCM_WDT_TIMER_VAL (SPM_BASE + 0x0824) | |
| 98 | #define SPM_SLEEP_ISR_MASK (SPM_BASE + 0x0900) | |
| 99 | #define SPM_SLEEP_ISR_STATUS (SPM_BASE + 0x0904) | |
| 100 | #define SPM_SLEEP_ISR_RAW_STA (SPM_BASE + 0x0910) | |
| 101 | #define SPM_PCM_RESERVE (SPM_BASE + 0x0b00) | |
| 102 | #define SPM_PCM_SRC_REQ (SPM_BASE + 0x0b04) | |
| 103 | #define SPM_SLEEP_CPU_IRQ_MASK (SPM_BASE + 0x0b10) | |
| 104 | #define SPM_PCM_DEBUG_CON (SPM_BASE + 0x0b20) | |
| 105 | #define SPM_CORE0_WFI_SEL (SPM_BASE + 0x0f00) | |
| 106 | #define SPM_CORE1_WFI_SEL (SPM_BASE + 0x0f04) | |
| 107 | #define SPM_CORE2_WFI_SEL (SPM_BASE + 0x0f08) | |
| 108 | #define SPM_CORE3_WFI_SEL (SPM_BASE + 0x0f0c) | |
| 109 | ||
| 110 | #define SPM_PROJECT_CODE 0xb16 | |
| 111 | ||
| 112 | #define CON0_PCM_KICK (1U << 0) | |
| 113 | #define CON0_IM_KICK (1U << 1) | |
| 114 | #define CON0_IM_SLEEP_DVS (1U << 3) | |
| 115 | #define CON0_EVENT_VEC0_EN (1U << 4) | |
| 116 | #define CON0_EVENT_VEC1_EN (1U << 5) | |
| 117 | #define CON0_EVENT_VEC2_EN (1U << 6) | |
| 118 | #define CON0_EVENT_VEC3_EN (1U << 7) | |
| 119 | #define CON0_EVENT_VEC4_EN (1U << 8) | |
| 120 | #define CON0_EVENT_VEC5_EN (1U << 9) | |
| 121 | #define CON0_EVENT_VEC6_EN (1U << 10) | |
| 122 | #define CON0_EVENT_VEC7_EN (1U << 11) | |
| 123 | #define CON0_PCM_SW_RESET (1U << 15) | |
| 124 | #define CON0_CFG_KEY (SPM_PROJECT_CODE << 16) | |
| 125 | ||
| 126 | #define CON1_IM_SLAVE (1U << 0) | |
| 127 | #define CON1_MIF_APBEN (1U << 3) | |
| 128 | #define CON1_PCM_TIMER_EN (1U << 5) | |
| 129 | #define CON1_IM_NONRP_EN (1U << 6) | |
| 130 | #define CON1_PCM_WDT_EN (1U << 8) | |
| 131 | #define CON1_PCM_WDT_WAKE_MODE (1U << 9) | |
| 132 | #define CON1_SPM_SRAM_SLP_B (1U << 10) | |
| 133 | #define CON1_SPM_SRAM_ISO_B (1U << 11) | |
| 134 | #define CON1_CFG_KEY (SPM_PROJECT_CODE << 16) | |
| 135 | ||
| 136 | #define PCM_PWRIO_EN_R0 (1U << 0) | |
| 137 | #define PCM_PWRIO_EN_R7 (1U << 7) | |
| 138 | #define PCM_RF_SYNC_R0 (1U << 16) | |
| 139 | #define PCM_RF_SYNC_R7 (1U << 23) | |
| 140 | ||
| 141 | #define R7_UART_CLK_OFF_REQ (1U << 0) | |
| 142 | #define R7_WDT_KICK_P (1U << 22) | |
| 143 | ||
| 144 | #define R13_CONN_SRCCLKENI (1U << 1) | |
| 145 | #define R13_MD_SRCCLKENI (1U << 4) | |
| 146 | #define R13_UART_CLK_OFF_ACK (1U << 20) | |
| 147 | ||
| 148 | #define PCM_SW_INT0 (1U << 0) | |
| 149 | #define PCM_SW_INT1 (1U << 1) | |
| 150 | #define PCM_SW_INT2 (1U << 2) | |
| 151 | #define PCM_SW_INT3 (1U << 3) | |
| 152 | #define PCM_SW_INT_ALL (PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ | |
| 153 | PCM_SW_INT0) | |
| 154 | ||
| 155 | #define CC_SYSCLK0_EN_0 (1U << 0) | |
| 156 | #define CC_SYSCLK0_EN_1 (1U << 1) | |
| 157 | #define CC_SYSSETTLE_SEL (1U << 4) | |
| 158 | #define CC_LOCK_INFRA_DCM (1U << 5) | |
| 159 | #define CC_SRCLKENA_MASK (1U << 6) | |
| 160 | #define CC_CXO32K_RM_EN_MD (1U << 9) | |
| 161 | #define CC_CXO32K_RM_EN_CONN (1U << 10) | |
| 162 | #define CC_CLKSQ0_SEL (1U << 11) | |
| 163 | #define CC_DISABLE_SODI (1U << 13) | |
| 164 | #define CC_DISABLE_DORM_PWR (1U << 14) | |
| 165 | #define CC_DISABLE_INFRA_PWR (1U << 15) | |
| 166 | #define CC_SRCLKEN0_EN (1U << 16) | |
| 167 | ||
| 168 | #define TWAM_CON_EN (1U << 0) | |
| 169 | #define TWAM_CON_SPEED_EN (1U << 4) | |
| 170 | ||
| 171 | #define WAKE_SRC_TS (1U << 1) | |
| 172 | #define WAKE_SRC_KP (1U << 2) | |
| 173 | #define WAKE_SRC_WDT (1U << 3) | |
| 174 | #define WAKE_SRC_GPT (1U << 4) | |
| 175 | #define WAKE_SRC_EINT (1U << 5) | |
| 176 | #define WAKE_SRC_CONN_WDT (1U << 6) | |
| 177 | #define WAKE_SRC_CEC (1U << 7) | |
| 178 | #define WAKE_SRC_IRRX (1U << 8) | |
| 179 | #define WAKE_SRC_LOW_BAT (1U << 9) | |
| 180 | #define WAKE_SRC_CONN (1U << 10) | |
| 181 | #define WAKE_SRC_USB_CD (1U << 14) | |
| 182 | #define WAKE_SRC_USB_PDN (1U << 16) | |
| 183 | #define WAKE_SRC_DBGSYS (1U << 18) | |
| 184 | #define WAKE_SRC_UART0 (1U << 19) | |
| 185 | #define WAKE_SRC_AFE (1U << 20) | |
| 186 | #define WAKE_SRC_THERM (1U << 21) | |
| 187 | #define WAKE_SRC_CIRQ (1U << 22) | |
| 188 | #define WAKE_SRC_SYSPWREQ (1U << 24) | |
| 189 | #define WAKE_SRC_ETHERNET (1U << 25) | |
| 190 | #define WAKE_SRC_CPU0_IRQ (1U << 26) | |
| 191 | #define WAKE_SRC_CPU1_IRQ (1U << 27) | |
| 192 | #define WAKE_SRC_CPU2_IRQ (1U << 28) | |
| 193 | #define WAKE_SRC_CPU3_IRQ (1U << 29) | |
| 194 | ||
| 195 | #define ISR_TWAM (1U << 2) | |
| 196 | #define ISR_PCM_RETURN (1U << 3) | |
| 197 | #define ISR_PCM_IRQ0 (1U << 8) | |
| 198 | #define ISR_PCM_IRQ1 (1U << 9) | |
| 199 | #define ISR_PCM_IRQ2 (1U << 10) | |
| 200 | #define ISR_PCM_IRQ3 (1U << 11) | |
| 201 | ||
| 202 | #define ISRM_PCM_IRQ_AUX (ISR_PCM_IRQ3 | ISR_PCM_IRQ2 | ISR_PCM_IRQ1) | |
| 203 | #define ISRM_ALL_EXC_TWAM (ISR_PCM_IRQ3 | ISR_PCM_IRQ2 | ISR_PCM_IRQ1 | \ | |
| 204 | ISR_PCM_IRQ0 | ISR_PCM_RETURN) | |
| 205 | #define ISRM_ALL (ISR_PCM_IRQ3 | ISR_PCM_IRQ2 | ISR_PCM_IRQ1 | \ | |
| 206 | ISR_PCM_IRQ0 | ISR_PCM_RETURN | ISR_TWAM) | |
| 207 | ||
| 208 | #define ISRC_ALL_EXC_TWAM (ISR_PCM_RETURN) | |
| 209 | #define ISRC_ALL (ISR_PCM_RETURN | ISR_TWAM) | |
| 210 | ||
| 211 | #define EVENT_VEC(event, resume, imme, pc) \ | |
| 212 | (((event) << 0) | ((resume) << 5) | ((imme) << 6) | ((pc) << 16)) | |
| 213 | ||
| 214 | #define spm_read(addr) (*(volatile u32 *)(addr)) | |
| 215 | #define spm_write(addr, val) mt65xx_reg_sync_writel(val, addr) | |
| 216 | ||
| 217 | ||
| 218 | #define spm_is_wakesrc_invalid(wakesrc) (!!((u32)(wakesrc) & 0xc082b881)) | |
| 219 | ||
| 220 | #define spm_emerg(fmt, args...) printk(KERN_EMERG "[SPM] " fmt, ##args) | |
| 221 | #define spm_alert(fmt, args...) printk(KERN_ALERT "[SPM] " fmt, ##args) | |
| 222 | #define spm_crit(fmt, args...) printk(KERN_CRIT "[SPM] " fmt, ##args) | |
| 223 | #define spm_error(fmt, args...) printk(KERN_ERR "[SPM] " fmt, ##args) | |
| 224 | #define spm_warning(fmt, args...) printk(KERN_WARNING "[SPM] " fmt, ##args) | |
| 225 | #define spm_notice(fmt, args...) printk(KERN_NOTICE "[SPM] " fmt, ##args) | |
| 226 | #define spm_info(fmt, args...) printk(KERN_INFO "[SPM] " fmt, ##args) | |
| 227 | #define spm_debug(fmt, args...) printk(KERN_DEBUG "[SPM] " fmt, ##args) | |
| 228 | ||
| 229 | typedef struct { | |
| 230 | const u32 *base; /* code array base */ | |
| 231 | const u16 size; /* code array size */ | |
| 232 | const u16 sess; /* session number */ | |
| 233 | u32 vec0; /* event vector 0 config */ | |
| 234 | u32 vec1; /* event vector 1 config */ | |
| 235 | u32 vec2; /* event vector 2 config */ | |
| 236 | u32 vec3; /* event vector 3 config */ | |
| 237 | u32 vec4; /* event vector 4 config */ | |
| 238 | u32 vec5; /* event vector 5 config */ | |
| 239 | u32 vec6; /* event vector 6 config */ | |
| 240 | u32 vec7; /* event vector 7 config */ | |
| 241 | } pcm_desc_t; | |
| 242 | ||
| 243 | typedef struct { | |
| 244 | u32 sig0; /* signal 0: config or status */ | |
| 245 | u32 sig1; /* signal 1: config or status */ | |
| 246 | u32 sig2; /* signal 2: config or status */ | |
| 247 | u32 sig3; /* signal 3: config or status */ | |
| 248 | } twam_sig_t; | |
| 249 | ||
| 250 | typedef void (*twam_handler_t)(twam_sig_t *twamsig); | |
| 251 | ||
| 252 | static inline u32 spm_get_base_phys(const u32 *base) | |
| 253 | { | |
| 254 | u32 phys = virt_to_phys(base); | |
| 255 | BUG_ON(phys & 0x00000003); /* check 4-byte alignment */ | |
| 256 | return phys; | |
| 257 | } | |
| 258 | ||
| 259 | extern void spm_go_to_normal(void); | |
| 260 | ||
| 261 | extern void spm_module_init(void); | |
| 262 | ||
| 263 | /* | |
| 264 | * for TWAM to integrate with MET | |
| 265 | */ | |
| 266 | extern void spm_twam_register_handler(twam_handler_t handler); | |
| 267 | extern void spm_twam_enable_monitor(twam_sig_t *twamsig, bool speed_mode); | |
| 268 | extern void spm_twam_disable_monitor(void); | |
| 269 | ||
| 270 | ||
| 271 | /* | |
| 272 | * for PCM WDT to replace RGU WDT | |
| 273 | */ | |
| 274 | extern int spm_wdt_register_fiq(fiq_isr_handler rgu_wdt_handler); | |
| 275 | extern int spm_wdt_register_irq(irq_handler_t rgu_wdt_handler); | |
| 276 | extern void spm_wdt_set_timeout(u32 sec); | |
| 277 | extern void spm_wdt_enable_timer(void); | |
| 278 | extern void spm_wdt_restart_timer(void); | |
| 279 | extern void spm_wdt_restart_timer_nolock(void); | |
| 280 | extern void spm_wdt_disable_timer(void); | |
| 281 | ||
| 282 | ||
| 283 | extern int spm_dvfs_ctrl_volt(u32 value); | |
| 284 | ||
| 285 | #endif |