Commit | Line | Data |
---|---|---|
6fa3eb70 S |
1 | /* |
2 | * This file is generated automatically according to the design of silicon. | |
3 | * Don't modify it directly. | |
4 | */ | |
5 | ||
6 | #ifndef __MT_REG_BASE | |
7 | #define __MT_REG_BASE | |
8 | ||
9 | #if !defined(CONFIG_MT8127_FPGA) | |
10 | ||
11 | // APB Module cksys | |
12 | #define INFRA_BASE (0xF0000000) | |
13 | ||
14 | // APB Module infracfg_ao | |
15 | #define INFRACFG_AO_BASE (0xF0001000) | |
16 | ||
17 | // APB Module fhctl | |
18 | #define FHCTL_BASE (0xF0002000) | |
19 | ||
20 | // APB Module pericfg | |
21 | #define PERICFG_BASE (0xF0003000) | |
22 | ||
23 | // APB Module dramc | |
24 | #define DRAMC0_BASE (0xF0004000) | |
25 | ||
26 | // APB Module gpio | |
27 | #define GPIO_BASE (0xF0005000) | |
28 | ||
29 | // APB Module sleep | |
30 | #define SPM_BASE (0xF0006000) | |
31 | ||
32 | // APB Module toprgu | |
33 | #define TOPRGU_BASE (0xF0007000) | |
34 | #define AP_RGU_BASE TOPRGU_BASE | |
35 | ||
36 | // APB Module apxgpt | |
37 | #define APMCU_GPTIMER_BASE (0xF0008000) | |
38 | ||
39 | // APB Module rsvd | |
40 | #define RSVD_BASE (0xF0009000) | |
41 | ||
42 | // APB Module sej | |
43 | #define HACC_BASE (0xF000A000) | |
44 | ||
45 | // APB Module ap_cirq_eint | |
46 | #define AP_CIRQ_EINT (0xF000B000) | |
47 | ||
48 | // APB Module ap_cirq_eint | |
49 | #define EINT_BASE (0xF000B000) | |
50 | ||
51 | // APB Module smi | |
52 | #define SMI1_BASE (0xF000C000) | |
53 | ||
54 | // APB Module pmic_wrap | |
55 | #define PWRAP_BASE (0xF000D000) | |
56 | ||
57 | // APB Module device_apc_ao | |
58 | #define DEVAPC_AO_BASE (0xF000E000) | |
59 | ||
60 | // APB Module ddrphy | |
61 | #define DDRPHY_BASE (0xF000F000) | |
62 | ||
63 | // APB Module vencpll | |
64 | #define VENCPLL_BASE (0xF000F000) | |
65 | ||
66 | // APB Module mipi_tx_config | |
67 | #define MIPI_CONFIG_BASE (0xF0010000) | |
68 | ||
69 | // APB Module LVDS ANA | |
70 | #define LVDS_ANA_BASE (0xF0010400) | |
71 | ||
72 | // APB Module mipi_rx_ana | |
73 | #define MIPI_RX_ANA_BASE (0xF0215000) | |
74 | ||
75 | // APB Module kp | |
76 | #define KP_BASE (0xF0011000) | |
77 | ||
78 | // APB Module dbgapb | |
79 | #define DEBUGTOP_BASE (0xF0100000) | |
80 | ||
81 | // APB Module mcucfg | |
82 | #define MCUSYS_CFGREG_BASE (0xF0200000) | |
83 | ||
84 | // APB Module infracfg | |
85 | #define INFRACFG_BASE (0xF0201000) | |
86 | ||
87 | // APB Module sramrom | |
88 | #define SRAMROM_BASE (0xF0202000) | |
89 | ||
90 | // APB Module emi | |
91 | #define EMI_BASE (0xF0203000) | |
92 | ||
93 | // APB Module sys_cirq | |
94 | #define SYS_CIRQ_BASE (0xF0204000) | |
95 | ||
96 | // APB Module m4u | |
97 | #define SMI_MMU_TOP_BASE (0xF0205000) | |
98 | ||
99 | // APB Module nb_mmu | |
100 | #define NB_MMU0_BASE (0xF0205200) | |
101 | ||
102 | // APB Module nb_mmu | |
103 | #define NB_MMU1_BASE (0xF0205800) | |
104 | ||
105 | // APB Module efusec | |
106 | #define EFUSEC_BASE (0xF0206000) | |
107 | ||
108 | // APB Module device_apc | |
109 | #define DEVAPC_BASE (0xF0207000) | |
110 | ||
111 | // APB Module mcu_biu_cfg | |
112 | #define MCU_BIU_BASE (0xF0208000) | |
113 | ||
114 | // APB Module apmixed | |
115 | #define APMIXEDSYS_BASE (0xF0209000) | |
116 | ||
117 | // APB Module ccif | |
118 | #define AP_CCIF_BASE (0xF020A000) | |
119 | ||
120 | // APB Module ccif | |
121 | #define MD_CCIF_BASE (0xF020B000) | |
122 | ||
123 | // APB Module gpio1 | |
124 | #define GPIO1_BASE (0xF020C000) | |
125 | ||
126 | // APB Module infra_mbist | |
127 | #define INFRA_TOP_MBIST_CTRL_BASE (0xF020D000) | |
128 | ||
129 | // APB Module dramc_conf_nao | |
130 | #define DRAMC_NAO_BASE (0xF020E000) | |
131 | ||
132 | // APB Module trng | |
133 | #define TRNG_BASE (0xF020F000) | |
134 | ||
135 | // APB Module ca9 | |
136 | #define CORTEXA7MP_BASE (0xF0210000) | |
137 | ||
138 | // APB Module ap_dma | |
139 | #define AP_DMA_BASE (0xF1000000) | |
140 | ||
141 | // APB Module auxadc | |
142 | #define AUXADC_BASE (0xF1001000) | |
143 | ||
144 | // APB Module uart | |
145 | #define UART1_BASE (0xF1002000) | |
146 | ||
147 | // APB Module uart | |
148 | #define UART2_BASE (0xF1003000) | |
149 | ||
150 | // APB Module uart | |
151 | #define UART3_BASE (0xF1004000) | |
152 | ||
153 | // APB Module uart | |
154 | #define UART4_BASE (0xF1005000) | |
155 | ||
156 | // APB Module pwm | |
157 | #define PWM_BASE (0xF1006000) | |
158 | ||
159 | // APB Module i2c | |
160 | #define I2C0_BASE (0xF1007000) | |
161 | ||
162 | // APB Module i2c | |
163 | #define I2C1_BASE (0xF1008000) | |
164 | ||
165 | // APB Module i2c | |
166 | #define I2C2_BASE (0xF1009000) | |
167 | ||
168 | // APB Module spi | |
169 | #define SPI0_BASE (0xF100A000) | |
170 | #define SPI1_BASE (0xF100A000) | |
171 | ||
172 | // APB Module therm_ctrl | |
173 | #define THERMAL_BASE (0xF100B000) | |
174 | ||
175 | // APB Module btif | |
176 | #define BTIF_BASE (0xF100C000) | |
177 | ||
178 | // APB Module nfi | |
179 | #define NFI_BASE (0xF100D000) | |
180 | ||
181 | // APB Module nfiecc_16bit | |
182 | #define NFIECC_BASE (0xF100E000) | |
183 | ||
184 | // APB Module nli_arb | |
185 | #define NLI_ARB_BASE (0xF100F000) | |
186 | ||
187 | // APB Module peri_pwrap_bridge | |
188 | #define PERI_PWRAP_BRIDGE_BASE (0xF1017000) | |
189 | ||
190 | // APB Module usb2 | |
191 | #define USB_BASE (0xF1200000) | |
192 | #define USB1_BASE (0xF1270000) | |
193 | ||
194 | // APB Module usb_sif | |
195 | #define USB_SIF_BASE (0xF1210000) | |
196 | ||
197 | // APB Module msdc | |
198 | #define MSDC_0_BASE (0xF1230000) | |
199 | ||
200 | // APB Module msdc | |
201 | #define MSDC_1_BASE (0xF1240000) | |
202 | ||
203 | // APB Module msdc | |
204 | #define MSDC_2_BASE (0xF1250000) | |
205 | ||
206 | // APB Module wcn_ahb | |
207 | #define WCN_AHB_BASE (0xF1260000) | |
208 | ||
209 | // ARB Module ethernet | |
210 | #define ETHERNET_BASE (0xF1280000) | |
211 | // APB Module mfg_top | |
212 | #define G3D_CONFIG_BASE (0xF3000000) | |
213 | ||
214 | // APB Module mali | |
215 | #define MALI_BASE (0xF3040000) | |
216 | ||
217 | // APB Module mali_tb_cmd | |
218 | #define MALI_TB_BASE (0xF301f000) | |
219 | ||
220 | // APB Module mmsys_config | |
221 | #define DISPSYS_BASE (0xF4000000) | |
222 | ||
223 | // APB Module mdp_rdma | |
224 | #define MDP_RDMA_BASE (0xF4001000) | |
225 | ||
226 | // APB Module mdp_rsz | |
227 | #define MDP_RSZ0_BASE (0xF4002000) | |
228 | ||
229 | // APB Module mdp_rsz | |
230 | #define MDP_RSZ1_BASE (0xF4003000) | |
231 | ||
232 | // APB Module disp_wdma | |
233 | #define MDP_WDMA_BASE (0xF4004000) | |
234 | ||
235 | // APB Module disp_wdma | |
236 | #define WDMA1_BASE (0xF4004000) | |
237 | ||
238 | // APB Module mdp_wrot | |
239 | #define MDP_WROT_BASE (0xF4005000) | |
240 | ||
241 | // APB Module mdp_tdshp | |
242 | #define MDP_TDSHP_BASE (0xF4006000) | |
243 | ||
244 | // APB Module ovl | |
245 | #define DISP_OVL_BASE (0xF4007000) | |
246 | ||
247 | // APB Module ovl | |
248 | #define OVL0_BASE (0xF4007000) | |
249 | ||
250 | // APB Module ovl | |
251 | #define OVL1_BASE (0xF4007000) | |
252 | ||
253 | // APB Module disp_rdma | |
254 | #define DISP_RDMA_BASE (0xF4008000) | |
255 | ||
256 | // APB Module disp_rdma | |
257 | #define R_DMA1_BASE (0xF4008000) | |
258 | ||
259 | // APB Module disp_rdma | |
260 | #define R_DMA0_BASE (0xF4008000) | |
261 | ||
262 | // APB Module disp_wdma | |
263 | #define DISP_WDMA_BASE (0xF4009000) | |
264 | ||
265 | // APB Module disp_wdma | |
266 | #define WDMA0_BASE (0xF4009000) | |
267 | ||
268 | // APB Module disp_bls | |
269 | #define DISP_BLS_BASE (0xF400A000) | |
270 | ||
271 | // APB Module disp_color_config | |
272 | #define DISP_COLOR_BASE (0xF400B000) | |
273 | ||
274 | // APB Module dsi | |
275 | #define DSI_BASE (0xF400C000) | |
276 | ||
277 | // APB Module disp_dpi | |
278 | #define DPI_BASE (0xF400D000) | |
279 | ||
280 | // APB Module disp_mutex | |
281 | #define MMSYS_MUTEX_BASE (0xF400E000) | |
282 | ||
283 | // APB Module mm_cmdq | |
284 | #define MMSYS_CMDQ_BASE (0xF400F000) | |
285 | ||
286 | #define DPI1_BASE (0xF4014000) | |
287 | ||
288 | ||
289 | // APB Module smi_larb | |
290 | #define SMI_LARB0_BASE (0xF4010000) | |
291 | ||
292 | // APB Module smi | |
293 | #define SMI_BASE (0xF4011000) | |
294 | ||
295 | // LVDS TX | |
296 | #define LVDS_TX_BASE (0xF4016200) | |
297 | ||
298 | // APB Module smi_larb | |
299 | #define SMILARB2_BASE (0xF5001000) | |
300 | ||
301 | // APB Module smi_larb | |
302 | #define SMI_LARB3_BASE (0xF5001000) | |
303 | ||
304 | // APB Module mmu | |
305 | #define SMI_LARB3_MMU_BASE (0xF5001800) | |
306 | ||
307 | // APB Module smi_larb | |
308 | #define SMI_LARB4_BASE (0xF5002000) | |
309 | ||
310 | // APB Module fake_eng | |
311 | #define FAKE_ENG_BASE (0xF5002000) | |
312 | ||
313 | // APB Module mmu | |
314 | #define SMI_LARB4_MMU_BASE (0xF5002800) | |
315 | ||
316 | // APB Module smi | |
317 | #define VENC_BASE (0xF5009000) | |
318 | ||
319 | // APB Module jpgenc | |
320 | #define JPGENC_BASE (0xF500A000) | |
321 | ||
322 | // APB Module vdecsys_config | |
323 | #define VDEC_GCON_BASE (0xF6000000) | |
324 | ||
325 | // APB Module smi_larb | |
326 | #define SMI_LARB1_BASE (0xF6010000) | |
327 | ||
328 | // APB Module mmu | |
329 | #define SMI_LARB1_MMU_BASE (0xF6010800) | |
330 | ||
331 | // APB Module vdtop | |
332 | #define VDEC_BASE (0xF6020000) | |
333 | ||
334 | // APB Module vdtop | |
335 | #define VDTOP_BASE (0xF6020000) | |
336 | ||
337 | // APB Module vld | |
338 | #define VLD_BASE (0xF6021000) | |
339 | ||
340 | // APB Module vld_top | |
341 | #define VLD_TOP_BASE (0xF6021800) | |
342 | ||
343 | // APB Module mc | |
344 | #define MC_BASE (0xF6022000) | |
345 | ||
346 | // APB Module avc_vld | |
347 | #define AVC_VLD_BASE (0xF6023000) | |
348 | ||
349 | // APB Module avc_mv | |
350 | #define AVC_MV_BASE (0xF6024000) | |
351 | ||
352 | // APB Module vdec_pp | |
353 | #define VDEC_PP_BASE (0xF6025000) | |
354 | ||
355 | // APB Module vp8_vld | |
356 | #define VP8_VLD_BASE (0xF6026800) | |
357 | ||
358 | // APB Module vp6 | |
359 | #define VP6_BASE (0xF6027000) | |
360 | ||
361 | // APB Module vld2 | |
362 | #define VLD2_BASE (0xF6027800) | |
363 | ||
364 | // APB Module mc_vmmu | |
365 | #define MC_VMMU_BASE (0xF6028000) | |
366 | ||
367 | // APB Module pp_vmmu | |
368 | #define PP_VMMU_BASE (0xF6029000) | |
369 | ||
370 | // APB Module imgsys | |
371 | #define IMGSYS_CONFG_BASE (0xF5000000) | |
372 | ||
373 | // APB Module cam | |
374 | #define CAMINF_BASE (0xF5000000) | |
375 | ||
376 | // APB Module csi2 | |
377 | #define CSI2_BASE (0xF5000000) | |
378 | ||
379 | // APB Module seninf | |
380 | #define SENINF_BASE (0xF5000000) | |
381 | ||
382 | // APB Module seninf_tg | |
383 | #define SENINF_TG_BASE (0xF5000000) | |
384 | ||
385 | // APB Module seninf_top | |
386 | #define SENINF_TOP_BASE (0xF5000000) | |
387 | ||
388 | // APB Module mipi_rx_config | |
389 | #define MIPI_RX_CONFIG_BASE (0xF500C000) | |
390 | ||
391 | // APB Module scam | |
392 | #define SCAM_BASE (0xF5008000) | |
393 | ||
394 | // APB Module ncsi2 | |
395 | #define NCSI2_BASE (0xF5008000) | |
396 | ||
397 | // APB Module ccir656 | |
398 | #define CCIR656_BASE (0xF5000000) | |
399 | ||
400 | // APB Module n3d_ctl | |
401 | #define N3D_CTL_BASE (0xF5000000) | |
402 | ||
403 | // APB Module fdvt | |
404 | #define FDVT_BASE (0xF500B000) | |
405 | ||
406 | // APB Module audiosys | |
407 | #define AUDIO_BASE (0xF1221000) | |
408 | #define AUDIO_REG_BASE (0xF1220000) | |
409 | ||
410 | // CONNSYS | |
411 | #define CONN_BTSYS_PKV_BASE (0xF8000000) | |
412 | #define CONN_BTSYS_TIMCON_BASE (0xF8010000) | |
413 | #define CONN_BTSYS_RF_CONTROL_BASE (0xF8020000) | |
414 | #define CONN_BTSYS_MODEM_BASE (0xF8030000) | |
415 | #define CONN_BTSYS_BT_CONFIG_BASE (0xF8040000) | |
416 | #define CONN_MCU_CONFIG_BASE (0xF8070000) | |
417 | #define CONN_TOP_CR_BASE (0xF80B0000) | |
418 | #define CONN_HIF_CR_BASE (0xF80F0000) | |
419 | ||
420 | /* | |
421 | * Addresses below are added manually. | |
422 | * They cannot be mapped via IO_VIRT_TO_PHYS(). | |
423 | */ | |
424 | ||
425 | #define GIC_CPU_BASE (CORTEXA7MP_BASE + 0x2000) | |
426 | #define GIC_DIST_BASE (CORTEXA7MP_BASE + 0x1000) | |
427 | #define SYSRAM_BASE 0xF2000000 /* L2 cache shared RAM */ | |
428 | #define DEVINFO_BASE 0xF7000000 | |
429 | #define INTER_SRAM 0xF9000000 | |
430 | ||
431 | #else | |
432 | ||
433 | #define SMI_MMU_TOP_BASE 0xF0205000 | |
434 | #define SMILARB2_BASE 0xF5001000 | |
435 | ||
436 | /* on-chip SRAM */ | |
437 | #define INTER_SRAM 0xF9000000 | |
438 | ||
439 | /* infrasys */ | |
440 | //#define TOPRGU_BASE 0xF0000000 | |
441 | #define INFRA_BASE 0xF0000000 | |
442 | #define INFRACFG_BASE 0xF0001000 | |
443 | #define INFRACFG_AO_BASE 0xF0001000 | |
444 | #define FHCTL_BASE 0xF0002000 | |
445 | #define PERICFG_BASE 0xF0003000 | |
446 | #define DRAMC0_BASE 0xF0004000 | |
447 | #define DDRPHY_BASE 0xF000F000 | |
448 | #define DRAMC_NAO_BASE 0xF020E000 | |
449 | #define GPIO_BASE 0xF0005000 | |
450 | #define GPIO1_BASE 0xF020C000 | |
451 | #define TOPSM_BASE 0xF0006000 | |
452 | #define SPM_BASE 0xF0006000 | |
453 | #define TOPRGU_BASE 0xF0007000 | |
454 | #define AP_RGU_BASE TOPRGU_BASE | |
455 | #define APMCU_GPTIMER_BASE 0xF0008000 | |
456 | #define HACC_BASE 0xF000A000 | |
457 | #define AP_CIRQ_EINT 0xF000B000 | |
458 | #define SMI1_BASE 0xF000C000 | |
459 | #define MIPI_CONFIG_BASE 0xF0010000 | |
460 | // APB Module LVDS ANA | |
461 | #define LVDS_ANA_BASE (0xF0010400) | |
462 | ||
463 | ||
464 | #define KP_BASE 0xF0011000 | |
465 | #if 0 | |
466 | #define DEVICE_APC_0_BASE 0xF0010000 | |
467 | #define DEVICE_APC_1_BASE 0xF0011000 | |
468 | #define DEVICE_APC_2_BASE 0xF0012000 | |
469 | #define DEVICE_APC_3_BASE 0xF0013000 | |
470 | #define DEVICE_APC_4_BASE 0xF0014000 | |
471 | #define SMI0_BASE 0xF0208000 | |
472 | #endif | |
473 | #define EINT_BASE 0xF000B000 | |
474 | ||
475 | ||
476 | #define DEBUGTOP_BASE 0xF0100000 | |
477 | #define MCUSYS_CFGREG_BASE 0xF0200000 | |
478 | #define SRAMROM_BASE 0xF0202000 | |
479 | #define EMI_BASE 0xF0203000 | |
480 | #define EFUSEC_BASE 0xF0206000 | |
481 | #define MCU_BIU_BASE 0xF0208000 | |
482 | #define APMIXED_BASE 0xF0209000 | |
483 | #define APMIXEDSYS_BASE 0xF0209000 | |
484 | #define AP_CCIF_BASE 0xF020A000 | |
485 | #define MD_CCIF_BASE 0xF020B000 | |
486 | #define INFRA_TOP_MBIST_CTRL_BASE 0xF020D000 | |
487 | #define DRAMC_NAO_BASE 0xF020E000 | |
488 | #define CORTEXA7MP_BASE 0xF0210000 | |
489 | #define GIC_CPU_BASE (CORTEXA7MP_BASE + 0x2000) | |
490 | #define GIC_DIST_BASE (CORTEXA7MP_BASE + 0x1000) | |
491 | //#define SMI_LARB_BASE 0xF0211000 | |
492 | //#define MCUSYS_AVS_BASE 0xF0212000 | |
493 | ||
494 | /* perisys */ | |
495 | /*avalaible*/ | |
496 | #define AP_DMA_BASE 0xF1000000 | |
497 | #define AUXADC_BASE 0xF1001000 | |
498 | #define UART1_BASE 0xF1002000 | |
499 | #define UART2_BASE 0xF1003000 | |
500 | #define UART3_BASE 0xF1004000 | |
501 | #define UART4_BASE 0xF1005000 | |
502 | #define PWM_BASE 0xF1006000 | |
503 | #define I2C0_BASE 0xF1007000 | |
504 | #define I2C1_BASE 0xF1008000 | |
505 | #define I2C2_BASE 0xF1009000 | |
506 | #define SPI0_BASE 0xF100A000 | |
507 | #define BTIF_BASE (0xF100C000) | |
508 | #define NFI_BASE 0xF100D000 | |
509 | #define NFIECC_BASE 0xF100E000 | |
510 | #define NLI_ARB_BASE 0xF100F000 | |
511 | #define I2C3_BASE 0xF1010000 //FIXME 6582 take off | |
512 | #define SPI1_BASE 0xF100A000 | |
513 | #define THERMAL_BASE 0xF100B000 | |
514 | ||
515 | // APB Module pmic_wrap | |
516 | #define PWRAP_BASE (0xF000D000) | |
517 | ||
518 | #if 0 | |
519 | //#define IRDA_BASE 0xF1007000 | |
520 | #define I2C4_BASE 0xF1014000 | |
521 | #define I2CDUAL_BASE 0xF1015000 | |
522 | #define ACCDET_BASE 0xF1016000 | |
523 | #define AP_HIF_BASE 0xF1017000 | |
524 | #define MD_HIF_BASE 0xF1018000 | |
525 | #define GCPU_BASE 0xF101B000 | |
526 | #define GCPU_NS_BASE 0xF01C000 | |
527 | #define GCPU_MMU_BASE 0xF01D000 | |
528 | #define SATA_BASE 0xF01E000 | |
529 | #define CEC_BASE 0xF01F000 | |
530 | //#define SPI1_BASE 0xF1022000 | |
531 | #endif | |
532 | ||
533 | #define USB1_BASE 0xF1270000 | |
534 | #define USB2_BASE 0xF1200000 | |
535 | #define USB_BASE 0xF1200000 | |
536 | #define USB_SIF_BASE 0xF1210000 | |
537 | //#define USB3_BASE 0xF1220000 | |
538 | #define MSDC_0_BASE 0xF1230000 | |
539 | #define MSDC_1_BASE 0xF1240000 | |
540 | #define MSDC_2_BASE 0xF1250000 | |
541 | #define MSDC_3_BASE 0xF1260000 | |
542 | #define MSDC_4_BASE 0xF1270000 | |
543 | //#define ETHERNET_BASE 0xF1290000 | |
544 | ||
545 | //#define ETB_BASE 0xF0111000 | |
546 | //#define ETM_BASE 0xF017C000 | |
547 | ||
548 | ||
549 | /* SMI common subsystem */ | |
550 | #define SYSRAM_BASE 0xF2000000 | |
551 | #define AUDIO_REG_BASE 0xF2030000 | |
552 | #define MFG_AXI_BASE 0xF2060000 | |
553 | #define CONN_MCU_CONFIG_BASE 0xF8070000 | |
554 | #define AUDIO_BASE 0xF1200000 //0xF2071000 | |
555 | #define MMSYS1_CONFIG_BASE 0xF2080000 | |
556 | #define SMI_LARB0_BASE 0xF2081000 | |
557 | // APB Module smi | |
558 | #define SMI_BASE (0xF4011000) | |
559 | #define SMI_LARB1_BASE 0xF2082000 | |
560 | #define SMI_LARB2_BASE 0xF2083000 | |
561 | #define VDEC_GCON_BASE 0xF6000000 //0xF4000000 | |
562 | #define VDEC_BASE 0xF4020000 | |
563 | #define VENC_TOP_BASE 0xF7000000 | |
564 | #define VENC_BASE 0xF7002000 | |
565 | #define JPGENC_BASE 0xF500A000 | |
566 | #define R_DMA0_BASE 0xF2086000 | |
567 | #define R_DMA1_BASE 0xF2087000 | |
568 | #define VDO_ROT0_BASE 0xF2088000 | |
569 | #define RGB_ROT0_BASE 0xF2089000 | |
570 | #define VDO_ROT1_BASE 0xF208A000 | |
571 | #define RGB_ROT1_BASE 0xF208B000 | |
572 | //#define DPI_BASE 0xF208C000 | |
573 | #define BRZ_BASE 0xF208D000 | |
574 | #define JPG_DMA_BASE 0xF208E000 | |
575 | #define OVL_DMA_BASE 0xF208F000 | |
576 | #define CSI2_BASE 0xF2092000 | |
577 | #define CRZ_BASE 0xF2093000 | |
578 | #define VRZ0_BASE 0xF2094000 | |
579 | #define IMGPROC_BASE 0xF2095000 | |
580 | #define EIS_BASE 0xF2096000 | |
581 | #define SPI_BASE 0xF2097000 | |
582 | #define SCAM_BASE 0xF2098000 | |
583 | #define PRZ0_BASE 0xF2099000 | |
584 | #define PRZ1_BASE 0xF209A000 | |
585 | #define JPG_CODEC_BASE 0xF209B000 | |
586 | //#define DSI_BASE 0xF209C000 | |
587 | #define TVC_BASE 0xF209D000 | |
588 | #define TVE_BASE 0xF209E000 | |
589 | #define TV_ROT_BASE 0xF209F000 | |
590 | #define RGB_ROT2_BASE 0xF20A0000 | |
591 | //#define LCD_BASE 0xF20A1000 | |
592 | #define FD_BASE 0xF20A2000 | |
593 | #define MIPI_CONFG_BASE 0xF20A3000 | |
594 | #define VRZ1_BASE 0xF20A4000 | |
595 | #define MMSYS2_CONFG_BASE 0xF20C0000 | |
596 | #define SMI_LARB3_BASE 0xF20C1000 | |
597 | #define MFG_APB_BASE 0xF20C4000 | |
598 | #define G2D_BASE 0xF20C6000 | |
599 | ||
600 | #define DISPSYS_BASE 0xF4000000 | |
601 | #define ROT_BASE 0xF4001000 | |
602 | #define SCL_BASE 0xF4002000 | |
603 | #define OVL_BASE 0xF4007000 | |
604 | #define WDMA0_BASE 0xF4009000 | |
605 | #define WDMA1_BASE 0xF4005000 | |
606 | #define RDMA0_BASE 0xF4008000 | |
607 | //#define RDMA1_BASE 0xF4007000 | |
608 | #define BLS_BASE 0xF400A000 | |
609 | //#define GAMMA_BASE 0xF400000 | |
610 | #define COLOR_BASE 0xF400B000 | |
611 | #define TDSHP_BASE 0xF4006000 | |
612 | #define LCD_BASE 0xF4012000// only exist on FPGA | |
613 | #define DSI_BASE 0xF400C000 | |
614 | #define DPI_BASE 0xF400D000 | |
615 | ||
616 | #define DPI1_BASE 0xF4014000 | |
617 | ||
618 | // LVDS TX | |
619 | #define LVDS_TX_BASE (0xF4016200) | |
620 | ||
621 | #define SMILARB1_BASE 0xF4010000 | |
622 | #define DISP_MUTEX_BASE 0xF400E000 | |
623 | #define DISP_CMDQ_BASE 0xF400F000 | |
624 | ||
625 | /* imgsys */ | |
626 | #define IMGSYS_CONFG_BASE 0xF5000000 | |
627 | #define CAMINF_BASE IMGSYS_CONFG_BASE | |
628 | ||
629 | /* G3DSYS */ | |
630 | #define G3D_CONFIG_BASE 0xF3000000 | |
631 | #define MALI_BASE 0xF3040000 | |
632 | ||
633 | #define DEVINFO_BASE 0xF8000000 | |
634 | ||
635 | #endif | |
636 | ||
637 | #endif |