projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 6fa3eb70 S |
1 | #ifndef __MT_EMI_BW_LIMITER__ |
| 2 | #define __MT_EMI_BW_LIMITER__ | |
| 3 | ||
| 4 | /* | |
| 5 | * Define EMI hardware registers. | |
| 6 | */ | |
| 7 | ||
| 8 | #define EMI_CONA (EMI_BASE + 0x0000) | |
| 9 | #define EMI_CONB (EMI_BASE + 0x0008) | |
| 10 | #define EMI_CONC (EMI_BASE + 0x0010) | |
| 11 | #define EMI_COND (EMI_BASE + 0x0018) | |
| 12 | #define EMI_CONE (EMI_BASE + 0x0020) | |
| 13 | #define EMI_CONG (EMI_BASE + 0x0030) | |
| 14 | #define EMI_CONH (EMI_BASE + 0x0038) | |
| 15 | #define EMI_TESTB (EMI_BASE + 0x0E8) | |
| 16 | #define EMI_TESTD (EMI_BASE + 0x0F8) | |
| 17 | #define EMI_ARBA (EMI_BASE + 0x0100) | |
| 18 | #define EMI_ARBB (EMI_BASE + 0x0108) | |
| 19 | #define EMI_ARBC (EMI_BASE + 0x0110) | |
| 20 | #define EMI_ARBD (EMI_BASE + 0x0118) | |
| 21 | #define EMI_ARBE (EMI_BASE + 0x0120) | |
| 22 | #define EMI_ARBF (EMI_BASE + 0x0128) | |
| 23 | #define EMI_ARBG (EMI_BASE + 0x0130) | |
| 24 | #define EMI_ARBI (EMI_BASE + 0x0140) | |
| 25 | #define EMI_ARBI_2ND (EMI_BASE + 0x0144) | |
| 26 | #define EMI_ARBJ (EMI_BASE + 0x0148) | |
| 27 | #define EMI_ARBJ_2ND (EMI_BASE + 0x014C) | |
| 28 | #define EMI_ARBK (EMI_BASE + 0x0150) | |
| 29 | #define EMI_ARBK_2ND (EMI_BASE + 0x0154) | |
| 30 | #define EMI_SLCT (EMI_BASE + 0x0158) | |
| 31 | ||
| 32 | #define DRAMC_CONF1 (0x004) | |
| 33 | #define DRAMC_LPDDR2 (0x1e0) | |
| 34 | #define DRAMC_PADCTL4 (0x0e4) | |
| 35 | #define DRAMC_ACTIM1 (0x1e8) | |
| 36 | #define DRAMC_DQSCAL0 (0x1c0) | |
| 37 | ||
| 38 | #define DRAMC_READ(offset) ( \ | |
| 39 | readl(IOMEM(DRAMC0_BASE + (offset)))| \ | |
| 40 | readl(IOMEM(DDRPHY_BASE + (offset)))| \ | |
| 41 | readl(IOMEM(DRAMC_NAO_BASE + (offset)))) | |
| 42 | ||
| 43 | #define DRAMC_WRITE(offset,data) do{ \ | |
| 44 | writel((unsigned int) (data), (DRAMC0_BASE + (offset))); \ | |
| 45 | writel((unsigned int) (data), (DDRPHY_BASE + (offset))); \ | |
| 46 | mt65xx_reg_sync_writel((unsigned int) (data), (DRAMC_NAO_BASE + (offset))); \ | |
| 47 | }while(0) | |
| 48 | ||
| 49 | ||
| 50 | ||
| 51 | /* | |
| 52 | * Define constants. | |
| 53 | */ | |
| 54 | ||
| 55 | /* define supported DRAM types */ | |
| 56 | enum | |
| 57 | { | |
| 58 | LPDDR2 = 0, | |
| 59 | DDR3_16, | |
| 60 | DDR3_32, | |
| 61 | LPDDR3, | |
| 62 | mDDR, | |
| 63 | }; | |
| 64 | ||
| 65 | /* define concurrency scenario ID */ | |
| 66 | enum | |
| 67 | { | |
| 68 | #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) con_sce, | |
| 69 | #include "mach/con_sce_lpddr2.h" | |
| 70 | #undef X_CON_SCE | |
| 71 | NR_CON_SCE | |
| 72 | }; | |
| 73 | ||
| 74 | /* define control operation */ | |
| 75 | enum | |
| 76 | { | |
| 77 | ENABLE_CON_SCE = 0, | |
| 78 | DISABLE_CON_SCE = 1 | |
| 79 | }; | |
| 80 | ||
| 81 | #define EN_CON_SCE_STR "ON" | |
| 82 | #define DIS_CON_SCE_STR "OFF" | |
| 83 | ||
| 84 | /* | |
| 85 | * Define data structures. | |
| 86 | */ | |
| 87 | ||
| 88 | /* define control table entry */ | |
| 89 | struct emi_bwl_ctrl | |
| 90 | { | |
| 91 | unsigned int ref_cnt; | |
| 92 | }; | |
| 93 | ||
| 94 | /* | |
| 95 | * Define function prototype. | |
| 96 | */ | |
| 97 | ||
| 98 | extern int mtk_mem_bw_ctrl(int sce, int op); | |
| 99 | extern int get_ddr_type(void); | |
| 100 | ||
| 101 | #endif /* !__MT_EMI_BWL_H__ */ | |
| 102 |