projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| fdd8b079 NP |
1 | /* |
| 2 | * arch/arm/mach-kirkwood/include/mach/bridge-regs.h | |
| 3 | * | |
| 4 | * Mbus-L to Mbus Bridge Registers | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public | |
| 7 | * License version 2. This program is licensed "as is" without any | |
| 8 | * warranty of any kind, whether express or implied. | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __ASM_ARCH_BRIDGE_REGS_H | |
| 12 | #define __ASM_ARCH_BRIDGE_REGS_H | |
| 13 | ||
| 14 | #include <mach/kirkwood.h> | |
| 15 | ||
| 2bf30108 LB |
16 | #define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0100) |
| 17 | #define CPU_CONFIG_ERROR_PROP 0x00000004 | |
| 18 | ||
| fdd8b079 NP |
19 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) |
| 20 | #define CPU_RESET 0x00000002 | |
| 21 | ||
| 22 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | |
| 054bd3f0 | 23 | #define WDT_RESET_OUT_EN 0x00000002 |
| fdd8b079 NP |
24 | #define SOFT_RESET_OUT_EN 0x00000004 |
| 25 | ||
| 26 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | |
| 27 | #define SOFT_RESET 0x00000001 | |
| 28 | ||
| 29 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | |
| 054bd3f0 TR |
30 | #define WDT_INT_REQ 0x0008 |
| 31 | ||
| fdd8b079 NP |
32 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
| 33 | ||
| 34 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | |
| 35 | #define IRQ_CAUSE_LOW_OFF 0x0000 | |
| 36 | #define IRQ_MASK_LOW_OFF 0x0004 | |
| 37 | #define IRQ_CAUSE_HIGH_OFF 0x0010 | |
| 38 | #define IRQ_MASK_HIGH_OFF 0x0014 | |
| 39 | ||
| 40 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | |
| 0fa1f060 | 41 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) |
| fdd8b079 NP |
42 | |
| 43 | #define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) | |
| 44 | #define L2_WRITETHROUGH 0x00000010 | |
| 45 | ||
| e8b2b7ba | 46 | #define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c) |
| 2f129bf4 AL |
47 | #define CGC_BIT_GE0 (0) |
| 48 | #define CGC_BIT_PEX0 (2) | |
| 49 | #define CGC_BIT_USB0 (3) | |
| 50 | #define CGC_BIT_SDIO (4) | |
| 51 | #define CGC_BIT_TSU (5) | |
| 52 | #define CGC_BIT_DUNIT (6) | |
| 53 | #define CGC_BIT_RUNIT (7) | |
| 54 | #define CGC_BIT_XOR0 (8) | |
| 55 | #define CGC_BIT_AUDIO (9) | |
| 56 | #define CGC_BIT_SATA0 (14) | |
| 57 | #define CGC_BIT_SATA1 (15) | |
| 58 | #define CGC_BIT_XOR1 (16) | |
| 59 | #define CGC_BIT_CRYPTO (17) | |
| 60 | #define CGC_BIT_PEX1 (18) | |
| 61 | #define CGC_BIT_GE1 (19) | |
| 62 | #define CGC_BIT_TDM (20) | |
| e8b2b7ba RK |
63 | #define CGC_GE0 (1 << 0) |
| 64 | #define CGC_PEX0 (1 << 2) | |
| 65 | #define CGC_USB0 (1 << 3) | |
| 66 | #define CGC_SDIO (1 << 4) | |
| 67 | #define CGC_TSU (1 << 5) | |
| 68 | #define CGC_DUNIT (1 << 6) | |
| 69 | #define CGC_RUNIT (1 << 7) | |
| 70 | #define CGC_XOR0 (1 << 8) | |
| 71 | #define CGC_AUDIO (1 << 9) | |
| 72 | #define CGC_SATA0 (1 << 14) | |
| 73 | #define CGC_SATA1 (1 << 15) | |
| 74 | #define CGC_XOR1 (1 << 16) | |
| 75 | #define CGC_CRYPTO (1 << 17) | |
| ffd58bd2 | 76 | #define CGC_PEX1 (1 << 18) |
| e8b2b7ba RK |
77 | #define CGC_GE1 (1 << 19) |
| 78 | #define CGC_TDM (1 << 20) | |
| ffd58bd2 | 79 | #define CGC_RESERVED (0x6 << 21) |
| e8b2b7ba | 80 | |
| fdd8b079 | 81 | #endif |