projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| a329b48c AK |
1 | /* |
| 2 | * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
| 3 | * | |
| 4 | * The code contained herein is licensed under the GNU General Public | |
| 5 | * License. You may obtain a copy of the GNU General Public License | |
| 6 | * Version 2 or later at the following locations: | |
| 7 | * | |
| 8 | * http://www.opensource.org/licenses/gpl-license.html | |
| 9 | * http://www.gnu.org/copyleft/gpl.html | |
| 10 | */ | |
| 11 | #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ | |
| 12 | #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ | |
| 13 | ||
| 14 | #define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR) | |
| 15 | #define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR) | |
| 16 | #define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR) | |
| 17 | #define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR) | |
| 18 | #define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) | |
| 19 | #define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) | |
| 20 | ||
| c0abefd3 | 21 | /*MX53*/ |
| 644b1d58 YS |
22 | #define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR) |
| 23 | #define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR) | |
| 24 | #define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR) | |
| 25 | #define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) | |
| cdd781ab | 26 | #define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR) |
| c0abefd3 | 27 | |
| a329b48c AK |
28 | /* PLL Register Offsets */ |
| 29 | #define MXC_PLL_DP_CTL 0x00 | |
| 30 | #define MXC_PLL_DP_CONFIG 0x04 | |
| 31 | #define MXC_PLL_DP_OP 0x08 | |
| 32 | #define MXC_PLL_DP_MFD 0x0C | |
| 33 | #define MXC_PLL_DP_MFN 0x10 | |
| 34 | #define MXC_PLL_DP_MFNMINUS 0x14 | |
| 35 | #define MXC_PLL_DP_MFNPLUS 0x18 | |
| 36 | #define MXC_PLL_DP_HFS_OP 0x1C | |
| 37 | #define MXC_PLL_DP_HFS_MFD 0x20 | |
| 38 | #define MXC_PLL_DP_HFS_MFN 0x24 | |
| 39 | #define MXC_PLL_DP_MFN_TOGC 0x28 | |
| 40 | #define MXC_PLL_DP_DESTAT 0x2c | |
| 41 | ||
| 42 | /* PLL Register Bit definitions */ | |
| 43 | #define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 | |
| 44 | #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 | |
| 45 | #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 | |
| 46 | #define MXC_PLL_DP_CTL_ADE 0x800 | |
| 47 | #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 | |
| 48 | #define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) | |
| 49 | #define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 | |
| 50 | #define MXC_PLL_DP_CTL_HFSM 0x80 | |
| 51 | #define MXC_PLL_DP_CTL_PRE 0x40 | |
| 52 | #define MXC_PLL_DP_CTL_UPEN 0x20 | |
| 53 | #define MXC_PLL_DP_CTL_RST 0x10 | |
| 54 | #define MXC_PLL_DP_CTL_RCP 0x8 | |
| 55 | #define MXC_PLL_DP_CTL_PLM 0x4 | |
| 56 | #define MXC_PLL_DP_CTL_BRM0 0x2 | |
| 57 | #define MXC_PLL_DP_CTL_LRF 0x1 | |
| 58 | ||
| 59 | #define MXC_PLL_DP_CONFIG_BIST 0x8 | |
| 60 | #define MXC_PLL_DP_CONFIG_SJC_CE 0x4 | |
| 61 | #define MXC_PLL_DP_CONFIG_AREN 0x2 | |
| 62 | #define MXC_PLL_DP_CONFIG_LDREQ 0x1 | |
| 63 | ||
| 64 | #define MXC_PLL_DP_OP_MFI_OFFSET 4 | |
| 65 | #define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) | |
| 66 | #define MXC_PLL_DP_OP_PDF_OFFSET 0 | |
| 67 | #define MXC_PLL_DP_OP_PDF_MASK 0xF | |
| 68 | ||
| 69 | #define MXC_PLL_DP_MFD_OFFSET 0 | |
| 70 | #define MXC_PLL_DP_MFD_MASK 0x07FFFFFF | |
| 71 | ||
| 72 | #define MXC_PLL_DP_MFN_OFFSET 0x0 | |
| 73 | #define MXC_PLL_DP_MFN_MASK 0x07FFFFFF | |
| 74 | ||
| 75 | #define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) | |
| 76 | #define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) | |
| 77 | #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 | |
| 78 | #define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF | |
| 79 | ||
| 80 | #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) | |
| 81 | #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF | |
| 82 | ||
| 83 | /* Register addresses of CCM*/ | |
| 84 | #define MXC_CCM_CCR (MX51_CCM_BASE + 0x00) | |
| 85 | #define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04) | |
| 86 | #define MXC_CCM_CSR (MX51_CCM_BASE + 0x08) | |
| 87 | #define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C) | |
| 88 | #define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10) | |
| 89 | #define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14) | |
| 90 | #define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18) | |
| 91 | #define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C) | |
| 92 | #define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20) | |
| 93 | #define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24) | |
| 94 | #define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28) | |
| 95 | #define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C) | |
| 96 | #define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30) | |
| 97 | #define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34) | |
| 98 | #define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38) | |
| 99 | #define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C) | |
| 100 | #define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40) | |
| 101 | #define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44) | |
| 102 | #define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48) | |
| 103 | #define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C) | |
| 104 | #define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50) | |
| 105 | #define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) | |
| 106 | #define MXC_CCM_CISR (MX51_CCM_BASE + 0x58) | |
| 107 | #define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C) | |
| 108 | #define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60) | |
| 109 | #define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64) | |
| 110 | #define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68) | |
| 111 | #define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C) | |
| 112 | #define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70) | |
| 113 | #define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74) | |
| 114 | #define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) | |
| 115 | #define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) | |
| 116 | #define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) | |
| fce43f99 FE |
117 | #define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84) |
| 118 | ||
| a329b48c AK |
119 | #define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) |
| 120 | ||
| 121 | /* Define the bits in register CCR */ | |
| 122 | #define MXC_CCM_CCR_COSC_EN (1 << 12) | |
| 123 | #define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11) | |
| 124 | #define MXC_CCM_CCR_CAMP2_EN (1 << 10) | |
| 125 | #define MXC_CCM_CCR_CAMP1_EN (1 << 9) | |
| 126 | #define MXC_CCM_CCR_FPM_EN (1 << 8) | |
| 127 | #define MXC_CCM_CCR_OSCNT_OFFSET (0) | |
| 128 | #define MXC_CCM_CCR_OSCNT_MASK (0xFF) | |
| 129 | ||
| 130 | /* Define the bits in register CCDR */ | |
| 131 | #define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18) | |
| 132 | #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) | |
| 133 | #define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) | |
| 134 | ||
| 135 | /* Define the bits in register CSR */ | |
| 136 | #define MXC_CCM_CSR_COSR_READY (1 << 5) | |
| 137 | #define MXC_CCM_CSR_LVS_VALUE (1 << 4) | |
| 138 | #define MXC_CCM_CSR_CAMP2_READY (1 << 3) | |
| 139 | #define MXC_CCM_CSR_CAMP1_READY (1 << 2) | |
| 140 | #define MXC_CCM_CSR_FPM_READY (1 << 1) | |
| 141 | #define MXC_CCM_CSR_REF_EN_B (1 << 0) | |
| 142 | ||
| 143 | /* Define the bits in register CCSR */ | |
| 144 | #define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) | |
| 145 | #define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) | |
| 146 | #define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) | |
| 147 | #define MXC_CCM_CCSR_STEP_SEL_LP_APM 0 | |
| 148 | #define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */ | |
| 149 | #define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2 | |
| 150 | #define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3 | |
| 151 | #define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) | |
| 152 | #define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) | |
| 153 | #define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) | |
| 154 | #define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) | |
| 155 | #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk, | |
| 156 | 1: step_clk */ | |
| 157 | #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) | |
| 158 | #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) | |
| 159 | ||
| 160 | /* Define the bits in register CACRR */ | |
| 161 | #define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) | |
| 162 | #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) | |
| 163 | ||
| 164 | /* Define the bits in register CBCDR */ | |
| 165 | #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) | |
| 166 | #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) | |
| 167 | #define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) | |
| 168 | #define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) | |
| 169 | #define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) | |
| 170 | #define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) | |
| 171 | #define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) | |
| 172 | #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) | |
| 173 | #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) | |
| 174 | #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) | |
| 175 | #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) | |
| 176 | #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) | |
| 177 | #define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13) | |
| 178 | #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) | |
| 179 | #define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) | |
| 180 | #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) | |
| 181 | #define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) | |
| 182 | #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) | |
| 183 | #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) | |
| 184 | #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) | |
| 185 | #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) | |
| 186 | #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) | |
| 187 | #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) | |
| 188 | #define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) | |
| 189 | ||
| 190 | /* Define the bits in register CBCMR */ | |
| 191 | #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) | |
| 192 | #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) | |
| 193 | #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) | |
| 194 | #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) | |
| 195 | #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) | |
| 196 | #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) | |
| 197 | #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) | |
| 198 | #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) | |
| 199 | #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) | |
| 200 | #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) | |
| 201 | #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) | |
| 202 | #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) | |
| 203 | #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14) | |
| 204 | #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14) | |
| 205 | #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) | |
| 206 | #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) | |
| 207 | ||
| 208 | /* Define the bits in register CSCMR1 */ | |
| 209 | #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) | |
| 210 | #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) | |
| 211 | #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) | |
| 212 | #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) | |
| 213 | #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) | |
| 214 | #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) | |
| 215 | #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) | |
| 216 | #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) | |
| 217 | #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) | |
| 218 | #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) | |
| 219 | #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) | |
| 220 | #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) | |
| 221 | #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) | |
| 35921902 | 222 | #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19) |
| a329b48c AK |
223 | #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) |
| 224 | #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) | |
| 225 | #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) | |
| 35921902 RZ |
226 | #define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16) |
| 227 | #define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16) | |
| a329b48c AK |
228 | #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) |
| 229 | #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) | |
| 230 | #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) | |
| 231 | #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) | |
| 232 | #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) | |
| 233 | #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) | |
| 234 | #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) | |
| 235 | #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) | |
| 236 | #define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) | |
| 237 | #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) | |
| 238 | #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) | |
| 239 | #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) | |
| 240 | #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) | |
| 241 | #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) | |
| 242 | #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) | |
| 243 | #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) | |
| 244 | ||
| 245 | /* Define the bits in register CSCMR2 */ | |
| 246 | #define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) | |
| 247 | #define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) | |
| 248 | #define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) | |
| 249 | #define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) | |
| 250 | #define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) | |
| 251 | #define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) | |
| 252 | #define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) | |
| 253 | #define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) | |
| 254 | #define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) | |
| 255 | #define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) | |
| 256 | #define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) | |
| 257 | #define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) | |
| 258 | #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) | |
| 259 | #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) | |
| 260 | #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) | |
| 261 | #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) | |
| 262 | #define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) | |
| 263 | #define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) | |
| 264 | #define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) | |
| 265 | #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) | |
| 266 | #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) | |
| 267 | #define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) | |
| 268 | #define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) | |
| 269 | #define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) | |
| 270 | #define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) | |
| 271 | #define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) | |
| 272 | #define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) | |
| 273 | ||
| 274 | /* Define the bits in register CSCDR1 */ | |
| 275 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) | |
| 276 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) | |
| 277 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) | |
| 278 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) | |
| 35921902 RZ |
279 | #define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22) |
| 280 | #define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22) | |
| 281 | #define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19) | |
| 282 | #define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19) | |
| a329b48c AK |
283 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) |
| 284 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) | |
| 285 | #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) | |
| 286 | #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) | |
| 287 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) | |
| 288 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) | |
| 289 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) | |
| 290 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) | |
| 291 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) | |
| 292 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) | |
| 293 | #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) | |
| 294 | #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) | |
| 295 | #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) | |
| 296 | #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) | |
| 297 | ||
| 298 | /* Define the bits in register CS1CDR and CS2CDR */ | |
| 299 | #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) | |
| 300 | #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) | |
| 301 | #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) | |
| 302 | #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) | |
| 303 | #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) | |
| 304 | #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) | |
| 305 | #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) | |
| 306 | #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) | |
| 307 | ||
| 308 | #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) | |
| 309 | #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) | |
| 310 | #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) | |
| 311 | #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) | |
| 312 | #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) | |
| 313 | #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) | |
| 314 | #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) | |
| 315 | #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) | |
| 316 | ||
| 317 | /* Define the bits in register CDCDR */ | |
| 318 | #define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) | |
| 319 | #define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) | |
| 320 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) | |
| 321 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) | |
| 322 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) | |
| 323 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) | |
| 324 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) | |
| 325 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) | |
| 326 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) | |
| 327 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) | |
| 328 | #define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) | |
| 329 | #define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) | |
| 330 | #define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) | |
| 331 | #define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) | |
| 332 | #define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) | |
| 333 | #define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) | |
| 334 | ||
| 335 | /* Define the bits in register CHSCCDR */ | |
| 336 | #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) | |
| 337 | #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) | |
| 338 | #define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) | |
| 339 | #define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) | |
| 340 | #define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) | |
| 341 | #define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) | |
| 342 | #define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) | |
| 343 | #define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) | |
| 344 | ||
| 345 | /* Define the bits in register CSCDR2 */ | |
| 346 | #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) | |
| 347 | #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) | |
| 348 | #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) | |
| 349 | #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) | |
| 350 | #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) | |
| 351 | #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) | |
| 352 | #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) | |
| 353 | #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) | |
| 354 | #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) | |
| 355 | #define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) | |
| 356 | #define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) | |
| 357 | #define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) | |
| 358 | ||
| 359 | /* Define the bits in register CSCDR3 */ | |
| 360 | #define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) | |
| 361 | #define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) | |
| 362 | #define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) | |
| 363 | #define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) | |
| 364 | #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) | |
| 365 | #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) | |
| 366 | #define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) | |
| 367 | #define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) | |
| 368 | ||
| 369 | /* Define the bits in register CSCDR4 */ | |
| 370 | #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) | |
| 371 | #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) | |
| 372 | #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) | |
| 373 | #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) | |
| 374 | #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) | |
| 375 | #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) | |
| 376 | #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) | |
| 377 | #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) | |
| 378 | ||
| 379 | /* Define the bits in register CDHIPR */ | |
| 380 | #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) | |
| 381 | #define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8) | |
| 382 | #define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7) | |
| 383 | #define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) | |
| 384 | #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) | |
| 385 | #define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) | |
| 386 | #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) | |
| 387 | #define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) | |
| 388 | #define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) | |
| 389 | #define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) | |
| 390 | ||
| 391 | /* Define the bits in register CDCR */ | |
| 392 | #define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) | |
| 393 | #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) | |
| 394 | #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) | |
| 395 | ||
| 396 | /* Define the bits in register CLPCR */ | |
| 397 | #define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) | |
| 398 | #define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) | |
| c0abefd3 DN |
399 | #define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) |
| 400 | #define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) | |
| a329b48c AK |
401 | #define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) |
| 402 | #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) | |
| 403 | #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) | |
| 404 | #define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) | |
| 405 | #define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) | |
| 406 | #define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) | |
| 407 | #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) | |
| 408 | #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) | |
| 409 | #define MXC_CCM_CLPCR_VSTBY (0x1 << 8) | |
| 410 | #define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) | |
| 411 | #define MXC_CCM_CLPCR_SBYOS (0x1 << 6) | |
| 412 | #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) | |
| 413 | #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) | |
| 414 | #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) | |
| 415 | #define MXC_CCM_CLPCR_LPM_OFFSET (0) | |
| 416 | #define MXC_CCM_CLPCR_LPM_MASK (0x3) | |
| 417 | ||
| 418 | /* Define the bits in register CISR */ | |
| 419 | #define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) | |
| 420 | #define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) | |
| 421 | #define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) | |
| 422 | #define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) | |
| 423 | #define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) | |
| 424 | #define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) | |
| 425 | #define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) | |
| 426 | #define MXC_CCM_CISR_COSC_READY (0x1 << 6) | |
| 427 | #define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) | |
| 428 | #define MXC_CCM_CISR_CKIH_READY (0x1 << 4) | |
| 429 | #define MXC_CCM_CISR_FPM_READY (0x1 << 3) | |
| 430 | #define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) | |
| 431 | #define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) | |
| 432 | #define MXC_CCM_CISR_LRF_PLL1 (0x1) | |
| 433 | ||
| 434 | /* Define the bits in register CIMR */ | |
| 435 | #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) | |
| 436 | #define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) | |
| 437 | #define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) | |
| 438 | #define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) | |
| 439 | #define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) | |
| 440 | #define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) | |
| 441 | #define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) | |
| 442 | #define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) | |
| 443 | #define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) | |
| 444 | #define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) | |
| 445 | #define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) | |
| 446 | #define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) | |
| 447 | #define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) | |
| 448 | ||
| 449 | /* Define the bits in register CCOSR */ | |
| 450 | #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) | |
| 451 | #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) | |
| 452 | #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) | |
| 453 | #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) | |
| 454 | #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) | |
| 455 | #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) | |
| 456 | #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) | |
| 457 | #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) | |
| 458 | #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) | |
| 459 | #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) | |
| 460 | ||
| 461 | /* Define the bits in registers CGPR */ | |
| 462 | #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) | |
| 463 | #define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) | |
| 464 | #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) | |
| 465 | #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) | |
| 466 | ||
| 467 | /* Define the bits in registers CCGRx */ | |
| 468 | #define MXC_CCM_CCGRx_CG_MASK 0x3 | |
| 469 | #define MXC_CCM_CCGRx_MOD_OFF 0x0 | |
| 470 | #define MXC_CCM_CCGRx_MOD_ON 0x3 | |
| 471 | #define MXC_CCM_CCGRx_MOD_IDLE 0x1 | |
| 472 | ||
| 473 | #define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30) | |
| 474 | #define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28) | |
| 475 | #define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26) | |
| 476 | #define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24) | |
| 477 | #define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22) | |
| 478 | #define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20) | |
| 479 | #define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18) | |
| 480 | #define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16) | |
| 481 | #define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10) | |
| 482 | #define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8) | |
| 483 | #define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6) | |
| 484 | #define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4) | |
| 485 | #define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2) | |
| 486 | #define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0) | |
| 487 | ||
| 488 | #define MXC_CCM_CCGRx_CG15_OFFSET 30 | |
| 489 | #define MXC_CCM_CCGRx_CG14_OFFSET 28 | |
| 490 | #define MXC_CCM_CCGRx_CG13_OFFSET 26 | |
| 491 | #define MXC_CCM_CCGRx_CG12_OFFSET 24 | |
| 492 | #define MXC_CCM_CCGRx_CG11_OFFSET 22 | |
| 493 | #define MXC_CCM_CCGRx_CG10_OFFSET 20 | |
| 494 | #define MXC_CCM_CCGRx_CG9_OFFSET 18 | |
| 495 | #define MXC_CCM_CCGRx_CG8_OFFSET 16 | |
| 496 | #define MXC_CCM_CCGRx_CG7_OFFSET 14 | |
| 497 | #define MXC_CCM_CCGRx_CG6_OFFSET 12 | |
| 498 | #define MXC_CCM_CCGRx_CG5_OFFSET 10 | |
| 499 | #define MXC_CCM_CCGRx_CG4_OFFSET 8 | |
| 500 | #define MXC_CCM_CCGRx_CG3_OFFSET 6 | |
| 501 | #define MXC_CCM_CCGRx_CG2_OFFSET 4 | |
| 502 | #define MXC_CCM_CCGRx_CG1_OFFSET 2 | |
| 503 | #define MXC_CCM_CCGRx_CG0_OFFSET 0 | |
| 504 | ||
| 505 | #define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80) | |
| 506 | #define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100) | |
| 507 | #define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180) | |
| 508 | #define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0) | |
| 509 | #define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) | |
| 510 | #define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) | |
| 511 | #define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) | |
| 512 | #define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280) | |
| 513 | #define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0) | |
| 514 | #define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0) | |
| 515 | #define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0) | |
| 516 | #define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0) | |
| 517 | #define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300) | |
| 518 | ||
| 519 | /* CORTEXA8 platform */ | |
| 520 | #define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) | |
| 521 | #define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) | |
| 522 | #define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) | |
| 523 | #define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) | |
| 524 | #define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) | |
| 525 | #define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) | |
| 526 | #define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) | |
| 527 | #define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) | |
| 528 | #define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) | |
| 529 | ||
| 530 | /* DVFS CORE */ | |
| 531 | #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) | |
| 532 | #define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) | |
| 533 | #define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) | |
| 534 | #define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) | |
| 535 | #define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) | |
| 536 | #define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) | |
| 537 | #define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) | |
| 538 | #define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) | |
| 539 | #define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) | |
| 540 | #define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) | |
| 541 | #define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) | |
| 542 | #define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) | |
| 543 | #define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) | |
| 544 | #define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) | |
| 545 | #define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) | |
| 546 | #define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) | |
| 547 | #define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) | |
| 548 | ||
| 549 | /* GPC */ | |
| 550 | #define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0) | |
| 551 | #define MXC_GPC_PGR (MX51_GPC_BASE + 0x4) | |
| 552 | #define MXC_GPC_VCR (MX51_GPC_BASE + 0x8) | |
| 553 | #define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC) | |
| 554 | #define MXC_GPC_NEON (MX51_GPC_BASE + 0x10) | |
| 555 | #define MXC_GPC_PGR_ARMPG_OFFSET 8 | |
| 556 | #define MXC_GPC_PGR_ARMPG_MASK (3 << 8) | |
| 557 | ||
| 558 | /* PGC */ | |
| 559 | #define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) | |
| 560 | #define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) | |
| 561 | #define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) | |
| 562 | #define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) | |
| 563 | #define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0) | |
| 564 | #define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC) | |
| 565 | ||
| 566 | #define MXC_PGCR_PCR 1 | |
| 567 | #define MXC_SRPGCR_PCR 1 | |
| 568 | #define MXC_EMPGCR_PCR 1 | |
| 569 | #define MXC_PGSR_PSR 1 | |
| 570 | ||
| 571 | ||
| 572 | #define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) | |
| 573 | #define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) | |
| 574 | ||
| 575 | /* SRPG */ | |
| 576 | #define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0) | |
| 577 | #define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4) | |
| 578 | #define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8) | |
| 579 | ||
| 580 | #define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0) | |
| 581 | #define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4) | |
| 582 | #define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8) | |
| 583 | ||
| 584 | #define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0) | |
| 585 | #define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4) | |
| 586 | #define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8) | |
| 587 | ||
| 588 | #define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0) | |
| 589 | #define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4) | |
| 590 | #define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8) | |
| 591 | ||
| 592 | #define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0) | |
| 593 | #define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4) | |
| 594 | #define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8) | |
| 595 | ||
| 596 | #define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0) | |
| 597 | #define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4) | |
| 598 | #define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8) | |
| 599 | ||
| 600 | #endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ |