[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-cns3xxx / pm.c

/*
 * Copyright 2008 Cavium Networks
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/atomic.h>
#include <mach/system.h>
#include <mach/cns3xxx.h>
#include <mach/pm.h>

void cns3xxx_pwr_clk_en(unsigned int block)
{
	u32 reg = __raw_readl(PM_CLK_GATE_REG);

	reg |= (block & PM_CLK_GATE_REG_MASK);
	__raw_writel(reg, PM_CLK_GATE_REG);
}
EXPORT_SYMBOL(cns3xxx_pwr_clk_en);

void cns3xxx_pwr_clk_dis(unsigned int block)
{
	u32 reg = __raw_readl(PM_CLK_GATE_REG);

	reg &= ~(block & PM_CLK_GATE_REG_MASK);
	__raw_writel(reg, PM_CLK_GATE_REG);
}
EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);

void cns3xxx_pwr_power_up(unsigned int block)
{
	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);

	reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);

	/* Wait for 300us for the PLL output clock locked. */
	udelay(300);
};
EXPORT_SYMBOL(cns3xxx_pwr_power_up);

void cns3xxx_pwr_power_down(unsigned int block)
{
	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);

	/* write '1' to power down */
	reg |= (block & CNS3XXX_PWR_PLL_ALL);
	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
};
EXPORT_SYMBOL(cns3xxx_pwr_power_down);

static void cns3xxx_pwr_soft_rst_force(unsigned int block)
{
	u32 reg = __raw_readl(PM_SOFT_RST_REG);

	/*
	 * bit 0, 28, 29 => program low to reset,
	 * the other else program low and then high
	 */
	if (block & 0x30000001) {
		reg &= ~(block & PM_SOFT_RST_REG_MASK);
	} else {
		reg &= ~(block & PM_SOFT_RST_REG_MASK);
		__raw_writel(reg, PM_SOFT_RST_REG);
		reg |= (block & PM_SOFT_RST_REG_MASK);
	}

	__raw_writel(reg, PM_SOFT_RST_REG);
}
EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);

void cns3xxx_pwr_soft_rst(unsigned int block)
{
	static unsigned int soft_reset;

	if (soft_reset & block) {
		/* SPI/I2C/GPIO use the same block, reset once. */
		return;
	} else {
		soft_reset |= block;
	}
	cns3xxx_pwr_soft_rst_force(block);
}
EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);

void arch_reset(char mode, const char *cmd)
{
	/*
	 * To reset, we hit the on-board reset register
	 * in the system FPGA.
	 */
	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
}

/*
 * cns3xxx_cpu_clock - return CPU/L2 clock
 *  aclk: cpu clock/2
 *  hclk: cpu clock/4
 *  pclk: cpu clock/8
 */
int cns3xxx_cpu_clock(void)
{
	u32 reg = __raw_readl(PM_CLK_CTRL_REG);
	int cpu;
	int cpu_sel;
	int div_sel;

	cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
	div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;

	cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;

	return cpu;
}
EXPORT_SYMBOL(cns3xxx_cpu_clock);

atomic_t usb_pwr_ref = ATOMIC_INIT(0);
EXPORT_SYMBOL(usb_pwr_ref);
Commit	Line	Data
d94f944e AV	1	/*
	2	* Copyright 2008 Cavium Networks
	3	*
	4	* This file is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License, Version 2, as
	6	* published by the Free Software Foundation.
	7	*/
	8
38e64ba0 ML	9	#include <linux/init.h>
38e64ba0 ML	10	#include <linux/module.h>
6eb5d146	11	#include <linux/io.h>
d94f944e	12	#include <linux/delay.h>
60063497	13	#include <linux/atomic.h>
d94f944e AV	14	#include <mach/system.h>
d94f944e AV	15	#include <mach/cns3xxx.h>
38e64ba0	16	#include <mach/pm.h>
d94f944e AV	17
	18	void cns3xxx_pwr_clk_en(unsigned int block)
	19	{
6eb5d146 AV	20	u32 reg = __raw_readl(PM_CLK_GATE_REG);
	21
	22	reg \|= (block & PM_CLK_GATE_REG_MASK);
	23	__raw_writel(reg, PM_CLK_GATE_REG);
d94f944e	24	}
38e64ba0 ML	25	EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
	26
	27	void cns3xxx_pwr_clk_dis(unsigned int block)
	28	{
	29	u32 reg = __raw_readl(PM_CLK_GATE_REG);
	30
	31	reg &= ~(block & PM_CLK_GATE_REG_MASK);
	32	__raw_writel(reg, PM_CLK_GATE_REG);
	33	}
	34	EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
d94f944e AV	35
	36	void cns3xxx_pwr_power_up(unsigned int block)
	37	{
6eb5d146 AV	38	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
	39
	40	reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
	41	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
d94f944e AV	42
	43	/* Wait for 300us for the PLL output clock locked. */
	44	udelay(300);
	45	};
38e64ba0	46	EXPORT_SYMBOL(cns3xxx_pwr_power_up);
d94f944e AV	47
	48	void cns3xxx_pwr_power_down(unsigned int block)
	49	{
6eb5d146 AV	50	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
6eb5d146 AV	51
d94f944e	52	/* write '1' to power down */
6eb5d146 AV	53	reg \|= (block & CNS3XXX_PWR_PLL_ALL);
6eb5d146 AV	54	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
d94f944e	55	};
38e64ba0	56	EXPORT_SYMBOL(cns3xxx_pwr_power_down);
d94f944e AV	57
	58	static void cns3xxx_pwr_soft_rst_force(unsigned int block)
	59	{
6eb5d146 AV	60	u32 reg = __raw_readl(PM_SOFT_RST_REG);
6eb5d146 AV	61
d94f944e AV	62	/*
	63	* bit 0, 28, 29 => program low to reset,
	64	* the other else program low and then high
	65	*/
	66	if (block & 0x30000001) {
6eb5d146	67	reg &= ~(block & PM_SOFT_RST_REG_MASK);
d94f944e	68	} else {
6eb5d146	69	reg &= ~(block & PM_SOFT_RST_REG_MASK);
df8f4d2f	70	__raw_writel(reg, PM_SOFT_RST_REG);
6eb5d146	71	reg \|= (block & PM_SOFT_RST_REG_MASK);
d94f944e	72	}
6eb5d146 AV	73
6eb5d146 AV	74	__raw_writel(reg, PM_SOFT_RST_REG);
d94f944e	75	}
38e64ba0	76	EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);
d94f944e AV	77
	78	void cns3xxx_pwr_soft_rst(unsigned int block)
	79	{
	80	static unsigned int soft_reset;
	81
	82	if (soft_reset & block) {
	83	/* SPI/I2C/GPIO use the same block, reset once. */
	84	return;
	85	} else {
	86	soft_reset \|= block;
	87	}
	88	cns3xxx_pwr_soft_rst_force(block);
	89	}
38e64ba0	90	EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
d94f944e AV	91
	92	void arch_reset(char mode, const char *cmd)
	93	{
	94	/*
	95	* To reset, we hit the on-board reset register
	96	* in the system FPGA.
	97	*/
	98	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
	99	}
	100
	101	/*
	102	* cns3xxx_cpu_clock - return CPU/L2 clock
	103	* aclk: cpu clock/2
	104	* hclk: cpu clock/4
	105	* pclk: cpu clock/8
	106	*/
	107	int cns3xxx_cpu_clock(void)
	108	{
6eb5d146	109	u32 reg = __raw_readl(PM_CLK_CTRL_REG);
d94f944e AV	110	int cpu;
	111	int cpu_sel;
	112	int div_sel;
	113
6eb5d146 AV	114	cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
6eb5d146 AV	115	div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
d94f944e AV	116
	117	cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
	118
	119	return cpu;
	120	}
38e64ba0	121	EXPORT_SYMBOL(cns3xxx_cpu_clock);
cf36797f ML	122
	123	atomic_t usb_pwr_ref = ATOMIC_INIT(0);
	124	EXPORT_SYMBOL(usb_pwr_ref);