[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-cns3xxx / core.c

/*
 * Copyright 1999 - 2003 ARM Limited
 * Copyright 2000 Deep Blue Solutions Ltd
 * Copyright 2008 Cavium Networks
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/cns3xxx.h>
#include "core.h"

static struct map_desc cns3xxx_io_desc[] __initdata = {
	{
		.virtual	= CNS3XXX_TC11MP_SCU_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
		.length		= SZ_8K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= CNS3XXX_TIMER1_2_3_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= CNS3XXX_GPIOA_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_GPIOA_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= CNS3XXX_GPIOB_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_GPIOB_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= CNS3XXX_MISC_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_MISC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= CNS3XXX_PM_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_PM_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

void __init cns3xxx_map_io(void)
{
	iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
}

/* used by entry-macro.S */
void __init cns3xxx_init_irq(void)
{
	gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
		 IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
}

void cns3xxx_power_off(void)
{
	u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT);
	u32 clkctrl;

	printk(KERN_INFO "powering system down...\n");

	clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET);
	clkctrl &= 0xfffff1ff;
	clkctrl |= (0x5 << 9);		/* Hibernate */
	writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);

}

/*
 * Timer
 */
static void __iomem *cns3xxx_tmr1;

static void cns3xxx_timer_set_mode(enum clock_event_mode mode,
				   struct clock_event_device *clk)
{
	unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	int pclk = cns3xxx_cpu_clock() / 8;
	int reload;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		reload = pclk * 20 / (3 * HZ) * 0x25000;
		writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
		ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* period set, and timer enabled in 'next_event' hook */
		ctrl |= (1 << 2) | (1 << 9);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		ctrl = 0;
	}

	writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
}

static int cns3xxx_timer_set_next_event(unsigned long evt,
					struct clock_event_device *unused)
{
	unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);

	writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
	writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);

	return 0;
}

static struct clock_event_device cns3xxx_tmr1_clockevent = {
	.name		= "cns3xxx timer1",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= cns3xxx_timer_set_mode,
	.set_next_event	= cns3xxx_timer_set_next_event,
	.rating		= 350,
	.cpumask	= cpu_all_mask,
};

static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
{
	cns3xxx_tmr1_clockevent.irq = timer_irq;
	clockevents_config_and_register(&cns3xxx_tmr1_clockevent,
					(cns3xxx_cpu_clock() >> 3) * 1000000,
					0xf, 0xffffffff);
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &cns3xxx_tmr1_clockevent;
	u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET;
	u32 val;

	/* Clear the interrupt */
	val = readl(stat);
	writel(val & ~(1 << 2), stat);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction cns3xxx_timer_irq = {
	.name		= "timer",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= cns3xxx_timer_interrupt,
};

/*
 * Set up the clock source and clock events devices
 */
static void __init __cns3xxx_timer_init(unsigned int timer_irq)
{
	u32 val;
	u32 irq_mask;

	/*
	 * Initialise to a known state (all timers off)
	 */

	/* disable timer1 and timer2 */
	writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	/* stop free running timer3 */
	writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);

	/* timer1 */
	writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
	writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);

	writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
	writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);

	/* mask irq, non-mask timer1 overflow */
	irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
	irq_mask &= ~(1 << 2);
	irq_mask |= 0x03;
	writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);

	/* down counter */
	val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	val |= (1 << 9);
	writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);

	/* timer2 */
	writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
	writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);

	/* mask irq */
	irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
	irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
	writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);

	/* down counter */
	val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	val |= (1 << 10);
	writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);

	/* Make irqs happen for the system timer */
	setup_irq(timer_irq, &cns3xxx_timer_irq);

	cns3xxx_clockevents_init(timer_irq);
}

void __init cns3xxx_timer_init(void)
{
	cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);

	__cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
}

#ifdef CONFIG_CACHE_L2X0

void __init cns3xxx_l2x0_init(void)
{
	void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
	u32 val;

	if (WARN_ON(!base))
		return;

	/*
	 * Tag RAM Control register
	 *
	 * bit[10:8]	- 1 cycle of write accesses latency
	 * bit[6:4]	- 1 cycle of read accesses latency
	 * bit[3:0]	- 1 cycle of setup latency
	 *
	 * 1 cycle of latency for setup, read and write accesses
	 */
	val = readl(base + L2X0_TAG_LATENCY_CTRL);
	val &= 0xfffff888;
	writel(val, base + L2X0_TAG_LATENCY_CTRL);

	/*
	 * Data RAM Control register
	 *
	 * bit[10:8]	- 1 cycles of write accesses latency
	 * bit[6:4]	- 1 cycles of read accesses latency
	 * bit[3:0]	- 1 cycle of setup latency
	 *
	 * 1 cycle of latency for setup, read and write accesses
	 */
	val = readl(base + L2X0_DATA_LATENCY_CTRL);
	val &= 0xfffff888;
	writel(val, base + L2X0_DATA_LATENCY_CTRL);

	/* 32 KiB, 8-way, parity disable */
	l2x0_init(base, 0x00540000, 0xfe000fff);
}

#endif /* CONFIG_CACHE_L2X0 */
Commit	Line	Data
d94f944e AV	1	/*
	2	* Copyright 1999 - 2003 ARM Limited
	3	* Copyright 2000 Deep Blue Solutions Ltd
	4	* Copyright 2008 Cavium Networks
	5	*
	6	* This file is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License, Version 2, as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/clockchips.h>
	14	#include <linux/io.h>
520f7bd7	15	#include <linux/irqchip/arm-gic.h>
d94f944e AV	16	#include <asm/mach/map.h>
	17	#include <asm/mach/time.h>
	18	#include <asm/mach/irq.h>
93e85d8e	19	#include <asm/hardware/cache-l2x0.h>
d94f944e AV	20	#include <mach/cns3xxx.h>
	21	#include "core.h"
	22
	23	static struct map_desc cns3xxx_io_desc[] __initdata = {
	24	{
a3d9052c ML	25	.virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
	26	.pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
	27	.length = SZ_8K,
d94f944e AV	28	.type = MT_DEVICE,
	29	}, {
	30	.virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
	31	.pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
	32	.length = SZ_4K,
	33	.type = MT_DEVICE,
	34	}, {
	35	.virtual = CNS3XXX_GPIOA_BASE_VIRT,
	36	.pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
	37	.length = SZ_4K,
	38	.type = MT_DEVICE,
	39	}, {
	40	.virtual = CNS3XXX_GPIOB_BASE_VIRT,
	41	.pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
	42	.length = SZ_4K,
	43	.type = MT_DEVICE,
	44	}, {
	45	.virtual = CNS3XXX_MISC_BASE_VIRT,
	46	.pfn = __phys_to_pfn(CNS3XXX_MISC_BASE),
	47	.length = SZ_4K,
	48	.type = MT_DEVICE,
	49	}, {
	50	.virtual = CNS3XXX_PM_BASE_VIRT,
	51	.pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
	52	.length = SZ_4K,
	53	.type = MT_DEVICE,
	54	},
	55	};
	56
	57	void __init cns3xxx_map_io(void)
	58	{
	59	iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
	60	}
	61
	62	/* used by entry-macro.S */
d94f944e AV	63	void __init cns3xxx_init_irq(void)
d94f944e AV	64	{
a2a47ca3 RH	65	gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
a2a47ca3 RH	66	IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
d94f944e AV	67	}
	68
	69	void cns3xxx_power_off(void)
	70	{
a2a47ca3	71	u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT);
d94f944e AV	72	u32 clkctrl;
	73
	74	printk(KERN_INFO "powering system down...\n");
	75
	76	clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET);
	77	clkctrl &= 0xfffff1ff;
	78	clkctrl \|= (0x5 << 9); /* Hibernate */
	79	writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);
	80
	81	}
	82
	83	/*
	84	* Timer
	85	*/
	86	static void __iomem *cns3xxx_tmr1;
	87
	88	static void cns3xxx_timer_set_mode(enum clock_event_mode mode,
	89	struct clock_event_device *clk)
	90	{
	91	unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	92	int pclk = cns3xxx_cpu_clock() / 8;
	93	int reload;
	94
	95	switch (mode) {
	96	case CLOCK_EVT_MODE_PERIODIC:
	97	reload = pclk * 20 / (3 * HZ) * 0x25000;
	98	writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
	99	ctrl \|= (1 << 0) \| (1 << 2) \| (1 << 9);
	100	break;
	101	case CLOCK_EVT_MODE_ONESHOT:
	102	/* period set, and timer enabled in 'next_event' hook */
	103	ctrl \|= (1 << 2) \| (1 << 9);
	104	break;
	105	case CLOCK_EVT_MODE_UNUSED:
	106	case CLOCK_EVT_MODE_SHUTDOWN:
	107	default:
	108	ctrl = 0;
	109	}
	110
	111	writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	112	}
	113
	114	static int cns3xxx_timer_set_next_event(unsigned long evt,
	115	struct clock_event_device *unused)
	116	{
	117	unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	118
	119	writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
	120	writel(ctrl \| (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	121
	122	return 0;
	123	}
	124
	125	static struct clock_event_device cns3xxx_tmr1_clockevent = {
	126	.name = "cns3xxx timer1",
d94f944e AV	127	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	128	.set_mode = cns3xxx_timer_set_mode,
	129	.set_next_event = cns3xxx_timer_set_next_event,
	130	.rating = 350,
	131	.cpumask = cpu_all_mask,
	132	};
	133
	134	static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
	135	{
	136	cns3xxx_tmr1_clockevent.irq = timer_irq;
838a2ae8 SG	137	clockevents_config_and_register(&cns3xxx_tmr1_clockevent,
	138	(cns3xxx_cpu_clock() >> 3) * 1000000,
	139	0xf, 0xffffffff);
d94f944e AV	140	}
	141
	142	/*
	143	* IRQ handler for the timer
	144	*/
	145	static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
	146	{
	147	struct clock_event_device *evt = &cns3xxx_tmr1_clockevent;
	148	u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET;
	149	u32 val;
	150
	151	/* Clear the interrupt */
	152	val = readl(stat);
	153	writel(val & ~(1 << 2), stat);
	154
	155	evt->event_handler(evt);
	156
	157	return IRQ_HANDLED;
	158	}
	159
	160	static struct irqaction cns3xxx_timer_irq = {
	161	.name = "timer",
	162	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	163	.handler = cns3xxx_timer_interrupt,
	164	};
	165
	166	/*
	167	* Set up the clock source and clock events devices
	168	*/
	169	static void __init __cns3xxx_timer_init(unsigned int timer_irq)
	170	{
	171	u32 val;
	172	u32 irq_mask;
	173
	174	/*
	175	* Initialise to a known state (all timers off)
	176	*/
	177
	178	/* disable timer1 and timer2 */
	179	writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	180	/* stop free running timer3 */
	181	writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
	182
	183	/* timer1 */
	184	writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
	185	writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
	186
	187	writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
	188	writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
	189
	190	/* mask irq, non-mask timer1 overflow */
	191	irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
	192	irq_mask &= ~(1 << 2);
	193	irq_mask \|= 0x03;
	194	writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
	195
	196	/* down counter */
	197	val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	198	val \|= (1 << 9);
	199	writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	200
	201	/* timer2 */
	202	writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
	203	writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
204
205	/* mask irq */
206	irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
207	irq_mask \|= ((1 << 3) \| (1 << 4) \| (1 << 5));
208	writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
209
210	/* down counter */
211	val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
212	val \|= (1 << 10);
213	writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
214
215	/* Make irqs happen for the system timer */
216	setup_irq(timer_irq, &cns3xxx_timer_irq);
217
218	cns3xxx_clockevents_init(timer_irq);
219	}
220
6bb27d73	221	void __init cns3xxx_timer_init(void)
d94f944e	222	{
a2a47ca3	223	cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);
d94f944e AV	224
	225	__cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
	226	}
	227
93e85d8e AV	228	#ifdef CONFIG_CACHE_L2X0
	229
	230	void __init cns3xxx_l2x0_init(void)
	231	{
	232	void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
	233	u32 val;
	234
	235	if (WARN_ON(!base))
	236	return;
	237
	238	/*
	239	* Tag RAM Control register
	240	*
	241	* bit[10:8] - 1 cycle of write accesses latency
	242	* bit[6:4] - 1 cycle of read accesses latency
	243	* bit[3:0] - 1 cycle of setup latency
	244	*
	245	* 1 cycle of latency for setup, read and write accesses
	246	*/
	247	val = readl(base + L2X0_TAG_LATENCY_CTRL);
	248	val &= 0xfffff888;
	249	writel(val, base + L2X0_TAG_LATENCY_CTRL);
	250
	251	/*
	252	* Data RAM Control register
	253	*
	254	* bit[10:8] - 1 cycles of write accesses latency
	255	* bit[6:4] - 1 cycles of read accesses latency
	256	* bit[3:0] - 1 cycle of setup latency
	257	*
	258	* 1 cycle of latency for setup, read and write accesses
	259	*/
	260	val = readl(base + L2X0_DATA_LATENCY_CTRL);
	261	val &= 0xfffff888;
	262	writel(val, base + L2X0_DATA_LATENCY_CTRL);
	263
	264	/* 32 KiB, 8-way, parity disable */
	265	l2x0_init(base, 0x00540000, 0xfe000fff);
	266	}
	267
	268	#endif /* CONFIG_CACHE_L2X0 */