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877d7720 AV |
1 | /* |
2 | * arch/arm/mach-at91/at91sam9rl.c | |
3 | * | |
4 | * Copyright (C) 2005 SAN People | |
5 | * Copyright (C) 2007 Atmel Corporation | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file COPYING in the main directory of this archive for | |
9 | * more details. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
3ef2fb42 | 13 | #include <linux/pm.h> |
877d7720 AV |
14 | |
15 | #include <asm/mach/arch.h> | |
16 | #include <asm/mach/map.h> | |
a09e64fb RK |
17 | #include <mach/cpu.h> |
18 | #include <mach/at91sam9rl.h> | |
19 | #include <mach/at91_pmc.h> | |
20 | #include <mach/at91_rstc.h> | |
21 | #include <mach/at91_shdwc.h> | |
877d7720 AV |
22 | |
23 | #include "generic.h" | |
24 | #include "clock.h" | |
25 | ||
26 | static struct map_desc at91sam9rl_io_desc[] __initdata = { | |
27 | { | |
28 | .virtual = AT91_VA_BASE_SYS, | |
29 | .pfn = __phys_to_pfn(AT91_BASE_SYS), | |
30 | .length = SZ_16K, | |
31 | .type = MT_DEVICE, | |
32 | }, | |
33 | }; | |
34 | ||
35 | static struct map_desc at91sam9rl_sram_desc[] __initdata = { | |
36 | { | |
37 | .pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE), | |
38 | .type = MT_DEVICE, | |
39 | } | |
40 | }; | |
41 | ||
42 | /* -------------------------------------------------------------------- | |
43 | * Clocks | |
44 | * -------------------------------------------------------------------- */ | |
45 | ||
46 | /* | |
47 | * The peripheral clocks. | |
48 | */ | |
49 | static struct clk pioA_clk = { | |
50 | .name = "pioA_clk", | |
51 | .pmc_mask = 1 << AT91SAM9RL_ID_PIOA, | |
52 | .type = CLK_TYPE_PERIPHERAL, | |
53 | }; | |
54 | static struct clk pioB_clk = { | |
55 | .name = "pioB_clk", | |
56 | .pmc_mask = 1 << AT91SAM9RL_ID_PIOB, | |
57 | .type = CLK_TYPE_PERIPHERAL, | |
58 | }; | |
59 | static struct clk pioC_clk = { | |
60 | .name = "pioC_clk", | |
61 | .pmc_mask = 1 << AT91SAM9RL_ID_PIOC, | |
62 | .type = CLK_TYPE_PERIPHERAL, | |
63 | }; | |
64 | static struct clk pioD_clk = { | |
65 | .name = "pioD_clk", | |
66 | .pmc_mask = 1 << AT91SAM9RL_ID_PIOD, | |
67 | .type = CLK_TYPE_PERIPHERAL, | |
68 | }; | |
69 | static struct clk usart0_clk = { | |
70 | .name = "usart0_clk", | |
71 | .pmc_mask = 1 << AT91SAM9RL_ID_US0, | |
72 | .type = CLK_TYPE_PERIPHERAL, | |
73 | }; | |
74 | static struct clk usart1_clk = { | |
75 | .name = "usart1_clk", | |
76 | .pmc_mask = 1 << AT91SAM9RL_ID_US1, | |
77 | .type = CLK_TYPE_PERIPHERAL, | |
78 | }; | |
79 | static struct clk usart2_clk = { | |
80 | .name = "usart2_clk", | |
81 | .pmc_mask = 1 << AT91SAM9RL_ID_US2, | |
82 | .type = CLK_TYPE_PERIPHERAL, | |
83 | }; | |
84 | static struct clk usart3_clk = { | |
85 | .name = "usart3_clk", | |
86 | .pmc_mask = 1 << AT91SAM9RL_ID_US3, | |
87 | .type = CLK_TYPE_PERIPHERAL, | |
88 | }; | |
89 | static struct clk mmc_clk = { | |
90 | .name = "mci_clk", | |
91 | .pmc_mask = 1 << AT91SAM9RL_ID_MCI, | |
92 | .type = CLK_TYPE_PERIPHERAL, | |
93 | }; | |
94 | static struct clk twi0_clk = { | |
95 | .name = "twi0_clk", | |
96 | .pmc_mask = 1 << AT91SAM9RL_ID_TWI0, | |
97 | .type = CLK_TYPE_PERIPHERAL, | |
98 | }; | |
99 | static struct clk twi1_clk = { | |
100 | .name = "twi1_clk", | |
101 | .pmc_mask = 1 << AT91SAM9RL_ID_TWI1, | |
102 | .type = CLK_TYPE_PERIPHERAL, | |
103 | }; | |
104 | static struct clk spi_clk = { | |
105 | .name = "spi_clk", | |
106 | .pmc_mask = 1 << AT91SAM9RL_ID_SPI, | |
107 | .type = CLK_TYPE_PERIPHERAL, | |
108 | }; | |
109 | static struct clk ssc0_clk = { | |
110 | .name = "ssc0_clk", | |
111 | .pmc_mask = 1 << AT91SAM9RL_ID_SSC0, | |
112 | .type = CLK_TYPE_PERIPHERAL, | |
113 | }; | |
114 | static struct clk ssc1_clk = { | |
115 | .name = "ssc1_clk", | |
116 | .pmc_mask = 1 << AT91SAM9RL_ID_SSC1, | |
117 | .type = CLK_TYPE_PERIPHERAL, | |
118 | }; | |
119 | static struct clk tc0_clk = { | |
120 | .name = "tc0_clk", | |
121 | .pmc_mask = 1 << AT91SAM9RL_ID_TC0, | |
122 | .type = CLK_TYPE_PERIPHERAL, | |
123 | }; | |
124 | static struct clk tc1_clk = { | |
125 | .name = "tc1_clk", | |
126 | .pmc_mask = 1 << AT91SAM9RL_ID_TC1, | |
127 | .type = CLK_TYPE_PERIPHERAL, | |
128 | }; | |
129 | static struct clk tc2_clk = { | |
130 | .name = "tc2_clk", | |
131 | .pmc_mask = 1 << AT91SAM9RL_ID_TC2, | |
132 | .type = CLK_TYPE_PERIPHERAL, | |
133 | }; | |
134 | static struct clk pwmc_clk = { | |
135 | .name = "pwmc_clk", | |
136 | .pmc_mask = 1 << AT91SAM9RL_ID_PWMC, | |
137 | .type = CLK_TYPE_PERIPHERAL, | |
138 | }; | |
139 | static struct clk tsc_clk = { | |
140 | .name = "tsc_clk", | |
141 | .pmc_mask = 1 << AT91SAM9RL_ID_TSC, | |
142 | .type = CLK_TYPE_PERIPHERAL, | |
143 | }; | |
144 | static struct clk dma_clk = { | |
145 | .name = "dma_clk", | |
146 | .pmc_mask = 1 << AT91SAM9RL_ID_DMA, | |
147 | .type = CLK_TYPE_PERIPHERAL, | |
148 | }; | |
149 | static struct clk udphs_clk = { | |
150 | .name = "udphs_clk", | |
151 | .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS, | |
152 | .type = CLK_TYPE_PERIPHERAL, | |
153 | }; | |
154 | static struct clk lcdc_clk = { | |
155 | .name = "lcdc_clk", | |
156 | .pmc_mask = 1 << AT91SAM9RL_ID_LCDC, | |
157 | .type = CLK_TYPE_PERIPHERAL, | |
158 | }; | |
159 | static struct clk ac97_clk = { | |
160 | .name = "ac97_clk", | |
161 | .pmc_mask = 1 << AT91SAM9RL_ID_AC97C, | |
162 | .type = CLK_TYPE_PERIPHERAL, | |
163 | }; | |
164 | ||
165 | static struct clk *periph_clocks[] __initdata = { | |
166 | &pioA_clk, | |
167 | &pioB_clk, | |
168 | &pioC_clk, | |
169 | &pioD_clk, | |
170 | &usart0_clk, | |
171 | &usart1_clk, | |
172 | &usart2_clk, | |
173 | &usart3_clk, | |
174 | &mmc_clk, | |
175 | &twi0_clk, | |
176 | &twi1_clk, | |
177 | &spi_clk, | |
178 | &ssc0_clk, | |
179 | &ssc1_clk, | |
180 | &tc0_clk, | |
181 | &tc1_clk, | |
182 | &tc2_clk, | |
183 | &pwmc_clk, | |
184 | &tsc_clk, | |
185 | &dma_clk, | |
186 | &udphs_clk, | |
187 | &lcdc_clk, | |
188 | &ac97_clk, | |
189 | // irq0 | |
190 | }; | |
191 | ||
192 | /* | |
193 | * The two programmable clocks. | |
194 | * You must configure pin multiplexing to bring these signals out. | |
195 | */ | |
196 | static struct clk pck0 = { | |
197 | .name = "pck0", | |
198 | .pmc_mask = AT91_PMC_PCK0, | |
199 | .type = CLK_TYPE_PROGRAMMABLE, | |
200 | .id = 0, | |
201 | }; | |
202 | static struct clk pck1 = { | |
203 | .name = "pck1", | |
204 | .pmc_mask = AT91_PMC_PCK1, | |
205 | .type = CLK_TYPE_PROGRAMMABLE, | |
206 | .id = 1, | |
207 | }; | |
208 | ||
209 | static void __init at91sam9rl_register_clocks(void) | |
210 | { | |
211 | int i; | |
212 | ||
213 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) | |
214 | clk_register(periph_clocks[i]); | |
215 | ||
216 | clk_register(&pck0); | |
217 | clk_register(&pck1); | |
218 | } | |
219 | ||
220 | /* -------------------------------------------------------------------- | |
221 | * GPIO | |
222 | * -------------------------------------------------------------------- */ | |
223 | ||
224 | static struct at91_gpio_bank at91sam9rl_gpio[] = { | |
225 | { | |
226 | .id = AT91SAM9RL_ID_PIOA, | |
227 | .offset = AT91_PIOA, | |
228 | .clock = &pioA_clk, | |
229 | }, { | |
230 | .id = AT91SAM9RL_ID_PIOB, | |
231 | .offset = AT91_PIOB, | |
232 | .clock = &pioB_clk, | |
233 | }, { | |
234 | .id = AT91SAM9RL_ID_PIOC, | |
235 | .offset = AT91_PIOC, | |
236 | .clock = &pioC_clk, | |
237 | }, { | |
238 | .id = AT91SAM9RL_ID_PIOD, | |
239 | .offset = AT91_PIOD, | |
240 | .clock = &pioD_clk, | |
241 | } | |
242 | }; | |
243 | ||
244 | static void at91sam9rl_reset(void) | |
245 | { | |
246 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); | |
247 | } | |
248 | ||
3ef2fb42 AV |
249 | static void at91sam9rl_poweroff(void) |
250 | { | |
251 | at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); | |
252 | } | |
253 | ||
877d7720 AV |
254 | |
255 | /* -------------------------------------------------------------------- | |
256 | * AT91SAM9RL processor initialization | |
257 | * -------------------------------------------------------------------- */ | |
258 | ||
259 | void __init at91sam9rl_initialize(unsigned long main_clock) | |
260 | { | |
261 | unsigned long cidr, sram_size; | |
262 | ||
263 | /* Map peripherals */ | |
264 | iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc)); | |
265 | ||
266 | cidr = at91_sys_read(AT91_DBGU_CIDR); | |
267 | ||
268 | switch (cidr & AT91_CIDR_SRAMSIZ) { | |
269 | case AT91_CIDR_SRAMSIZ_32K: | |
270 | sram_size = 2 * SZ_16K; | |
271 | break; | |
272 | case AT91_CIDR_SRAMSIZ_16K: | |
273 | default: | |
274 | sram_size = SZ_16K; | |
275 | } | |
276 | ||
277 | at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size; | |
278 | at91sam9rl_sram_desc->length = sram_size; | |
279 | ||
280 | /* Map SRAM */ | |
281 | iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc)); | |
282 | ||
283 | at91_arch_reset = at91sam9rl_reset; | |
3ef2fb42 | 284 | pm_power_off = at91sam9rl_poweroff; |
877d7720 AV |
285 | at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); |
286 | ||
287 | /* Init clock subsystem */ | |
288 | at91_clock_init(main_clock); | |
289 | ||
290 | /* Register the processor-specific clocks */ | |
291 | at91sam9rl_register_clocks(); | |
292 | ||
293 | /* Register GPIO subsystem */ | |
294 | at91_gpio_init(at91sam9rl_gpio, 4); | |
295 | } | |
296 | ||
297 | /* -------------------------------------------------------------------- | |
298 | * Interrupt initialization | |
299 | * -------------------------------------------------------------------- */ | |
300 | ||
301 | /* | |
302 | * The default interrupt priority levels (0 = lowest, 7 = highest). | |
303 | */ | |
304 | static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { | |
305 | 7, /* Advanced Interrupt Controller */ | |
306 | 7, /* System Peripherals */ | |
307 | 1, /* Parallel IO Controller A */ | |
308 | 1, /* Parallel IO Controller B */ | |
309 | 1, /* Parallel IO Controller C */ | |
310 | 1, /* Parallel IO Controller D */ | |
311 | 5, /* USART 0 */ | |
312 | 5, /* USART 1 */ | |
313 | 5, /* USART 2 */ | |
314 | 5, /* USART 3 */ | |
315 | 0, /* Multimedia Card Interface */ | |
316 | 6, /* Two-Wire Interface 0 */ | |
317 | 6, /* Two-Wire Interface 1 */ | |
318 | 5, /* Serial Peripheral Interface */ | |
319 | 4, /* Serial Synchronous Controller 0 */ | |
320 | 4, /* Serial Synchronous Controller 1 */ | |
321 | 0, /* Timer Counter 0 */ | |
322 | 0, /* Timer Counter 1 */ | |
323 | 0, /* Timer Counter 2 */ | |
324 | 0, | |
325 | 0, /* Touch Screen Controller */ | |
326 | 0, /* DMA Controller */ | |
327 | 2, /* USB Device High speed port */ | |
328 | 2, /* LCD Controller */ | |
329 | 6, /* AC97 Controller */ | |
330 | 0, | |
331 | 0, | |
332 | 0, | |
333 | 0, | |
334 | 0, | |
335 | 0, | |
336 | 0, /* Advanced Interrupt Controller */ | |
337 | }; | |
338 | ||
339 | void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS]) | |
340 | { | |
341 | if (!priority) | |
342 | priority = at91sam9rl_default_irq_priority; | |
343 | ||
344 | /* Initialize the AIC interrupt controller */ | |
345 | at91_aic_init(priority); | |
346 | ||
347 | /* Enable GPIO interrupts */ | |
348 | at91_gpio_irq_setup(); | |
349 | } |