[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / kernel / head.S

/*
 *  linux/arch/arm/kernel/head.S
 *
 *  Copyright (C) 1994-2002 Russell King
 *  Copyright (c) 2003 ARM Limited
 *  All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  Kernel startup code for all 32-bit CPUs
 */
#include <linux/linkage.h>
#include <linux/init.h>

#include <asm/assembler.h>
#include <asm/domain.h>
#include <asm/procinfo.h>
#include <asm/ptrace.h>
#include <asm/asm-offsets.h>
#include <asm/memory.h>
#include <asm/thread_info.h>
#include <asm/system.h>

#define KERNEL_RAM_ADDR	(PAGE_OFFSET + TEXT_OFFSET)

/*
 * swapper_pg_dir is the virtual address of the initial page table.
 * We place the page tables 16K below KERNEL_RAM_ADDR.  Therefore, we must
 * make sure that KERNEL_RAM_ADDR is correctly set.  Currently, we expect
 * the least significant 16 bits to be 0x8000, but we could probably
 * relax this restriction to KERNEL_RAM_ADDR >= PAGE_OFFSET + 0x4000.
 */
#if (KERNEL_RAM_ADDR & 0xffff) != 0x8000
#error KERNEL_RAM_ADDR must start at 0xXXXX8000
#endif

	.globl	swapper_pg_dir
	.equ	swapper_pg_dir, KERNEL_RAM_ADDR - 0x4000

	.macro	pgtbl, rd
	ldr	\rd, =(__virt_to_phys(KERNEL_RAM_ADDR - 0x4000))
	.endm

#ifdef CONFIG_XIP_KERNEL
#define TEXTADDR  XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
#else
#define TEXTADDR  KERNEL_RAM_ADDR
#endif

/*
 * Kernel startup entry point.
 * ---------------------------
 *
 * This is normally called from the decompressor code.  The requirements
 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
 * r1 = machine nr.
 *
 * This code is mostly position independent, so if you link the kernel at
 * 0xc0008000, you call this at __pa(0xc0008000).
 *
 * See linux/arch/arm/tools/mach-types for the complete list of machine
 * numbers for r1.
 *
 * We're trying to keep crap to a minimum; DO NOT add any machine specific
 * crap here - that's what the boot loader (or in extreme, well justified
 * circumstances, zImage) is for.
 */
	__INIT
	.type	stext, %function
ENTRY(stext)
	msr	cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
						@ and irqs disabled
	mrc	p15, 0, r9, c0, c0		@ get processor id
	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
	movs	r10, r5				@ invalid processor (r5=0)?
	beq	__error_p			@ yes, error 'p'
	bl	__lookup_machine_type		@ r5=machinfo
	movs	r8, r5				@ invalid machine (r5=0)?
	beq	__error_a			@ yes, error 'a'
	bl	__create_page_tables

	/*
	 * The following calls CPU specific code in a position independent
	 * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of
	 * xxx_proc_info structure selected by __lookup_machine_type
	 * above.  On return, the CPU will be ready for the MMU to be
	 * turned on, and r0 will hold the CPU control register value.
	 */
	ldr	r13, __switch_data		@ address to jump to after
						@ mmu has been enabled
	adr	lr, __enable_mmu		@ return (PIC) address
	add	pc, r10, #PROCINFO_INITFUNC

#if defined(CONFIG_SMP)
	.type   secondary_startup, #function
ENTRY(secondary_startup)
	/*
	 * Common entry point for secondary CPUs.
	 *
	 * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
	 * the processor type - there is no need to check the machine type
	 * as it has already been validated by the primary processor.
	 */
	msr	cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
	mrc	p15, 0, r9, c0, c0		@ get processor id
	bl	__lookup_processor_type
	movs	r10, r5				@ invalid processor?
	moveq	r0, #'p'			@ yes, error 'p'
	beq	__error

	/*
	 * Use the page tables supplied from  __cpu_up.
	 */
	adr	r4, __secondary_data
	ldmia	r4, {r5, r7, r13}		@ address to jump to after
	sub	r4, r4, r5			@ mmu has been enabled
	ldr	r4, [r7, r4]			@ get secondary_data.pgdir
	adr	lr, __enable_mmu		@ return address
	add	pc, r10, #PROCINFO_INITFUNC	@ initialise processor
						@ (return control reg)

	/*
	 * r6  = &secondary_data
	 */
ENTRY(__secondary_switched)
	ldr	sp, [r7, #4]			@ get secondary_data.stack
	mov	fp, #0
	b	secondary_start_kernel

	.type	__secondary_data, %object
__secondary_data:
	.long	.
	.long	secondary_data
	.long	__secondary_switched
#endif /* defined(CONFIG_SMP) */


/*
 * Setup common bits before finally enabling the MMU.  Essentially
 * this is just loading the page table pointer and domain access
 * registers.
 */
	.type	__enable_mmu, %function
__enable_mmu:
#ifdef CONFIG_ALIGNMENT_TRAP
	orr	r0, r0, #CR_A
#else
	bic	r0, r0, #CR_A
#endif
#ifdef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CR_C
#endif
#ifdef CONFIG_CPU_BPREDICT_DISABLE
	bic	r0, r0, #CR_Z
#endif
#ifdef CONFIG_CPU_ICACHE_DISABLE
	bic	r0, r0, #CR_I
#endif
	mov	r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
		      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
		      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
		      domain_val(DOMAIN_IO, DOMAIN_CLIENT))
	mcr	p15, 0, r5, c3, c0, 0		@ load domain access register
	mcr	p15, 0, r4, c2, c0, 0		@ load page table pointer
	b	__turn_mmu_on

/*
 * Enable the MMU.  This completely changes the structure of the visible
 * memory space.  You will not be able to trace execution through this.
 * If you have an enquiry about this, *please* check the linux-arm-kernel
 * mailing list archives BEFORE sending another post to the list.
 *
 *  r0  = cp#15 control register
 *  r13 = *virtual* address to jump to upon completion
 *
 * other registers depend on the function called upon completion
 */
	.align	5
	.type	__turn_mmu_on, %function
__turn_mmu_on:
	mov	r0, r0
	mcr	p15, 0, r0, c1, c0, 0		@ write control reg
	mrc	p15, 0, r3, c0, c0, 0		@ read id reg
	mov	r3, r3
	mov	r3, r3
	mov	pc, r13


/*
 * Setup the initial page tables.  We only setup the barest
 * amount which are required to get the kernel running, which
 * generally means mapping in the kernel code.
 *
 * r8  = machinfo
 * r9  = cpuid
 * r10 = procinfo
 *
 * Returns:
 *  r0, r3, r6, r7 corrupted
 *  r4 = physical page table address
 */
	.type	__create_page_tables, %function
__create_page_tables:
	pgtbl	r4				@ page table address

	/*
	 * Clear the 16K level 1 swapper page table
	 */
	mov	r0, r4
	mov	r3, #0
	add	r6, r0, #0x4000
1:	str	r3, [r0], #4
	str	r3, [r0], #4
	str	r3, [r0], #4
	str	r3, [r0], #4
	teq	r0, r6
	bne	1b

	ldr	r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags

	/*
	 * Create identity mapping for first MB of kernel to
	 * cater for the MMU enable.  This identity mapping
	 * will be removed by paging_init().  We use our current program
	 * counter to determine corresponding section base address.
	 */
	mov	r6, pc, lsr #20			@ start of kernel section
	orr	r3, r7, r6, lsl #20		@ flags + kernel base
	str	r3, [r4, r6, lsl #2]		@ identity mapping

	/*
	 * Now setup the pagetables for our kernel direct
	 * mapped region.  We round TEXTADDR down to the
	 * nearest megabyte boundary.  It is assumed that
	 * the kernel fits within 4 contigous 1MB sections.
	 */
	add	r0, r4,  #(TEXTADDR & 0xff000000) >> 18	@ start of kernel
	str	r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!
	add	r3, r3, #1 << 20
	str	r3, [r0, #4]!			@ KERNEL + 1MB
	add	r3, r3, #1 << 20
	str	r3, [r0, #4]!			@ KERNEL + 2MB
	add	r3, r3, #1 << 20
	str	r3, [r0, #4]			@ KERNEL + 3MB

	/*
	 * Then map first 1MB of ram in case it contains our boot params.
	 */
	add	r0, r4, #PAGE_OFFSET >> 18
	orr	r6, r7, #PHYS_OFFSET
	str	r6, [r0]

#ifdef CONFIG_XIP_KERNEL
	/*
	 * Map some ram to cover our .data and .bss areas.
	 * Mapping 3MB should be plenty.
	 */
	sub	r3, r4, #PHYS_OFFSET
	mov	r3, r3, lsr #20
	add	r0, r0, r3, lsl #2
	add	r6, r6, r3, lsl #20
	str	r6, [r0], #4
	add	r6, r6, #(1 << 20)
	str	r6, [r0], #4
	add	r6, r6, #(1 << 20)
	str	r6, [r0]
#endif

#ifdef CONFIG_DEBUG_LL
	ldr	r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
	/*
	 * Map in IO space for serial debugging.
	 * This allows debug messages to be output
	 * via a serial console before paging_init.
	 */
	ldr	r3, [r8, #MACHINFO_PGOFFIO]
	add	r0, r4, r3
	rsb	r3, r3, #0x4000			@ PTRS_PER_PGD*sizeof(long)
	cmp	r3, #0x0800			@ limit to 512MB
	movhi	r3, #0x0800
	add	r6, r0, r3
	ldr	r3, [r8, #MACHINFO_PHYSIO]
	orr	r3, r3, r7
1:	str	r3, [r0], #4
	add	r3, r3, #1 << 20
	teq	r0, r6
	bne	1b
#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
	/*
	 * If we're using the NetWinder or CATS, we also need to map
	 * in the 16550-type serial port for the debug messages
	 */
	add	r0, r4, #0xff000000 >> 18
	orr	r3, r7, #0x7c000000
	str	r3, [r0]
#endif
#ifdef CONFIG_ARCH_RPC
	/*
	 * Map in screen at 0x02000000 & SCREEN2_BASE
	 * Similar reasons here - for debug.  This is
	 * only for Acorn RiscPC architectures.
	 */
	add	r0, r4, #0x02000000 >> 18
	orr	r3, r7, #0x02000000
	str	r3, [r0]
	add	r0, r4, #0xd8000000 >> 18
	str	r3, [r0]
#endif
#endif
	mov	pc, lr
	.ltorg

#include "head-common.S"
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/kernel/head.S
	3	*
	4	* Copyright (C) 1994-2002 Russell King
e65f38ed RK	5	* Copyright (c) 2003 ARM Limited
e65f38ed RK	6	* All Rights Reserved
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* Kernel startup code for all 32-bit CPUs
	13	*/
1da177e4 LT	14	#include <linux/linkage.h>
	15	#include <linux/init.h>
	16
	17	#include <asm/assembler.h>
	18	#include <asm/domain.h>
1da177e4 LT	19	#include <asm/procinfo.h>
1da177e4 LT	20	#include <asm/ptrace.h>
e6ae744d	21	#include <asm/asm-offsets.h>
f09b9979	22	#include <asm/memory.h>
4f7a1812	23	#include <asm/thread_info.h>
1da177e4 LT	24	#include <asm/system.h>
1da177e4 LT	25
9d4f13e5 RK	26	#define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET)
9d4f13e5 RK	27
1da177e4	28	/*
37d07b72 NP	29	* swapper_pg_dir is the virtual address of the initial page table.
	30	* We place the page tables 16K below KERNEL_RAM_ADDR. Therefore, we must
	31	* make sure that KERNEL_RAM_ADDR is correctly set. Currently, we expect
	32	* the least significant 16 bits to be 0x8000, but we could probably
	33	* relax this restriction to KERNEL_RAM_ADDR >= PAGE_OFFSET + 0x4000.
1da177e4	34	*/
37d07b72 NP	35	#if (KERNEL_RAM_ADDR & 0xffff) != 0x8000
37d07b72 NP	36	#error KERNEL_RAM_ADDR must start at 0xXXXX8000
1da177e4 LT	37	#endif
	38
	39	.globl swapper_pg_dir
37d07b72	40	.equ swapper_pg_dir, KERNEL_RAM_ADDR - 0x4000
1da177e4	41
37d07b72 NP	42	.macro pgtbl, rd
37d07b72 NP	43	ldr \rd, =(__virt_to_phys(KERNEL_RAM_ADDR - 0x4000))
1da177e4	44	.endm
1da177e4	45
37d07b72 NP	46	#ifdef CONFIG_XIP_KERNEL
	47	#define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
	48	#else
	49	#define TEXTADDR KERNEL_RAM_ADDR
1da177e4 LT	50	#endif
	51
	52	/*
	53	* Kernel startup entry point.
	54	* ---------------------------
	55	*
	56	* This is normally called from the decompressor code. The requirements
	57	* are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
	58	* r1 = machine nr.
	59	*
	60	* This code is mostly position independent, so if you link the kernel at
	61	* 0xc0008000, you call this at __pa(0xc0008000).
	62	*
	63	* See linux/arch/arm/tools/mach-types for the complete list of machine
	64	* numbers for r1.
	65	*
	66	* We're trying to keep crap to a minimum; DO NOT add any machine specific
	67	* crap here - that's what the boot loader (or in extreme, well justified
	68	* circumstances, zImage) is for.
	69	*/
	70	__INIT
	71	.type stext, %function
	72	ENTRY(stext)
801194e3	73	msr cpsr_c, #PSR_F_BIT \| PSR_I_BIT \| SVC_MODE @ ensure svc mode
1da177e4	74	@ and irqs disabled
0f44ba1d	75	mrc p15, 0, r9, c0, c0 @ get processor id
1da177e4 LT	76	bl __lookup_processor_type @ r5=procinfo r9=cpuid
1da177e4 LT	77	movs r10, r5 @ invalid processor (r5=0)?
3c0bdac3	78	beq __error_p @ yes, error 'p'
1da177e4 LT	79	bl __lookup_machine_type @ r5=machinfo
	80	movs r8, r5 @ invalid machine (r5=0)?
	81	beq __error_a @ yes, error 'a'
	82	bl __create_page_tables
	83
	84	/*
	85	* The following calls CPU specific code in a position independent
	86	* manner. See arch/arm/mm/proc-*.S for details. r10 = base of
	87	* xxx_proc_info structure selected by __lookup_machine_type
	88	* above. On return, the CPU will be ready for the MMU to be
	89	* turned on, and r0 will hold the CPU control register value.
	90	*/
	91	ldr r13, __switch_data @ address to jump to after
	92	@ mmu has been enabled
	93	adr lr, __enable_mmu @ return (PIC) address
	94	add pc, r10, #PROCINFO_INITFUNC
	95
e65f38ed RK	96	#if defined(CONFIG_SMP)
	97	.type secondary_startup, #function
	98	ENTRY(secondary_startup)
	99	/*
	100	* Common entry point for secondary CPUs.
	101	*
	102	* Ensure that we're in SVC mode, and IRQs are disabled. Lookup
	103	* the processor type - there is no need to check the machine type
	104	* as it has already been validated by the primary processor.
	105	*/
801194e3	106	msr cpsr_c, #PSR_F_BIT \| PSR_I_BIT \| SVC_MODE
0f44ba1d	107	mrc p15, 0, r9, c0, c0 @ get processor id
e65f38ed RK	108	bl __lookup_processor_type
	109	movs r10, r5 @ invalid processor?
	110	moveq r0, #'p' @ yes, error 'p'
	111	beq __error
	112
	113	/*
	114	* Use the page tables supplied from __cpu_up.
	115	*/
	116	adr r4, __secondary_data
34d92626	117	ldmia r4, {r5, r7, r13} @ address to jump to after
e65f38ed	118	sub r4, r4, r5 @ mmu has been enabled
34d92626	119	ldr r4, [r7, r4] @ get secondary_data.pgdir
e65f38ed	120	adr lr, __enable_mmu @ return address
90af774a	121	add pc, r10, #PROCINFO_INITFUNC @ initialise processor
e65f38ed RK	122	@ (return control reg)
	123
	124	/*
	125	* r6 = &secondary_data
	126	*/
	127	ENTRY(__secondary_switched)
34d92626	128	ldr sp, [r7, #4] @ get secondary_data.stack
e65f38ed RK	129	mov fp, #0
	130	b secondary_start_kernel
	131
	132	.type __secondary_data, %object
	133	__secondary_data:
	134	.long .
	135	.long secondary_data
	136	.long __secondary_switched
	137	#endif /* defined(CONFIG_SMP) */
	138
1da177e4 LT	139
	140
	141	/*
	142	* Setup common bits before finally enabling the MMU. Essentially
	143	* this is just loading the page table pointer and domain access
	144	* registers.
	145	*/
	146	.type __enable_mmu, %function
	147	__enable_mmu:
	148	#ifdef CONFIG_ALIGNMENT_TRAP
	149	orr r0, r0, #CR_A
	150	#else
	151	bic r0, r0, #CR_A
	152	#endif
	153	#ifdef CONFIG_CPU_DCACHE_DISABLE
	154	bic r0, r0, #CR_C
	155	#endif
	156	#ifdef CONFIG_CPU_BPREDICT_DISABLE
	157	bic r0, r0, #CR_Z
	158	#endif
	159	#ifdef CONFIG_CPU_ICACHE_DISABLE
	160	bic r0, r0, #CR_I
	161	#endif
	162	mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) \| \
	163	domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) \| \
	164	domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) \| \
	165	domain_val(DOMAIN_IO, DOMAIN_CLIENT))
	166	mcr p15, 0, r5, c3, c0, 0 @ load domain access register
	167	mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
	168	b __turn_mmu_on
	169
	170	/*
	171	* Enable the MMU. This completely changes the structure of the visible
	172	* memory space. You will not be able to trace execution through this.
	173	* If you have an enquiry about this, please check the linux-arm-kernel
	174	* mailing list archives BEFORE sending another post to the list.
	175	*
	176	* r0 = cp#15 control register
	177	* r13 = virtual address to jump to upon completion
	178	*
	179	* other registers depend on the function called upon completion
	180	*/
	181	.align 5
	182	.type __turn_mmu_on, %function
	183	__turn_mmu_on:
	184	mov r0, r0
	185	mcr p15, 0, r0, c1, c0, 0 @ write control reg
	186	mrc p15, 0, r3, c0, c0, 0 @ read id reg
	187	mov r3, r3
	188	mov r3, r3
	189	mov pc, r13
	190
	191
	192
	193	/*
	194	* Setup the initial page tables. We only setup the barest
	195	* amount which are required to get the kernel running, which
	196	* generally means mapping in the kernel code.
	197	*
	198	* r8 = machinfo
	199	* r9 = cpuid
	200	* r10 = procinfo
	201	*
	202	* Returns:
2df96b34	203	* r0, r3, r6, r7 corrupted
1da177e4 LT	204	* r4 = physical page table address
	205	*/
	206	.type __create_page_tables, %function
	207	__create_page_tables:
37d07b72	208	pgtbl r4 @ page table address
1da177e4 LT	209
	210	/*
	211	* Clear the 16K level 1 swapper page table
	212	*/
	213	mov r0, r4
	214	mov r3, #0
	215	add r6, r0, #0x4000
	216	1: str r3, [r0], #4
	217	str r3, [r0], #4
	218	str r3, [r0], #4
	219	str r3, [r0], #4
	220	teq r0, r6
	221	bne 1b
	222
8799ee9f	223	ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
1da177e4 LT	224
	225	/*
	226	* Create identity mapping for first MB of kernel to
	227	* cater for the MMU enable. This identity mapping
	228	* will be removed by paging_init(). We use our current program
	229	* counter to determine corresponding section base address.
	230	*/
	231	mov r6, pc, lsr #20 @ start of kernel section
	232	orr r3, r7, r6, lsl #20 @ flags + kernel base
	233	str r3, [r4, r6, lsl #2] @ identity mapping
	234
	235	/*
	236	* Now setup the pagetables for our kernel direct
	237	* mapped region. We round TEXTADDR down to the
	238	* nearest megabyte boundary. It is assumed that
	239	* the kernel fits within 4 contigous 1MB sections.
	240	*/
	241	add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel
	242	str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!
	243	add r3, r3, #1 << 20
	244	str r3, [r0, #4]! @ KERNEL + 1MB
	245	add r3, r3, #1 << 20
	246	str r3, [r0, #4]! @ KERNEL + 2MB
	247	add r3, r3, #1 << 20
	248	str r3, [r0, #4] @ KERNEL + 3MB
	249
	250	/*
	251	* Then map first 1MB of ram in case it contains our boot params.
	252	*/
f09b9979	253	add r0, r4, #PAGE_OFFSET >> 18
2df96b34	254	orr r6, r7, #PHYS_OFFSET
1da177e4 LT	255	str r6, [r0]
	256
	257	#ifdef CONFIG_XIP_KERNEL
	258	/*
	259	* Map some ram to cover our .data and .bss areas.
	260	* Mapping 3MB should be plenty.
	261	*/
2df96b34	262	sub r3, r4, #PHYS_OFFSET
1da177e4 LT	263	mov r3, r3, lsr #20
	264	add r0, r0, r3, lsl #2
	265	add r6, r6, r3, lsl #20
	266	str r6, [r0], #4
	267	add r6, r6, #(1 << 20)
	268	str r6, [r0], #4
	269	add r6, r6, #(1 << 20)
	270	str r6, [r0]
	271	#endif
	272
c77b0427	273	#ifdef CONFIG_DEBUG_LL
8799ee9f	274	ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
1da177e4 LT	275	/*
	276	* Map in IO space for serial debugging.
	277	* This allows debug messages to be output
	278	* via a serial console before paging_init.
	279	*/
	280	ldr r3, [r8, #MACHINFO_PGOFFIO]
	281	add r0, r4, r3
	282	rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
	283	cmp r3, #0x0800 @ limit to 512MB
	284	movhi r3, #0x0800
	285	add r6, r0, r3
	286	ldr r3, [r8, #MACHINFO_PHYSIO]
	287	orr r3, r3, r7
	288	1: str r3, [r0], #4
	289	add r3, r3, #1 << 20
	290	teq r0, r6
	291	bne 1b
	292	#if defined(CONFIG_ARCH_NETWINDER) \|\| defined(CONFIG_ARCH_CATS)
	293	/*
3c0bdac3 RK	294	* If we're using the NetWinder or CATS, we also need to map
3c0bdac3 RK	295	* in the 16550-type serial port for the debug messages
1da177e4	296	*/
c77b0427 RK	297	add r0, r4, #0xff000000 >> 18
	298	orr r3, r7, #0x7c000000
	299	str r3, [r0]
1da177e4	300	#endif
1da177e4 LT	301	#ifdef CONFIG_ARCH_RPC
	302	/*
	303	* Map in screen at 0x02000000 & SCREEN2_BASE
	304	* Similar reasons here - for debug. This is
	305	* only for Acorn RiscPC architectures.
	306	*/
c77b0427 RK	307	add r0, r4, #0x02000000 >> 18
c77b0427 RK	308	orr r3, r7, #0x02000000
1da177e4	309	str r3, [r0]
c77b0427	310	add r0, r4, #0xd8000000 >> 18
1da177e4	311	str r3, [r0]
c77b0427	312	#endif
1da177e4 LT	313	#endif
	314	mov pc, lr
	315	.ltorg
	316
75d90832	317	#include "head-common.S"