Commit | Line | Data |
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9eb8f674 GL |
1 | /* |
2 | * linux/arch/arm/kernel/devtree.c | |
3 | * | |
4 | * Copyright (C) 2009 Canonical Ltd. <jeremy.kerr@canonical.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
ecea4ab6 | 12 | #include <linux/export.h> |
9eb8f674 GL |
13 | #include <linux/errno.h> |
14 | #include <linux/types.h> | |
15 | #include <linux/bootmem.h> | |
16 | #include <linux/memblock.h> | |
17 | #include <linux/of.h> | |
18 | #include <linux/of_fdt.h> | |
19 | #include <linux/of_irq.h> | |
20 | #include <linux/of_platform.h> | |
21 | ||
a0ae0240 | 22 | #include <asm/cputype.h> |
9eb8f674 GL |
23 | #include <asm/setup.h> |
24 | #include <asm/page.h> | |
a0ae0240 | 25 | #include <asm/smp_plat.h> |
93c02ab4 GL |
26 | #include <asm/mach/arch.h> |
27 | #include <asm/mach-types.h> | |
9eb8f674 | 28 | |
6fa3eb70 S |
29 | extern char default_command_line[COMMAND_LINE_SIZE]; |
30 | ||
9eb8f674 GL |
31 | void __init early_init_dt_add_memory_arch(u64 base, u64 size) |
32 | { | |
33 | arm_add_memory(base, size); | |
34 | } | |
35 | ||
36 | void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) | |
37 | { | |
38 | return alloc_bootmem_align(size, align); | |
39 | } | |
40 | ||
93c02ab4 GL |
41 | void __init arm_dt_memblock_reserve(void) |
42 | { | |
43 | u64 *reserve_map, base, size; | |
44 | ||
45 | if (!initial_boot_params) | |
46 | return; | |
47 | ||
48 | /* Reserve the dtb region */ | |
49 | memblock_reserve(virt_to_phys(initial_boot_params), | |
50 | be32_to_cpu(initial_boot_params->totalsize)); | |
51 | ||
52 | /* | |
53 | * Process the reserve map. This will probably overlap the initrd | |
54 | * and dtb locations which are already reserved, but overlaping | |
55 | * doesn't hurt anything | |
56 | */ | |
57 | reserve_map = ((void*)initial_boot_params) + | |
58 | be32_to_cpu(initial_boot_params->off_mem_rsvmap); | |
59 | while (1) { | |
60 | base = be64_to_cpup(reserve_map++); | |
61 | size = be64_to_cpup(reserve_map++); | |
62 | if (!size) | |
63 | break; | |
64 | memblock_reserve(base, size); | |
65 | } | |
66 | } | |
67 | ||
a0ae0240 LP |
68 | /* |
69 | * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree | |
70 | * and builds the cpu logical map array containing MPIDR values related to | |
71 | * logical cpus | |
72 | * | |
73 | * Updates the cpu possible mask with the number of parsed cpu nodes | |
74 | */ | |
75 | void __init arm_dt_init_cpu_maps(void) | |
76 | { | |
77 | /* | |
78 | * Temp logical map is initialized with UINT_MAX values that are | |
79 | * considered invalid logical map entries since the logical map must | |
80 | * contain a list of MPIDR[23:0] values where MPIDR[31:24] must | |
81 | * read as 0. | |
82 | */ | |
83 | struct device_node *cpu, *cpus; | |
84 | u32 i, j, cpuidx = 1; | |
85 | u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; | |
86 | ||
18d7f152 | 87 | u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID }; |
a0ae0240 LP |
88 | bool bootcpu_valid = false; |
89 | cpus = of_find_node_by_path("/cpus"); | |
90 | ||
91 | if (!cpus) | |
92 | return; | |
93 | ||
94 | for_each_child_of_node(cpus, cpu) { | |
95 | u32 hwid; | |
96 | ||
1ba9bf0a LP |
97 | if (of_node_cmp(cpu->type, "cpu")) |
98 | continue; | |
99 | ||
a0ae0240 LP |
100 | pr_debug(" * %s...\n", cpu->full_name); |
101 | /* | |
102 | * A device tree containing CPU nodes with missing "reg" | |
103 | * properties is considered invalid to build the | |
104 | * cpu_logical_map. | |
105 | */ | |
106 | if (of_property_read_u32(cpu, "reg", &hwid)) { | |
107 | pr_debug(" * %s missing reg property\n", | |
108 | cpu->full_name); | |
109 | return; | |
110 | } | |
111 | ||
112 | /* | |
113 | * 8 MSBs must be set to 0 in the DT since the reg property | |
114 | * defines the MPIDR[23:0]. | |
115 | */ | |
116 | if (hwid & ~MPIDR_HWID_BITMASK) | |
117 | return; | |
118 | ||
119 | /* | |
120 | * Duplicate MPIDRs are a recipe for disaster. | |
121 | * Scan all initialized entries and check for | |
122 | * duplicates. If any is found just bail out. | |
123 | * temp values were initialized to UINT_MAX | |
124 | * to avoid matching valid MPIDR[23:0] values. | |
125 | */ | |
126 | for (j = 0; j < cpuidx; j++) | |
127 | if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg " | |
128 | "properties in the DT\n")) | |
129 | return; | |
130 | ||
131 | /* | |
132 | * Build a stashed array of MPIDR values. Numbering scheme | |
133 | * requires that if detected the boot CPU must be assigned | |
134 | * logical id 0. Other CPUs get sequential indexes starting | |
135 | * from 1. If a CPU node with a reg property matching the | |
136 | * boot CPU MPIDR is detected, this is recorded so that the | |
137 | * logical map built from DT is validated and can be used | |
138 | * to override the map created in smp_setup_processor_id(). | |
139 | */ | |
140 | if (hwid == mpidr) { | |
141 | i = 0; | |
142 | bootcpu_valid = true; | |
143 | } else { | |
144 | i = cpuidx++; | |
145 | } | |
146 | ||
ce7b1756 LP |
147 | if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than " |
148 | "max cores %u, capping them\n", | |
149 | cpuidx, nr_cpu_ids)) { | |
150 | cpuidx = nr_cpu_ids; | |
a0ae0240 | 151 | break; |
ce7b1756 LP |
152 | } |
153 | ||
154 | tmp_map[i] = hwid; | |
a0ae0240 LP |
155 | } |
156 | ||
8d5bc1a6 OJ |
157 | if (!bootcpu_valid) { |
158 | pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n"); | |
a0ae0240 | 159 | return; |
8d5bc1a6 | 160 | } |
a0ae0240 LP |
161 | |
162 | /* | |
163 | * Since the boot CPU node contains proper data, and all nodes have | |
164 | * a reg property, the DT CPU list can be considered valid and the | |
165 | * logical map created in smp_setup_processor_id() can be overridden | |
166 | */ | |
167 | for (i = 0; i < cpuidx; i++) { | |
168 | set_cpu_possible(i, true); | |
169 | cpu_logical_map(i) = tmp_map[i]; | |
170 | pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i)); | |
171 | } | |
172 | } | |
173 | ||
93c02ab4 GL |
174 | /** |
175 | * setup_machine_fdt - Machine setup when an dtb was passed to the kernel | |
176 | * @dt_phys: physical address of dt blob | |
177 | * | |
178 | * If a dtb was passed to the kernel in r2, then use it to choose the | |
179 | * correct machine_desc and to setup the system. | |
180 | */ | |
181 | struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) | |
182 | { | |
183 | struct boot_param_header *devtree; | |
184 | struct machine_desc *mdesc, *mdesc_best = NULL; | |
185 | unsigned int score, mdesc_score = ~1; | |
186 | unsigned long dt_root; | |
187 | const char *model; | |
6fa3eb70 | 188 | char *from = default_command_line; |
93c02ab4 | 189 | |
883a106b AB |
190 | #ifdef CONFIG_ARCH_MULTIPLATFORM |
191 | DT_MACHINE_START(GENERIC_DT, "Generic DT based system") | |
192 | MACHINE_END | |
193 | ||
194 | mdesc_best = (struct machine_desc *)&__mach_desc_GENERIC_DT; | |
195 | #endif | |
196 | ||
f506cd48 NP |
197 | if (!dt_phys) |
198 | return NULL; | |
199 | ||
93c02ab4 GL |
200 | devtree = phys_to_virt(dt_phys); |
201 | ||
202 | /* check device tree validity */ | |
203 | if (be32_to_cpu(devtree->magic) != OF_DT_HEADER) | |
204 | return NULL; | |
205 | ||
206 | /* Search the mdescs for the 'best' compatible value match */ | |
207 | initial_boot_params = devtree; | |
208 | dt_root = of_get_flat_dt_root(); | |
209 | for_each_machine_desc(mdesc) { | |
210 | score = of_flat_dt_match(dt_root, mdesc->dt_compat); | |
211 | if (score > 0 && score < mdesc_score) { | |
212 | mdesc_best = mdesc; | |
213 | mdesc_score = score; | |
214 | } | |
215 | } | |
216 | if (!mdesc_best) { | |
217 | const char *prop; | |
218 | long size; | |
219 | ||
220 | early_print("\nError: unrecognized/unsupported " | |
221 | "device tree compatible list:\n[ "); | |
222 | ||
223 | prop = of_get_flat_dt_prop(dt_root, "compatible", &size); | |
224 | while (size > 0) { | |
225 | early_print("'%s' ", prop); | |
226 | size -= strlen(prop) + 1; | |
227 | prop += strlen(prop) + 1; | |
228 | } | |
229 | early_print("]\n\n"); | |
230 | ||
231 | dump_machine_table(); /* does not return */ | |
232 | } | |
233 | ||
234 | model = of_get_flat_dt_prop(dt_root, "model", NULL); | |
235 | if (!model) | |
236 | model = of_get_flat_dt_prop(dt_root, "compatible", NULL); | |
237 | if (!model) | |
238 | model = "<unknown>"; | |
239 | pr_info("Machine: %s, model: %s\n", mdesc_best->name, model); | |
240 | ||
241 | /* Retrieve various information from the /chosen node */ | |
242 | of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line); | |
243 | /* Initialize {size,address}-cells info */ | |
244 | of_scan_flat_dt(early_init_dt_scan_root, NULL); | |
245 | /* Setup memory, calling early_init_dt_add_memory_arch */ | |
246 | of_scan_flat_dt(early_init_dt_scan_memory, NULL); | |
247 | ||
248 | /* Change machine number to match the mdesc we're using */ | |
249 | __machine_arch_type = mdesc_best->nr; | |
250 | ||
6fa3eb70 S |
251 | if (mdesc_best->fixup) { |
252 | mdesc_best->fixup((void *)dt_root, &from, &meminfo); | |
253 | strlcpy(boot_command_line, from, COMMAND_LINE_SIZE); | |
254 | } | |
255 | ||
93c02ab4 GL |
256 | return mdesc_best; |
257 | } |