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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 1995-2003 Russell King | |
3 | * 2001-2002 Keith Owens | |
4 | * | |
5 | * Generate definitions needed by assembly language modules. | |
6 | * This code generates raw asm output which is post-processed to extract | |
7 | * and format the required data. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/sched.h> | |
14 | #include <linux/mm.h> | |
6fa3eb70 | 15 | #include <linux/suspend.h> |
a9c9147e | 16 | #include <linux/dma-mapping.h> |
f7ed45be CD |
17 | #ifdef CONFIG_KVM_ARM_HOST |
18 | #include <linux/kvm_host.h> | |
19 | #endif | |
f6b0fa02 | 20 | #include <asm/cacheflush.h> |
753790e7 RK |
21 | #include <asm/glue-df.h> |
22 | #include <asm/glue-pf.h> | |
1da177e4 LT |
23 | #include <asm/mach/arch.h> |
24 | #include <asm/thread_info.h> | |
25 | #include <asm/memory.h> | |
ee90dabc | 26 | #include <asm/procinfo.h> |
91c2ebb9 | 27 | #include <asm/hardware/cache-l2x0.h> |
02cbe474 | 28 | #include <linux/kbuild.h> |
1da177e4 LT |
29 | |
30 | /* | |
31 | * Make sure that the compiler and target are compatible. | |
32 | */ | |
33 | #if defined(__APCS_26__) | |
34 | #error Sorry, your compiler targets APCS-26 but this kernel requires APCS-32 | |
35 | #endif | |
36 | /* | |
1da177e4 LT |
37 | * GCC 3.0, 3.1: general bad code generation. |
38 | * GCC 3.2.0: incorrect function argument offset calculation. | |
39 | * GCC 3.2.x: miscompiles NEW_AUX_ENT in fs/binfmt_elf.c | |
40 | * (http://gcc.gnu.org/PR8896) and incorrect structure | |
41 | * initialisation in fs/jffs2/erase.c | |
42 | */ | |
a1365647 | 43 | #if (__GNUC__ == 3 && __GNUC_MINOR__ < 3) |
1da177e4 | 44 | #error Your compiler is too buggy; it is known to miscompile kernels. |
a1365647 | 45 | #error Known good compilers: 3.3 |
1da177e4 LT |
46 | #endif |
47 | ||
1da177e4 LT |
48 | int main(void) |
49 | { | |
50 | DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); | |
df0698be NP |
51 | #ifdef CONFIG_CC_STACKPROTECTOR |
52 | DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary)); | |
53 | #endif | |
1da177e4 LT |
54 | BLANK(); |
55 | DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); | |
56 | DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); | |
57 | DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit)); | |
58 | DEFINE(TI_TASK, offsetof(struct thread_info, task)); | |
59 | DEFINE(TI_EXEC_DOMAIN, offsetof(struct thread_info, exec_domain)); | |
60 | DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); | |
61 | DEFINE(TI_CPU_DOMAIN, offsetof(struct thread_info, cpu_domain)); | |
62 | DEFINE(TI_CPU_SAVE, offsetof(struct thread_info, cpu_context)); | |
63 | DEFINE(TI_USED_CP, offsetof(struct thread_info, used_cp)); | |
64 | DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value)); | |
65 | DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate)); | |
9fc31ddc | 66 | #ifdef CONFIG_VFP |
1da177e4 | 67 | DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate)); |
f8f2a852 RK |
68 | #ifdef CONFIG_SMP |
69 | DEFINE(VFP_CPU, offsetof(union vfp_state, hard.cpu)); | |
70 | #endif | |
9fc31ddc | 71 | #endif |
d7f864be CM |
72 | #ifdef CONFIG_ARM_THUMBEE |
73 | DEFINE(TI_THUMBEE_STATE, offsetof(struct thread_info, thumbee_state)); | |
74 | #endif | |
cdaabbd7 RK |
75 | #ifdef CONFIG_IWMMXT |
76 | DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt)); | |
c17fad11 LB |
77 | #endif |
78 | #ifdef CONFIG_CRUNCH | |
79 | DEFINE(TI_CRUNCH_STATE, offsetof(struct thread_info, crunchstate)); | |
cdaabbd7 | 80 | #endif |
1da177e4 | 81 | BLANK(); |
925c8a1a RK |
82 | DEFINE(S_R0, offsetof(struct pt_regs, ARM_r0)); |
83 | DEFINE(S_R1, offsetof(struct pt_regs, ARM_r1)); | |
84 | DEFINE(S_R2, offsetof(struct pt_regs, ARM_r2)); | |
85 | DEFINE(S_R3, offsetof(struct pt_regs, ARM_r3)); | |
86 | DEFINE(S_R4, offsetof(struct pt_regs, ARM_r4)); | |
87 | DEFINE(S_R5, offsetof(struct pt_regs, ARM_r5)); | |
88 | DEFINE(S_R6, offsetof(struct pt_regs, ARM_r6)); | |
89 | DEFINE(S_R7, offsetof(struct pt_regs, ARM_r7)); | |
90 | DEFINE(S_R8, offsetof(struct pt_regs, ARM_r8)); | |
91 | DEFINE(S_R9, offsetof(struct pt_regs, ARM_r9)); | |
92 | DEFINE(S_R10, offsetof(struct pt_regs, ARM_r10)); | |
93 | DEFINE(S_FP, offsetof(struct pt_regs, ARM_fp)); | |
94 | DEFINE(S_IP, offsetof(struct pt_regs, ARM_ip)); | |
95 | DEFINE(S_SP, offsetof(struct pt_regs, ARM_sp)); | |
96 | DEFINE(S_LR, offsetof(struct pt_regs, ARM_lr)); | |
97 | DEFINE(S_PC, offsetof(struct pt_regs, ARM_pc)); | |
98 | DEFINE(S_PSR, offsetof(struct pt_regs, ARM_cpsr)); | |
99 | DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0)); | |
100 | DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); | |
101 | BLANK(); | |
91c2ebb9 BS |
102 | #ifdef CONFIG_CACHE_L2X0 |
103 | DEFINE(L2X0_R_PHY_BASE, offsetof(struct l2x0_regs, phy_base)); | |
104 | DEFINE(L2X0_R_AUX_CTRL, offsetof(struct l2x0_regs, aux_ctrl)); | |
105 | DEFINE(L2X0_R_TAG_LATENCY, offsetof(struct l2x0_regs, tag_latency)); | |
106 | DEFINE(L2X0_R_DATA_LATENCY, offsetof(struct l2x0_regs, data_latency)); | |
107 | DEFINE(L2X0_R_FILTER_START, offsetof(struct l2x0_regs, filter_start)); | |
108 | DEFINE(L2X0_R_FILTER_END, offsetof(struct l2x0_regs, filter_end)); | |
109 | DEFINE(L2X0_R_PREFETCH_CTRL, offsetof(struct l2x0_regs, prefetch_ctrl)); | |
110 | DEFINE(L2X0_R_PWR_CTRL, offsetof(struct l2x0_regs, pwr_ctrl)); | |
111 | BLANK(); | |
112 | #endif | |
516793c6 | 113 | #ifdef CONFIG_CPU_HAS_ASID |
8a4e3a9e | 114 | DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter)); |
1da177e4 LT |
115 | BLANK(); |
116 | #endif | |
117 | DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm)); | |
118 | DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags)); | |
119 | BLANK(); | |
120 | DEFINE(VM_EXEC, VM_EXEC); | |
121 | BLANK(); | |
122 | DEFINE(PAGE_SZ, PAGE_SIZE); | |
1da177e4 LT |
123 | BLANK(); |
124 | DEFINE(SYS_ERROR0, 0x9f0000); | |
125 | BLANK(); | |
126 | DEFINE(SIZEOF_MACHINE_DESC, sizeof(struct machine_desc)); | |
2eb9d315 UZ |
127 | DEFINE(MACHINFO_TYPE, offsetof(struct machine_desc, nr)); |
128 | DEFINE(MACHINFO_NAME, offsetof(struct machine_desc, name)); | |
2ceec0c8 UZ |
129 | BLANK(); |
130 | DEFINE(PROC_INFO_SZ, sizeof(struct proc_info_list)); | |
2eb9d315 | 131 | DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush)); |
8799ee9f RK |
132 | DEFINE(PROCINFO_MM_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mm_mmu_flags)); |
133 | DEFINE(PROCINFO_IO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_io_mmu_flags)); | |
48d7927b PB |
134 | BLANK(); |
135 | #ifdef MULTI_DABORT | |
136 | DEFINE(PROCESSOR_DABT_FUNC, offsetof(struct processor, _data_abort)); | |
137 | #endif | |
138 | #ifdef MULTI_PABORT | |
139 | DEFINE(PROCESSOR_PABT_FUNC, offsetof(struct processor, _prefetch_abort)); | |
f6b0fa02 RK |
140 | #endif |
141 | #ifdef MULTI_CPU | |
142 | DEFINE(CPU_SLEEP_SIZE, offsetof(struct processor, suspend_size)); | |
143 | DEFINE(CPU_DO_SUSPEND, offsetof(struct processor, do_suspend)); | |
144 | DEFINE(CPU_DO_RESUME, offsetof(struct processor, do_resume)); | |
145 | #endif | |
146 | #ifdef MULTI_CACHE | |
147 | DEFINE(CACHE_FLUSH_KERN_ALL, offsetof(struct cpu_cache_fns, flush_kern_all)); | |
48d7927b | 148 | #endif |
a9c9147e RK |
149 | BLANK(); |
150 | DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL); | |
151 | DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE); | |
152 | DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE); | |
7fe31d28 | 153 | BLANK(); |
1ae98561 | 154 | DEFINE(CACHE_WRITEBACK_ORDER, __CACHE_WRITEBACK_ORDER); |
7fe31d28 DM |
155 | DEFINE(CACHE_WRITEBACK_GRANULE, __CACHE_WRITEBACK_GRANULE); |
156 | BLANK(); | |
f7ed45be CD |
157 | #ifdef CONFIG_KVM_ARM_HOST |
158 | DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm)); | |
159 | DEFINE(VCPU_MIDR, offsetof(struct kvm_vcpu, arch.midr)); | |
160 | DEFINE(VCPU_CP15, offsetof(struct kvm_vcpu, arch.cp15)); | |
161 | DEFINE(VCPU_VFP_GUEST, offsetof(struct kvm_vcpu, arch.vfp_guest)); | |
3de50da6 | 162 | DEFINE(VCPU_VFP_HOST, offsetof(struct kvm_vcpu, arch.host_cpu_context)); |
f7ed45be CD |
163 | DEFINE(VCPU_REGS, offsetof(struct kvm_vcpu, arch.regs)); |
164 | DEFINE(VCPU_USR_REGS, offsetof(struct kvm_vcpu, arch.regs.usr_regs)); | |
165 | DEFINE(VCPU_SVC_REGS, offsetof(struct kvm_vcpu, arch.regs.svc_regs)); | |
166 | DEFINE(VCPU_ABT_REGS, offsetof(struct kvm_vcpu, arch.regs.abt_regs)); | |
167 | DEFINE(VCPU_UND_REGS, offsetof(struct kvm_vcpu, arch.regs.und_regs)); | |
168 | DEFINE(VCPU_IRQ_REGS, offsetof(struct kvm_vcpu, arch.regs.irq_regs)); | |
169 | DEFINE(VCPU_FIQ_REGS, offsetof(struct kvm_vcpu, arch.regs.fiq_regs)); | |
170 | DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_pc)); | |
171 | DEFINE(VCPU_CPSR, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_cpsr)); | |
172 | DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines)); | |
7393b599 MZ |
173 | DEFINE(VCPU_HSR, offsetof(struct kvm_vcpu, arch.fault.hsr)); |
174 | DEFINE(VCPU_HxFAR, offsetof(struct kvm_vcpu, arch.fault.hxfar)); | |
175 | DEFINE(VCPU_HPFAR, offsetof(struct kvm_vcpu, arch.fault.hpfar)); | |
176 | DEFINE(VCPU_HYP_PC, offsetof(struct kvm_vcpu, arch.fault.hyp_pc)); | |
348b2b07 MZ |
177 | #ifdef CONFIG_KVM_ARM_VGIC |
178 | DEFINE(VCPU_VGIC_CPU, offsetof(struct kvm_vcpu, arch.vgic_cpu)); | |
179 | DEFINE(VGIC_CPU_HCR, offsetof(struct vgic_cpu, vgic_hcr)); | |
180 | DEFINE(VGIC_CPU_VMCR, offsetof(struct vgic_cpu, vgic_vmcr)); | |
181 | DEFINE(VGIC_CPU_MISR, offsetof(struct vgic_cpu, vgic_misr)); | |
182 | DEFINE(VGIC_CPU_EISR, offsetof(struct vgic_cpu, vgic_eisr)); | |
183 | DEFINE(VGIC_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_elrsr)); | |
184 | DEFINE(VGIC_CPU_APR, offsetof(struct vgic_cpu, vgic_apr)); | |
185 | DEFINE(VGIC_CPU_LR, offsetof(struct vgic_cpu, vgic_lr)); | |
186 | DEFINE(VGIC_CPU_NR_LR, offsetof(struct vgic_cpu, nr_lr)); | |
c7e3ba64 MZ |
187 | #ifdef CONFIG_KVM_ARM_TIMER |
188 | DEFINE(VCPU_TIMER_CNTV_CTL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl)); | |
189 | DEFINE(VCPU_TIMER_CNTV_CVAL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval)); | |
190 | DEFINE(KVM_TIMER_CNTVOFF, offsetof(struct kvm, arch.timer.cntvoff)); | |
191 | DEFINE(KVM_TIMER_ENABLED, offsetof(struct kvm, arch.timer.enabled)); | |
192 | #endif | |
348b2b07 MZ |
193 | DEFINE(KVM_VGIC_VCTRL, offsetof(struct kvm, arch.vgic.vctrl_base)); |
194 | #endif | |
f7ed45be CD |
195 | DEFINE(KVM_VTTBR, offsetof(struct kvm, arch.vttbr)); |
196 | #endif | |
6fa3eb70 S |
197 | DEFINE(PBE_ADDRESS, offsetof(struct pbe, address)); |
198 | DEFINE(PBE_ORIG_ADDRESS, offsetof(struct pbe, orig_address)); | |
199 | DEFINE(PBE_NEXT, offsetof(struct pbe, next)); | |
1da177e4 LT |
200 | return 0; |
201 | } |