projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 9ae6f740 TP |
1 | /* |
| 2 | * Device Tree Include file for Marvell Armada XP family SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Marvell | |
| 5 | * | |
| 6 | * Lior Amsalem <alior@marvell.com> | |
| 7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
| 8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
| 9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
| 10 | * | |
| 11 | * This file is licensed under the terms of the GNU General Public | |
| 12 | * License version 2. This program is licensed "as is" without any | |
| 13 | * warranty of any kind, whether express or implied. | |
| 14 | * | |
| 10b683cb | 15 | * Contains definitions specific to the Armada XP SoC that are not |
| 9ae6f740 TP |
16 | * common to all Armada SoCs. |
| 17 | */ | |
| 18 | ||
| 19 | /include/ "armada-370-xp.dtsi" | |
| 20 | ||
| 21 | / { | |
| 22 | model = "Marvell Armada XP family SoC"; | |
| 23 | compatible = "marvell,armadaxp", "marvell,armada-370-xp"; | |
| 24 | ||
| 2f96fbb7 GC |
25 | L2: l2-cache { |
| 26 | compatible = "marvell,aurora-system-cache"; | |
| 27 | reg = <0xd0008000 0x1000>; | |
| 28 | cache-id-part = <0x100>; | |
| 29 | wt-override; | |
| 30 | }; | |
| 31 | ||
| 9ae6f740 | 32 | mpic: interrupt-controller@d0020000 { |
| 3202bf01 | 33 | reg = <0xd0020a00 0x2d0>, |
| 344e873e | 34 | <0xd0021070 0x58>; |
| 9ae6f740 TP |
35 | }; |
| 36 | ||
| 7444dad2 GC |
37 | armada-370-xp-pmsu@d0022000 { |
| 38 | compatible = "marvell,armada-370-xp-pmsu"; | |
| 39 | reg = <0xd0022100 0x430>, | |
| 40 | <0xd0020800 0x20>; | |
| 9ae6f740 TP |
41 | }; |
| 42 | ||
| 43 | soc { | |
| 44 | serial@d0012200 { | |
| b24212fb | 45 | compatible = "snps,dw-apb-uart"; |
| 9ae6f740 TP |
46 | reg = <0xd0012200 0x100>; |
| 47 | reg-shift = <2>; | |
| 48 | interrupts = <43>; | |
| e366154f | 49 | reg-io-width = <1>; |
| 9ae6f740 TP |
50 | status = "disabled"; |
| 51 | }; | |
| 52 | serial@d0012300 { | |
| b24212fb | 53 | compatible = "snps,dw-apb-uart"; |
| 9ae6f740 TP |
54 | reg = <0xd0012300 0x100>; |
| 55 | reg-shift = <2>; | |
| 56 | interrupts = <44>; | |
| e366154f | 57 | reg-io-width = <1>; |
| 9ae6f740 TP |
58 | status = "disabled"; |
| 59 | }; | |
| 60 | ||
| 61 | timer@d0020300 { | |
| 62 | marvell,timer-25Mhz; | |
| 63 | }; | |
| 64 | ||
| 9d202783 GC |
65 | coreclk: mvebu-sar@d0018230 { |
| 66 | compatible = "marvell,armada-xp-core-clock"; | |
| 67 | reg = <0xd0018230 0x08>; | |
| 68 | #clock-cells = <1>; | |
| 69 | }; | |
| 70 | ||
| 71 | cpuclk: clock-complex@d0018700 { | |
| 72 | #clock-cells = <1>; | |
| 73 | compatible = "marvell,armada-xp-cpu-clock"; | |
| 74 | reg = <0xd0018700 0xA0>; | |
| 75 | clocks = <&coreclk 1>; | |
| 76 | }; | |
| 77 | ||
| 78 | gateclk: clock-gating-control@d0018220 { | |
| 79 | compatible = "marvell,armada-xp-gating-clock"; | |
| 80 | reg = <0xd0018220 0x4>; | |
| 81 | clocks = <&coreclk 0>; | |
| 82 | #clock-cells = <1>; | |
| 83 | }; | |
| 84 | ||
| 9ae6f740 TP |
85 | system-controller@d0018200 { |
| 86 | compatible = "marvell,armada-370-xp-system-controller"; | |
| 87 | reg = <0xd0018200 0x500>; | |
| 88 | }; | |
| 323c1010 TP |
89 | |
| 90 | ethernet@d0030000 { | |
| 91 | compatible = "marvell,armada-370-neta"; | |
| 92 | reg = <0xd0030000 0x2500>; | |
| 93 | interrupts = <12>; | |
| 4aa935a2 | 94 | clocks = <&gateclk 2>; |
| 323c1010 TP |
95 | status = "disabled"; |
| 96 | }; | |
| 97 | ||
| a1d53dab TP |
98 | xor@d0060900 { |
| 99 | compatible = "marvell,orion-xor"; | |
| 100 | reg = <0xd0060900 0x100 | |
| 101 | 0xd0060b00 0x100>; | |
| 102 | clocks = <&gateclk 22>; | |
| 103 | status = "okay"; | |
| 104 | ||
| 105 | xor10 { | |
| 106 | interrupts = <51>; | |
| 107 | dmacap,memcpy; | |
| 108 | dmacap,xor; | |
| 109 | }; | |
| 110 | xor11 { | |
| 111 | interrupts = <52>; | |
| 112 | dmacap,memcpy; | |
| 113 | dmacap,xor; | |
| 114 | dmacap,memset; | |
| 115 | }; | |
| 116 | }; | |
| 117 | ||
| 118 | xor@d00f0900 { | |
| 119 | compatible = "marvell,orion-xor"; | |
| 120 | reg = <0xd00F0900 0x100 | |
| 121 | 0xd00F0B00 0x100>; | |
| 122 | clocks = <&gateclk 28>; | |
| 123 | status = "okay"; | |
| 124 | ||
| 125 | xor00 { | |
| 126 | interrupts = <94>; | |
| 127 | dmacap,memcpy; | |
| 128 | dmacap,xor; | |
| 129 | }; | |
| 130 | xor01 { | |
| 131 | interrupts = <95>; | |
| 132 | dmacap,memcpy; | |
| 133 | dmacap,xor; | |
| 134 | dmacap,memset; | |
| 135 | }; | |
| 136 | }; | |
| b2bb806f EG |
137 | |
| 138 | usb@d0050000 { | |
| 139 | clocks = <&gateclk 18>; | |
| 140 | }; | |
| 141 | ||
| 142 | usb@d0051000 { | |
| 143 | clocks = <&gateclk 19>; | |
| 144 | }; | |
| 145 | ||
| 146 | usb@d0052000 { | |
| 147 | compatible = "marvell,orion-ehci"; | |
| 148 | reg = <0xd0052000 0x500>; | |
| 149 | interrupts = <47>; | |
| 150 | clocks = <&gateclk 20>; | |
| 151 | status = "disabled"; | |
| 152 | }; | |
| 153 | ||
| 9ae6f740 TP |
154 | }; |
| 155 | }; |