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2744e8af LW |
1 | PINCTRL (PIN CONTROL) subsystem |
2 | This document outlines the pin control subsystem in Linux | |
3 | ||
4 | This subsystem deals with: | |
5 | ||
6 | - Enumerating and naming controllable pins | |
7 | ||
8 | - Multiplexing of pins, pads, fingers (etc) see below for details | |
9 | ||
ae6b4d85 LW |
10 | - Configuration of pins, pads, fingers (etc), such as software-controlled |
11 | biasing and driving mode specific pins, such as pull-up/down, open drain, | |
12 | load capacitance etc. | |
2744e8af LW |
13 | |
14 | Top-level interface | |
15 | =================== | |
16 | ||
17 | Definition of PIN CONTROLLER: | |
18 | ||
19 | - A pin controller is a piece of hardware, usually a set of registers, that | |
20 | can control PINs. It may be able to multiplex, bias, set load capacitance, | |
21 | set drive strength etc for individual pins or groups of pins. | |
22 | ||
23 | Definition of PIN: | |
24 | ||
25 | - PINS are equal to pads, fingers, balls or whatever packaging input or | |
26 | output line you want to control and these are denoted by unsigned integers | |
27 | in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so | |
28 | there may be several such number spaces in a system. This pin space may | |
29 | be sparse - i.e. there may be gaps in the space with numbers where no | |
30 | pin exists. | |
31 | ||
336cdba0 | 32 | When a PIN CONTROLLER is instantiated, it will register a descriptor to the |
2744e8af LW |
33 | pin control framework, and this descriptor contains an array of pin descriptors |
34 | describing the pins handled by this specific pin controller. | |
35 | ||
36 | Here is an example of a PGA (Pin Grid Array) chip seen from underneath: | |
37 | ||
38 | A B C D E F G H | |
39 | ||
40 | 8 o o o o o o o o | |
41 | ||
42 | 7 o o o o o o o o | |
43 | ||
44 | 6 o o o o o o o o | |
45 | ||
46 | 5 o o o o o o o o | |
47 | ||
48 | 4 o o o o o o o o | |
49 | ||
50 | 3 o o o o o o o o | |
51 | ||
52 | 2 o o o o o o o o | |
53 | ||
54 | 1 o o o o o o o o | |
55 | ||
56 | To register a pin controller and name all the pins on this package we can do | |
57 | this in our driver: | |
58 | ||
59 | #include <linux/pinctrl/pinctrl.h> | |
60 | ||
336cdba0 LW |
61 | const struct pinctrl_pin_desc foo_pins[] = { |
62 | PINCTRL_PIN(0, "A8"), | |
63 | PINCTRL_PIN(1, "B8"), | |
64 | PINCTRL_PIN(2, "C8"), | |
2744e8af | 65 | ... |
336cdba0 LW |
66 | PINCTRL_PIN(61, "F1"), |
67 | PINCTRL_PIN(62, "G1"), | |
68 | PINCTRL_PIN(63, "H1"), | |
2744e8af LW |
69 | }; |
70 | ||
71 | static struct pinctrl_desc foo_desc = { | |
72 | .name = "foo", | |
73 | .pins = foo_pins, | |
74 | .npins = ARRAY_SIZE(foo_pins), | |
75 | .maxpin = 63, | |
76 | .owner = THIS_MODULE, | |
77 | }; | |
78 | ||
79 | int __init foo_probe(void) | |
80 | { | |
81 | struct pinctrl_dev *pctl; | |
82 | ||
83 | pctl = pinctrl_register(&foo_desc, <PARENT>, NULL); | |
84 | if (IS_ERR(pctl)) | |
85 | pr_err("could not register foo pin driver\n"); | |
86 | } | |
87 | ||
ae6b4d85 LW |
88 | To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and |
89 | selected drivers, you need to select them from your machine's Kconfig entry, | |
90 | since these are so tightly integrated with the machines they are used on. | |
91 | See for example arch/arm/mach-u300/Kconfig for an example. | |
92 | ||
2744e8af LW |
93 | Pins usually have fancier names than this. You can find these in the dataheet |
94 | for your chip. Notice that the core pinctrl.h file provides a fancy macro | |
95 | called PINCTRL_PIN() to create the struct entries. As you can see I enumerated | |
336cdba0 LW |
96 | the pins from 0 in the upper left corner to 63 in the lower right corner. |
97 | This enumeration was arbitrarily chosen, in practice you need to think | |
2744e8af LW |
98 | through your numbering system so that it matches the layout of registers |
99 | and such things in your driver, or the code may become complicated. You must | |
100 | also consider matching of offsets to the GPIO ranges that may be handled by | |
101 | the pin controller. | |
102 | ||
103 | For a padring with 467 pads, as opposed to actual pins, I used an enumeration | |
104 | like this, walking around the edge of the chip, which seems to be industry | |
105 | standard too (all these pads had names, too): | |
106 | ||
107 | ||
108 | 0 ..... 104 | |
109 | 466 105 | |
110 | . . | |
111 | . . | |
112 | 358 224 | |
113 | 357 .... 225 | |
114 | ||
115 | ||
116 | Pin groups | |
117 | ========== | |
118 | ||
119 | Many controllers need to deal with groups of pins, so the pin controller | |
120 | subsystem has a mechanism for enumerating groups of pins and retrieving the | |
121 | actual enumerated pins that are part of a certain group. | |
122 | ||
123 | For example, say that we have a group of pins dealing with an SPI interface | |
124 | on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins | |
125 | on { 24, 25 }. | |
126 | ||
127 | These two groups are presented to the pin control subsystem by implementing | |
128 | some generic pinctrl_ops like this: | |
129 | ||
130 | #include <linux/pinctrl/pinctrl.h> | |
131 | ||
132 | struct foo_group { | |
133 | const char *name; | |
134 | const unsigned int *pins; | |
135 | const unsigned num_pins; | |
136 | }; | |
137 | ||
336cdba0 LW |
138 | static const unsigned int spi0_pins[] = { 0, 8, 16, 24 }; |
139 | static const unsigned int i2c0_pins[] = { 24, 25 }; | |
2744e8af LW |
140 | |
141 | static const struct foo_group foo_groups[] = { | |
142 | { | |
143 | .name = "spi0_grp", | |
144 | .pins = spi0_pins, | |
145 | .num_pins = ARRAY_SIZE(spi0_pins), | |
146 | }, | |
147 | { | |
148 | .name = "i2c0_grp", | |
149 | .pins = i2c0_pins, | |
150 | .num_pins = ARRAY_SIZE(i2c0_pins), | |
151 | }, | |
152 | }; | |
153 | ||
154 | ||
155 | static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector) | |
156 | { | |
157 | if (selector >= ARRAY_SIZE(foo_groups)) | |
158 | return -EINVAL; | |
159 | return 0; | |
160 | } | |
161 | ||
162 | static const char *foo_get_group_name(struct pinctrl_dev *pctldev, | |
163 | unsigned selector) | |
164 | { | |
165 | return foo_groups[selector].name; | |
166 | } | |
167 | ||
168 | static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
169 | unsigned ** const pins, | |
170 | unsigned * const num_pins) | |
171 | { | |
172 | *pins = (unsigned *) foo_groups[selector].pins; | |
173 | *num_pins = foo_groups[selector].num_pins; | |
174 | return 0; | |
175 | } | |
176 | ||
177 | static struct pinctrl_ops foo_pctrl_ops = { | |
178 | .list_groups = foo_list_groups, | |
179 | .get_group_name = foo_get_group_name, | |
180 | .get_group_pins = foo_get_group_pins, | |
181 | }; | |
182 | ||
183 | ||
184 | static struct pinctrl_desc foo_desc = { | |
185 | ... | |
186 | .pctlops = &foo_pctrl_ops, | |
187 | }; | |
188 | ||
189 | The pin control subsystem will call the .list_groups() function repeatedly | |
190 | beginning on 0 until it returns non-zero to determine legal selectors, then | |
191 | it will call the other functions to retrieve the name and pins of the group. | |
192 | Maintaining the data structure of the groups is up to the driver, this is | |
193 | just a simple example - in practice you may need more entries in your group | |
194 | structure, for example specific register ranges associated with each group | |
195 | and so on. | |
196 | ||
197 | ||
ae6b4d85 LW |
198 | Pin configuration |
199 | ================= | |
200 | ||
201 | Pins can sometimes be software-configured in an various ways, mostly related | |
202 | to their electronic properties when used as inputs or outputs. For example you | |
203 | may be able to make an output pin high impedance, or "tristate" meaning it is | |
204 | effectively disconnected. You may be able to connect an input pin to VDD or GND | |
205 | using a certain resistor value - pull up and pull down - so that the pin has a | |
206 | stable value when nothing is driving the rail it is connected to, or when it's | |
207 | unconnected. | |
208 | ||
209 | For example, a platform may do this: | |
210 | ||
28a8d14c LW |
211 | #include <linux/pinctrl/consumer.h> |
212 | ||
43699dea | 213 | ret = pin_config_set("foo-dev", "FOO_GPIO_PIN", PLATFORM_X_PULL_UP); |
ae6b4d85 LW |
214 | |
215 | To pull up a pin to VDD. The pin configuration driver implements callbacks for | |
216 | changing pin configuration in the pin controller ops like this: | |
217 | ||
218 | #include <linux/pinctrl/pinctrl.h> | |
219 | #include <linux/pinctrl/pinconf.h> | |
220 | #include "platform_x_pindefs.h" | |
221 | ||
e6337c3c | 222 | static int foo_pin_config_get(struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
223 | unsigned offset, |
224 | unsigned long *config) | |
225 | { | |
226 | struct my_conftype conf; | |
227 | ||
228 | ... Find setting for pin @ offset ... | |
229 | ||
230 | *config = (unsigned long) conf; | |
231 | } | |
232 | ||
e6337c3c | 233 | static int foo_pin_config_set(struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
234 | unsigned offset, |
235 | unsigned long config) | |
236 | { | |
237 | struct my_conftype *conf = (struct my_conftype *) config; | |
238 | ||
239 | switch (conf) { | |
240 | case PLATFORM_X_PULL_UP: | |
241 | ... | |
242 | } | |
243 | } | |
244 | } | |
245 | ||
e6337c3c | 246 | static int foo_pin_config_group_get (struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
247 | unsigned selector, |
248 | unsigned long *config) | |
249 | { | |
250 | ... | |
251 | } | |
252 | ||
e6337c3c | 253 | static int foo_pin_config_group_set (struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
254 | unsigned selector, |
255 | unsigned long config) | |
256 | { | |
257 | ... | |
258 | } | |
259 | ||
260 | static struct pinconf_ops foo_pconf_ops = { | |
261 | .pin_config_get = foo_pin_config_get, | |
262 | .pin_config_set = foo_pin_config_set, | |
263 | .pin_config_group_get = foo_pin_config_group_get, | |
264 | .pin_config_group_set = foo_pin_config_group_set, | |
265 | }; | |
266 | ||
267 | /* Pin config operations are handled by some pin controller */ | |
268 | static struct pinctrl_desc foo_desc = { | |
269 | ... | |
270 | .confops = &foo_pconf_ops, | |
271 | }; | |
272 | ||
273 | Since some controllers have special logic for handling entire groups of pins | |
274 | they can exploit the special whole-group pin control function. The | |
275 | pin_config_group_set() callback is allowed to return the error code -EAGAIN, | |
276 | for groups it does not want to handle, or if it just wants to do some | |
277 | group-level handling and then fall through to iterate over all pins, in which | |
278 | case each individual pin will be treated by separate pin_config_set() calls as | |
279 | well. | |
280 | ||
281 | ||
2744e8af LW |
282 | Interaction with the GPIO subsystem |
283 | =================================== | |
284 | ||
285 | The GPIO drivers may want to perform operations of various types on the same | |
286 | physical pins that are also registered as pin controller pins. | |
287 | ||
288 | Since the pin controller subsystem have its pinspace local to the pin | |
289 | controller we need a mapping so that the pin control subsystem can figure out | |
290 | which pin controller handles control of a certain GPIO pin. Since a single | |
291 | pin controller may be muxing several GPIO ranges (typically SoCs that have | |
292 | one set of pins but internally several GPIO silicon blocks, each modeled as | |
293 | a struct gpio_chip) any number of GPIO ranges can be added to a pin controller | |
294 | instance like this: | |
295 | ||
296 | struct gpio_chip chip_a; | |
297 | struct gpio_chip chip_b; | |
298 | ||
299 | static struct pinctrl_gpio_range gpio_range_a = { | |
300 | .name = "chip a", | |
301 | .id = 0, | |
302 | .base = 32, | |
3c739ad0 | 303 | .pin_base = 32, |
2744e8af LW |
304 | .npins = 16, |
305 | .gc = &chip_a; | |
306 | }; | |
307 | ||
3c739ad0 | 308 | static struct pinctrl_gpio_range gpio_range_b = { |
2744e8af LW |
309 | .name = "chip b", |
310 | .id = 0, | |
311 | .base = 48, | |
3c739ad0 | 312 | .pin_base = 64, |
2744e8af LW |
313 | .npins = 8, |
314 | .gc = &chip_b; | |
315 | }; | |
316 | ||
2744e8af LW |
317 | { |
318 | struct pinctrl_dev *pctl; | |
319 | ... | |
320 | pinctrl_add_gpio_range(pctl, &gpio_range_a); | |
321 | pinctrl_add_gpio_range(pctl, &gpio_range_b); | |
322 | } | |
323 | ||
324 | So this complex system has one pin controller handling two different | |
3c739ad0 CP |
325 | GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and |
326 | "chip b" have different .pin_base, which means a start pin number of the | |
327 | GPIO range. | |
328 | ||
329 | The GPIO range of "chip a" starts from the GPIO base of 32 and actual | |
330 | pin range also starts from 32. However "chip b" has different starting | |
331 | offset for the GPIO range and pin range. The GPIO range of "chip b" starts | |
332 | from GPIO number 48, while the pin range of "chip b" starts from 64. | |
2744e8af | 333 | |
3c739ad0 CP |
334 | We can convert a gpio number to actual pin number using this "pin_base". |
335 | They are mapped in the global GPIO pin space at: | |
336 | ||
337 | chip a: | |
338 | - GPIO range : [32 .. 47] | |
339 | - pin range : [32 .. 47] | |
340 | chip b: | |
341 | - GPIO range : [48 .. 55] | |
342 | - pin range : [64 .. 71] | |
2744e8af LW |
343 | |
344 | When GPIO-specific functions in the pin control subsystem are called, these | |
336cdba0 | 345 | ranges will be used to look up the appropriate pin controller by inspecting |
2744e8af LW |
346 | and matching the pin to the pin ranges across all controllers. When a |
347 | pin controller handling the matching range is found, GPIO-specific functions | |
348 | will be called on that specific pin controller. | |
349 | ||
350 | For all functionalities dealing with pin biasing, pin muxing etc, the pin | |
351 | controller subsystem will subtract the range's .base offset from the passed | |
3c739ad0 CP |
352 | in gpio number, and add the ranges's .pin_base offset to retrive a pin number. |
353 | After that, the subsystem passes it on to the pin control driver, so the driver | |
354 | will get an pin number into its handled number range. Further it is also passed | |
2744e8af LW |
355 | the range ID value, so that the pin controller knows which range it should |
356 | deal with. | |
357 | ||
2744e8af LW |
358 | PINMUX interfaces |
359 | ================= | |
360 | ||
361 | These calls use the pinmux_* naming prefix. No other calls should use that | |
362 | prefix. | |
363 | ||
364 | ||
365 | What is pinmuxing? | |
366 | ================== | |
367 | ||
368 | PINMUX, also known as padmux, ballmux, alternate functions or mission modes | |
369 | is a way for chip vendors producing some kind of electrical packages to use | |
370 | a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive | |
371 | functions, depending on the application. By "application" in this context | |
372 | we usually mean a way of soldering or wiring the package into an electronic | |
373 | system, even though the framework makes it possible to also change the function | |
374 | at runtime. | |
375 | ||
376 | Here is an example of a PGA (Pin Grid Array) chip seen from underneath: | |
377 | ||
378 | A B C D E F G H | |
379 | +---+ | |
380 | 8 | o | o o o o o o o | |
381 | | | | |
382 | 7 | o | o o o o o o o | |
383 | | | | |
384 | 6 | o | o o o o o o o | |
385 | +---+---+ | |
386 | 5 | o | o | o o o o o o | |
387 | +---+---+ +---+ | |
388 | 4 o o o o o o | o | o | |
389 | | | | |
390 | 3 o o o o o o | o | o | |
391 | | | | |
392 | 2 o o o o o o | o | o | |
393 | +-------+-------+-------+---+---+ | |
394 | 1 | o o | o o | o o | o | o | | |
395 | +-------+-------+-------+---+---+ | |
396 | ||
397 | This is not tetris. The game to think of is chess. Not all PGA/BGA packages | |
398 | are chessboard-like, big ones have "holes" in some arrangement according to | |
399 | different design patterns, but we're using this as a simple example. Of the | |
400 | pins you see some will be taken by things like a few VCC and GND to feed power | |
401 | to the chip, and quite a few will be taken by large ports like an external | |
402 | memory interface. The remaining pins will often be subject to pin multiplexing. | |
403 | ||
404 | The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to | |
405 | its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using | |
406 | pinctrl_register_pins() and a suitable data set as shown earlier. | |
407 | ||
408 | In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port | |
409 | (these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as | |
410 | some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can | |
411 | be used as an I2C port (these are just two pins: SCL, SDA). Needless to say, | |
412 | we cannot use the SPI port and I2C port at the same time. However in the inside | |
413 | of the package the silicon performing the SPI logic can alternatively be routed | |
414 | out on pins { G4, G3, G2, G1 }. | |
415 | ||
416 | On the botton row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something | |
417 | special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will | |
418 | consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or | |
419 | { A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI | |
420 | port on pins { G4, G3, G2, G1 } of course. | |
421 | ||
422 | This way the silicon blocks present inside the chip can be multiplexed "muxed" | |
423 | out on different pin ranges. Often contemporary SoC (systems on chip) will | |
424 | contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to | |
425 | different pins by pinmux settings. | |
426 | ||
427 | Since general-purpose I/O pins (GPIO) are typically always in shortage, it is | |
428 | common to be able to use almost any pin as a GPIO pin if it is not currently | |
429 | in use by some other I/O port. | |
430 | ||
431 | ||
432 | Pinmux conventions | |
433 | ================== | |
434 | ||
435 | The purpose of the pinmux functionality in the pin controller subsystem is to | |
436 | abstract and provide pinmux settings to the devices you choose to instantiate | |
437 | in your machine configuration. It is inspired by the clk, GPIO and regulator | |
438 | subsystems, so devices will request their mux setting, but it's also possible | |
439 | to request a single pin for e.g. GPIO. | |
440 | ||
441 | Definitions: | |
442 | ||
443 | - FUNCTIONS can be switched in and out by a driver residing with the pin | |
444 | control subsystem in the drivers/pinctrl/* directory of the kernel. The | |
445 | pin control driver knows the possible functions. In the example above you can | |
446 | identify three pinmux functions, one for spi, one for i2c and one for mmc. | |
447 | ||
448 | - FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array. | |
449 | In this case the array could be something like: { spi0, i2c0, mmc0 } | |
450 | for the three available functions. | |
451 | ||
452 | - FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain | |
453 | function is *always* associated with a certain set of pin groups, could | |
454 | be just a single one, but could also be many. In the example above the | |
455 | function i2c is associated with the pins { A5, B5 }, enumerated as | |
456 | { 24, 25 } in the controller pin space. | |
457 | ||
458 | The Function spi is associated with pin groups { A8, A7, A6, A5 } | |
459 | and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and | |
460 | { 38, 46, 54, 62 } respectively. | |
461 | ||
462 | Group names must be unique per pin controller, no two groups on the same | |
463 | controller may have the same name. | |
464 | ||
465 | - The combination of a FUNCTION and a PIN GROUP determine a certain function | |
466 | for a certain set of pins. The knowledge of the functions and pin groups | |
467 | and their machine-specific particulars are kept inside the pinmux driver, | |
468 | from the outside only the enumerators are known, and the driver core can: | |
469 | ||
470 | - Request the name of a function with a certain selector (>= 0) | |
471 | - A list of groups associated with a certain function | |
472 | - Request that a certain group in that list to be activated for a certain | |
473 | function | |
474 | ||
475 | As already described above, pin groups are in turn self-descriptive, so | |
476 | the core will retrieve the actual pin range in a certain group from the | |
477 | driver. | |
478 | ||
479 | - FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain | |
480 | device by the board file, device tree or similar machine setup configuration | |
481 | mechanism, similar to how regulators are connected to devices, usually by | |
482 | name. Defining a pin controller, function and group thus uniquely identify | |
483 | the set of pins to be used by a certain device. (If only one possible group | |
484 | of pins is available for the function, no group name need to be supplied - | |
485 | the core will simply select the first and only group available.) | |
486 | ||
487 | In the example case we can define that this particular machine shall | |
488 | use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function | |
489 | fi2c0 group gi2c0, on the primary pin controller, we get mappings | |
490 | like these: | |
491 | ||
492 | { | |
493 | {"map-spi0", spi0, pinctrl0, fspi0, gspi0}, | |
494 | {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0} | |
495 | } | |
496 | ||
497 | Every map must be assigned a symbolic name, pin controller and function. | |
498 | The group is not compulsory - if it is omitted the first group presented by | |
499 | the driver as applicable for the function will be selected, which is | |
500 | useful for simple cases. | |
501 | ||
502 | The device name is present in map entries tied to specific devices. Maps | |
503 | without device names are referred to as SYSTEM pinmuxes, such as can be taken | |
504 | by the machine implementation on boot and not tied to any specific device. | |
505 | ||
506 | It is possible to map several groups to the same combination of device, | |
507 | pin controller and function. This is for cases where a certain function on | |
508 | a certain pin controller may use different sets of pins in different | |
509 | configurations. | |
510 | ||
511 | - PINS for a certain FUNCTION using a certain PIN GROUP on a certain | |
512 | PIN CONTROLLER are provided on a first-come first-serve basis, so if some | |
513 | other device mux setting or GPIO pin request has already taken your physical | |
514 | pin, you will be denied the use of it. To get (activate) a new setting, the | |
515 | old one has to be put (deactivated) first. | |
516 | ||
517 | Sometimes the documentation and hardware registers will be oriented around | |
518 | pads (or "fingers") rather than pins - these are the soldering surfaces on the | |
519 | silicon inside the package, and may or may not match the actual number of | |
520 | pins/balls underneath the capsule. Pick some enumeration that makes sense to | |
521 | you. Define enumerators only for the pins you can control if that makes sense. | |
522 | ||
523 | Assumptions: | |
524 | ||
336cdba0 | 525 | We assume that the number of possible function maps to pin groups is limited by |
2744e8af LW |
526 | the hardware. I.e. we assume that there is no system where any function can be |
527 | mapped to any pin, like in a phone exchange. So the available pins groups for | |
528 | a certain function will be limited to a few choices (say up to eight or so), | |
529 | not hundreds or any amount of choices. This is the characteristic we have found | |
530 | by inspecting available pinmux hardware, and a necessary assumption since we | |
531 | expect pinmux drivers to present *all* possible function vs pin group mappings | |
532 | to the subsystem. | |
533 | ||
534 | ||
535 | Pinmux drivers | |
536 | ============== | |
537 | ||
538 | The pinmux core takes care of preventing conflicts on pins and calling | |
539 | the pin controller driver to execute different settings. | |
540 | ||
541 | It is the responsibility of the pinmux driver to impose further restrictions | |
542 | (say for example infer electronic limitations due to load etc) to determine | |
543 | whether or not the requested function can actually be allowed, and in case it | |
544 | is possible to perform the requested mux setting, poke the hardware so that | |
545 | this happens. | |
546 | ||
547 | Pinmux drivers are required to supply a few callback functions, some are | |
548 | optional. Usually the enable() and disable() functions are implemented, | |
549 | writing values into some certain registers to activate a certain mux setting | |
550 | for a certain pin. | |
551 | ||
552 | A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4 | |
553 | into some register named MUX to select a certain function with a certain | |
554 | group of pins would work something like this: | |
555 | ||
556 | #include <linux/pinctrl/pinctrl.h> | |
557 | #include <linux/pinctrl/pinmux.h> | |
558 | ||
559 | struct foo_group { | |
560 | const char *name; | |
561 | const unsigned int *pins; | |
562 | const unsigned num_pins; | |
563 | }; | |
564 | ||
565 | static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 }; | |
566 | static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 }; | |
567 | static const unsigned i2c0_pins[] = { 24, 25 }; | |
568 | static const unsigned mmc0_1_pins[] = { 56, 57 }; | |
569 | static const unsigned mmc0_2_pins[] = { 58, 59 }; | |
570 | static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 }; | |
571 | ||
572 | static const struct foo_group foo_groups[] = { | |
573 | { | |
574 | .name = "spi0_0_grp", | |
575 | .pins = spi0_0_pins, | |
576 | .num_pins = ARRAY_SIZE(spi0_0_pins), | |
577 | }, | |
578 | { | |
579 | .name = "spi0_1_grp", | |
580 | .pins = spi0_1_pins, | |
581 | .num_pins = ARRAY_SIZE(spi0_1_pins), | |
582 | }, | |
583 | { | |
584 | .name = "i2c0_grp", | |
585 | .pins = i2c0_pins, | |
586 | .num_pins = ARRAY_SIZE(i2c0_pins), | |
587 | }, | |
588 | { | |
589 | .name = "mmc0_1_grp", | |
590 | .pins = mmc0_1_pins, | |
591 | .num_pins = ARRAY_SIZE(mmc0_1_pins), | |
592 | }, | |
593 | { | |
594 | .name = "mmc0_2_grp", | |
595 | .pins = mmc0_2_pins, | |
596 | .num_pins = ARRAY_SIZE(mmc0_2_pins), | |
597 | }, | |
598 | { | |
599 | .name = "mmc0_3_grp", | |
600 | .pins = mmc0_3_pins, | |
601 | .num_pins = ARRAY_SIZE(mmc0_3_pins), | |
602 | }, | |
603 | }; | |
604 | ||
605 | ||
606 | static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector) | |
607 | { | |
608 | if (selector >= ARRAY_SIZE(foo_groups)) | |
609 | return -EINVAL; | |
610 | return 0; | |
611 | } | |
612 | ||
613 | static const char *foo_get_group_name(struct pinctrl_dev *pctldev, | |
614 | unsigned selector) | |
615 | { | |
616 | return foo_groups[selector].name; | |
617 | } | |
618 | ||
619 | static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
620 | unsigned ** const pins, | |
621 | unsigned * const num_pins) | |
622 | { | |
623 | *pins = (unsigned *) foo_groups[selector].pins; | |
624 | *num_pins = foo_groups[selector].num_pins; | |
625 | return 0; | |
626 | } | |
627 | ||
628 | static struct pinctrl_ops foo_pctrl_ops = { | |
629 | .list_groups = foo_list_groups, | |
630 | .get_group_name = foo_get_group_name, | |
631 | .get_group_pins = foo_get_group_pins, | |
632 | }; | |
633 | ||
634 | struct foo_pmx_func { | |
635 | const char *name; | |
636 | const char * const *groups; | |
637 | const unsigned num_groups; | |
638 | }; | |
639 | ||
640 | static const char * const spi0_groups[] = { "spi0_1_grp" }; | |
641 | static const char * const i2c0_groups[] = { "i2c0_grp" }; | |
642 | static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", | |
643 | "mmc0_3_grp" }; | |
644 | ||
645 | static const struct foo_pmx_func foo_functions[] = { | |
646 | { | |
647 | .name = "spi0", | |
648 | .groups = spi0_groups, | |
649 | .num_groups = ARRAY_SIZE(spi0_groups), | |
650 | }, | |
651 | { | |
652 | .name = "i2c0", | |
653 | .groups = i2c0_groups, | |
654 | .num_groups = ARRAY_SIZE(i2c0_groups), | |
655 | }, | |
656 | { | |
657 | .name = "mmc0", | |
658 | .groups = mmc0_groups, | |
659 | .num_groups = ARRAY_SIZE(mmc0_groups), | |
660 | }, | |
661 | }; | |
662 | ||
663 | int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector) | |
664 | { | |
665 | if (selector >= ARRAY_SIZE(foo_functions)) | |
666 | return -EINVAL; | |
667 | return 0; | |
668 | } | |
669 | ||
670 | const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector) | |
671 | { | |
336cdba0 | 672 | return foo_functions[selector].name; |
2744e8af LW |
673 | } |
674 | ||
675 | static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
676 | const char * const **groups, | |
677 | unsigned * const num_groups) | |
678 | { | |
679 | *groups = foo_functions[selector].groups; | |
680 | *num_groups = foo_functions[selector].num_groups; | |
681 | return 0; | |
682 | } | |
683 | ||
684 | int foo_enable(struct pinctrl_dev *pctldev, unsigned selector, | |
685 | unsigned group) | |
686 | { | |
336cdba0 | 687 | u8 regbit = (1 << selector + group); |
2744e8af LW |
688 | |
689 | writeb((readb(MUX)|regbit), MUX) | |
690 | return 0; | |
691 | } | |
692 | ||
336cdba0 | 693 | void foo_disable(struct pinctrl_dev *pctldev, unsigned selector, |
2744e8af LW |
694 | unsigned group) |
695 | { | |
336cdba0 | 696 | u8 regbit = (1 << selector + group); |
2744e8af LW |
697 | |
698 | writeb((readb(MUX) & ~(regbit)), MUX) | |
699 | return 0; | |
700 | } | |
701 | ||
702 | struct pinmux_ops foo_pmxops = { | |
703 | .list_functions = foo_list_funcs, | |
704 | .get_function_name = foo_get_fname, | |
705 | .get_function_groups = foo_get_groups, | |
706 | .enable = foo_enable, | |
707 | .disable = foo_disable, | |
708 | }; | |
709 | ||
710 | /* Pinmux operations are handled by some pin controller */ | |
711 | static struct pinctrl_desc foo_desc = { | |
712 | ... | |
713 | .pctlops = &foo_pctrl_ops, | |
714 | .pmxops = &foo_pmxops, | |
715 | }; | |
716 | ||
717 | In the example activating muxing 0 and 1 at the same time setting bits | |
718 | 0 and 1, uses one pin in common so they would collide. | |
719 | ||
720 | The beauty of the pinmux subsystem is that since it keeps track of all | |
721 | pins and who is using them, it will already have denied an impossible | |
722 | request like that, so the driver does not need to worry about such | |
723 | things - when it gets a selector passed in, the pinmux subsystem makes | |
724 | sure no other device or GPIO assignment is already using the selected | |
725 | pins. Thus bits 0 and 1 in the control register will never be set at the | |
726 | same time. | |
727 | ||
728 | All the above functions are mandatory to implement for a pinmux driver. | |
729 | ||
730 | ||
731 | Pinmux interaction with the GPIO subsystem | |
732 | ========================================== | |
733 | ||
542e704f LW |
734 | The public pinmux API contains two functions named pinmux_request_gpio() |
735 | and pinmux_free_gpio(). These two functions shall *ONLY* be called from | |
736 | gpiolib-based drivers as part of their gpio_request() and | |
737 | gpio_free() semantics. Likewise the pinmux_gpio_direction_[input|output] | |
738 | shall only be called from within respective gpio_direction_[input|output] | |
739 | gpiolib implementation. | |
740 | ||
741 | NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be | |
742 | muxed in. Instead, implement a proper gpiolib driver and have that driver | |
743 | request proper muxing for its pins. | |
744 | ||
2744e8af LW |
745 | The function list could become long, especially if you can convert every |
746 | individual pin into a GPIO pin independent of any other pins, and then try | |
747 | the approach to define every pin as a function. | |
748 | ||
749 | In this case, the function array would become 64 entries for each GPIO | |
750 | setting and then the device functions. | |
751 | ||
542e704f LW |
752 | For this reason there are two functions a pinmux driver can implement |
753 | to enable only GPIO on an individual pin: .gpio_request_enable() and | |
754 | .gpio_disable_free(). | |
2744e8af LW |
755 | |
756 | This function will pass in the affected GPIO range identified by the pin | |
757 | controller core, so you know which GPIO pins are being affected by the request | |
758 | operation. | |
759 | ||
542e704f LW |
760 | If your driver needs to have an indication from the framework of whether the |
761 | GPIO pin shall be used for input or output you can implement the | |
762 | .gpio_set_direction() function. As described this shall be called from the | |
763 | gpiolib driver and the affected GPIO range, pin offset and desired direction | |
764 | will be passed along to this function. | |
765 | ||
766 | Alternatively to using these special functions, it is fully allowed to use | |
767 | named functions for each GPIO pin, the pinmux_request_gpio() will attempt to | |
768 | obtain the function "gpioN" where "N" is the global GPIO pin number if no | |
769 | special GPIO-handler is registered. | |
2744e8af LW |
770 | |
771 | ||
772 | Pinmux board/machine configuration | |
773 | ================================== | |
774 | ||
775 | Boards and machines define how a certain complete running system is put | |
776 | together, including how GPIOs and devices are muxed, how regulators are | |
777 | constrained and how the clock tree looks. Of course pinmux settings are also | |
778 | part of this. | |
779 | ||
780 | A pinmux config for a machine looks pretty much like a simple regulator | |
781 | configuration, so for the example array above we want to enable i2c and | |
782 | spi on the second function mapping: | |
783 | ||
784 | #include <linux/pinctrl/machine.h> | |
785 | ||
97607d15 | 786 | static const struct pinmux_map __initdata pmx_mapping[] = { |
2744e8af | 787 | { |
51cd24ee | 788 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af LW |
789 | .function = "spi0", |
790 | .dev_name = "foo-spi.0", | |
791 | }, | |
792 | { | |
51cd24ee | 793 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af LW |
794 | .function = "i2c0", |
795 | .dev_name = "foo-i2c.0", | |
796 | }, | |
797 | { | |
51cd24ee | 798 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af LW |
799 | .function = "mmc0", |
800 | .dev_name = "foo-mmc.0", | |
801 | }, | |
802 | }; | |
803 | ||
804 | The dev_name here matches to the unique device name that can be used to look | |
805 | up the device struct (just like with clockdev or regulators). The function name | |
806 | must match a function provided by the pinmux driver handling this pin range. | |
807 | ||
808 | As you can see we may have several pin controllers on the system and thus | |
809 | we need to specify which one of them that contain the functions we wish | |
9dfac4fd | 810 | to map. |
2744e8af LW |
811 | |
812 | You register this pinmux mapping to the pinmux subsystem by simply: | |
813 | ||
336cdba0 | 814 | ret = pinmux_register_mappings(pmx_mapping, ARRAY_SIZE(pmx_mapping)); |
2744e8af LW |
815 | |
816 | Since the above construct is pretty common there is a helper macro to make | |
51cd24ee | 817 | it even more compact which assumes you want to use pinctrl-foo and position |
2744e8af LW |
818 | 0 for mapping, for example: |
819 | ||
97607d15 | 820 | static struct pinmux_map __initdata pmx_mapping[] = { |
e6337c3c | 821 | PINMUX_MAP("I2CMAP", "pinctrl-foo", "i2c0", "foo-i2c.0"), |
2744e8af LW |
822 | }; |
823 | ||
824 | ||
825 | Complex mappings | |
826 | ================ | |
827 | ||
828 | As it is possible to map a function to different groups of pins an optional | |
829 | .group can be specified like this: | |
830 | ||
831 | ... | |
832 | { | |
833 | .name = "spi0-pos-A", | |
51cd24ee | 834 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af LW |
835 | .function = "spi0", |
836 | .group = "spi0_0_grp", | |
837 | .dev_name = "foo-spi.0", | |
838 | }, | |
839 | { | |
840 | .name = "spi0-pos-B", | |
51cd24ee | 841 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af LW |
842 | .function = "spi0", |
843 | .group = "spi0_1_grp", | |
844 | .dev_name = "foo-spi.0", | |
845 | }, | |
846 | ... | |
847 | ||
848 | This example mapping is used to switch between two positions for spi0 at | |
849 | runtime, as described further below under the heading "Runtime pinmuxing". | |
850 | ||
851 | Further it is possible to match several groups of pins to the same function | |
852 | for a single device, say for example in the mmc0 example above, where you can | |
853 | additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all | |
854 | three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the | |
855 | case), we define a mapping like this: | |
856 | ||
857 | ... | |
858 | { | |
f54367f9 | 859 | .name = "2bit" |
51cd24ee | 860 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 861 | .function = "mmc0", |
336cdba0 | 862 | .group = "mmc0_1_grp", |
2744e8af LW |
863 | .dev_name = "foo-mmc.0", |
864 | }, | |
865 | { | |
f54367f9 | 866 | .name = "4bit" |
51cd24ee | 867 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 868 | .function = "mmc0", |
336cdba0 | 869 | .group = "mmc0_1_grp", |
2744e8af LW |
870 | .dev_name = "foo-mmc.0", |
871 | }, | |
872 | { | |
f54367f9 | 873 | .name = "4bit" |
51cd24ee | 874 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 875 | .function = "mmc0", |
336cdba0 | 876 | .group = "mmc0_2_grp", |
2744e8af LW |
877 | .dev_name = "foo-mmc.0", |
878 | }, | |
879 | { | |
f54367f9 | 880 | .name = "8bit" |
51cd24ee | 881 | .ctrl_dev_name = "pinctrl-foo", |
336cdba0 | 882 | .group = "mmc0_1_grp", |
2744e8af LW |
883 | .dev_name = "foo-mmc.0", |
884 | }, | |
885 | { | |
f54367f9 | 886 | .name = "8bit" |
51cd24ee | 887 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 888 | .function = "mmc0", |
336cdba0 | 889 | .group = "mmc0_2_grp", |
2744e8af LW |
890 | .dev_name = "foo-mmc.0", |
891 | }, | |
892 | { | |
f54367f9 | 893 | .name = "8bit" |
51cd24ee | 894 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 895 | .function = "mmc0", |
336cdba0 | 896 | .group = "mmc0_3_grp", |
2744e8af LW |
897 | .dev_name = "foo-mmc.0", |
898 | }, | |
899 | ... | |
900 | ||
901 | The result of grabbing this mapping from the device with something like | |
902 | this (see next paragraph): | |
903 | ||
904 | pmx = pinmux_get(&device, "8bit"); | |
905 | ||
906 | Will be that you activate all the three bottom records in the mapping at | |
907 | once. Since they share the same name, pin controller device, funcion and | |
908 | device, and since we allow multiple groups to match to a single device, they | |
909 | all get selected, and they all get enabled and disable simultaneously by the | |
910 | pinmux core. | |
911 | ||
912 | ||
913 | Pinmux requests from drivers | |
914 | ============================ | |
915 | ||
916 | Generally it is discouraged to let individual drivers get and enable pinmuxes. | |
917 | So if possible, handle the pinmuxes in platform code or some other place where | |
918 | you have access to all the affected struct device * pointers. In some cases | |
919 | where a driver needs to switch between different mux mappings at runtime | |
920 | this is not possible. | |
921 | ||
922 | A driver may request a certain mux to be activated, usually just the default | |
923 | mux like this: | |
924 | ||
28a8d14c | 925 | #include <linux/pinctrl/consumer.h> |
2744e8af LW |
926 | |
927 | struct foo_state { | |
928 | struct pinmux *pmx; | |
929 | ... | |
930 | }; | |
931 | ||
932 | foo_probe() | |
933 | { | |
934 | /* Allocate a state holder named "state" etc */ | |
935 | struct pinmux pmx; | |
936 | ||
937 | pmx = pinmux_get(&device, NULL); | |
938 | if IS_ERR(pmx) | |
939 | return PTR_ERR(pmx); | |
940 | pinmux_enable(pmx); | |
941 | ||
942 | state->pmx = pmx; | |
943 | } | |
944 | ||
945 | foo_remove() | |
946 | { | |
947 | pinmux_disable(state->pmx); | |
948 | pinmux_put(state->pmx); | |
949 | } | |
950 | ||
951 | If you want to grab a specific mux mapping and not just the first one found for | |
952 | this device you can specify a specific mapping name, for example in the above | |
953 | example the second i2c0 setting: pinmux_get(&device, "spi0-pos-B"); | |
954 | ||
955 | This get/enable/disable/put sequence can just as well be handled by bus drivers | |
956 | if you don't want each and every driver to handle it and you know the | |
957 | arrangement on your bus. | |
958 | ||
959 | The semantics of the get/enable respective disable/put is as follows: | |
960 | ||
961 | - pinmux_get() is called in process context to reserve the pins affected with | |
962 | a certain mapping and set up the pinmux core and the driver. It will allocate | |
963 | a struct from the kernel memory to hold the pinmux state. | |
964 | ||
965 | - pinmux_enable()/pinmux_disable() is quick and can be called from fastpath | |
966 | (irq context) when you quickly want to set up/tear down the hardware muxing | |
967 | when running a device driver. Usually it will just poke some values into a | |
968 | register. | |
969 | ||
970 | - pinmux_disable() is called in process context to tear down the pin requests | |
971 | and release the state holder struct for the mux setting. | |
972 | ||
973 | Usually the pinmux core handled the get/put pair and call out to the device | |
974 | drivers bookkeeping operations, like checking available functions and the | |
975 | associated pins, whereas the enable/disable pass on to the pin controller | |
976 | driver which takes care of activating and/or deactivating the mux setting by | |
977 | quickly poking some registers. | |
978 | ||
979 | The pins are allocated for your device when you issue the pinmux_get() call, | |
980 | after this you should be able to see this in the debugfs listing of all pins. | |
981 | ||
982 | ||
983 | System pinmux hogging | |
984 | ===================== | |
985 | ||
986 | A system pinmux map entry, i.e. a pinmux setting that does not have a device | |
987 | associated with it, can be hogged by the core when the pin controller is | |
988 | registered. This means that the core will attempt to call pinmux_get() and | |
989 | pinmux_enable() on it immediately after the pin control device has been | |
990 | registered. | |
991 | ||
992 | This is enabled by simply setting the .hog_on_boot field in the map to true, | |
993 | like this: | |
994 | ||
995 | { | |
f54367f9 | 996 | .name = "POWERMAP" |
51cd24ee | 997 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af LW |
998 | .function = "power_func", |
999 | .hog_on_boot = true, | |
1000 | }, | |
1001 | ||
1002 | Since it may be common to request the core to hog a few always-applicable | |
1003 | mux settings on the primary pin controller, there is a convenience macro for | |
1004 | this: | |
1005 | ||
1006 | PINMUX_MAP_PRIMARY_SYS_HOG("POWERMAP", "power_func") | |
1007 | ||
1008 | This gives the exact same result as the above construction. | |
1009 | ||
1010 | ||
1011 | Runtime pinmuxing | |
1012 | ================= | |
1013 | ||
1014 | It is possible to mux a certain function in and out at runtime, say to move | |
1015 | an SPI port from one set of pins to another set of pins. Say for example for | |
1016 | spi0 in the example above, we expose two different groups of pins for the same | |
1017 | function, but with different named in the mapping as described under | |
1018 | "Advanced mapping" above. So we have two mappings named "spi0-pos-A" and | |
1019 | "spi0-pos-B". | |
1020 | ||
1021 | This snippet first muxes the function in the pins defined by group A, enables | |
1022 | it, disables and releases it, and muxes it in on the pins defined by group B: | |
1023 | ||
28a8d14c LW |
1024 | #include <linux/pinctrl/consumer.h> |
1025 | ||
2744e8af LW |
1026 | foo_switch() |
1027 | { | |
de849eec | 1028 | struct pinmux *pmx; |
2744e8af LW |
1029 | |
1030 | /* Enable on position A */ | |
1031 | pmx = pinmux_get(&device, "spi0-pos-A"); | |
1032 | if IS_ERR(pmx) | |
1033 | return PTR_ERR(pmx); | |
1034 | pinmux_enable(pmx); | |
1035 | ||
1036 | /* This releases the pins again */ | |
1037 | pinmux_disable(pmx); | |
1038 | pinmux_put(pmx); | |
1039 | ||
1040 | /* Enable on position B */ | |
1041 | pmx = pinmux_get(&device, "spi0-pos-B"); | |
1042 | if IS_ERR(pmx) | |
1043 | return PTR_ERR(pmx); | |
1044 | pinmux_enable(pmx); | |
1045 | ... | |
1046 | } | |
1047 | ||
1048 | The above has to be done from process context. |