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f1a0c4aa CM |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | #ifndef __ASM_CACHE_H | |
17 | #define __ASM_CACHE_H | |
18 | ||
02f7760e WD |
19 | #include <asm/cputype.h> |
20 | ||
21 | #define CTR_L1IP_SHIFT 14 | |
22 | #define CTR_L1IP_MASK 3 | |
469c89aa SP |
23 | #define CTR_DMINLINE_SHIFT 16 |
24 | #define CTR_IMINLINE_SHIFT 0 | |
02f7760e WD |
25 | #define CTR_CWG_SHIFT 24 |
26 | #define CTR_CWG_MASK 15 | |
27 | ||
469c89aa SP |
28 | #define CTR_CACHE_MINLINE_MASK \ |
29 | (0xf << CTR_DMINLINE_SHIFT | 0xf << CTR_IMINLINE_SHIFT) | |
30 | ||
02f7760e WD |
31 | #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) |
32 | ||
dda288d7 | 33 | #define ICACHE_POLICY_VPIPT 0 |
02f7760e WD |
34 | #define ICACHE_POLICY_VIPT 2 |
35 | #define ICACHE_POLICY_PIPT 3 | |
a41dc0e8 | 36 | |
97303480 | 37 | #define L1_CACHE_SHIFT 7 |
f1a0c4aa CM |
38 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
39 | ||
40 | /* | |
41 | * Memory returned by kmalloc() may be used for DMA, so we must make | |
42 | * sure that all such allocations are cache aligned. Otherwise, | |
43 | * unrelated code may cause parts of the buffer to be read into the | |
44 | * cache before the transfer is done, causing old data to be seen by | |
45 | * the CPU. | |
46 | */ | |
47 | #define ARCH_DMA_MINALIGN L1_CACHE_BYTES | |
a41dc0e8 CM |
48 | |
49 | #ifndef __ASSEMBLY__ | |
50 | ||
02f7760e WD |
51 | #include <linux/bitops.h> |
52 | ||
53 | #define ICACHEF_ALIASING 0 | |
dda288d7 | 54 | #define ICACHEF_VPIPT 1 |
02f7760e WD |
55 | extern unsigned long __icache_flags; |
56 | ||
57 | /* | |
58 | * Whilst the D-side always behaves as PIPT on AArch64, aliasing is | |
59 | * permitted in the I-cache. | |
60 | */ | |
61 | static inline int icache_is_aliasing(void) | |
62 | { | |
63 | return test_bit(ICACHEF_ALIASING, &__icache_flags); | |
64 | } | |
65 | ||
dda288d7 WD |
66 | static inline int icache_is_vpipt(void) |
67 | { | |
68 | return test_bit(ICACHEF_VPIPT, &__icache_flags); | |
69 | } | |
70 | ||
02f7760e WD |
71 | static inline u32 cache_type_cwg(void) |
72 | { | |
73 | return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; | |
74 | } | |
75 | ||
e4f88d83 JL |
76 | #define __read_mostly __attribute__((__section__(".data..read_mostly"))) |
77 | ||
a41dc0e8 CM |
78 | static inline int cache_line_size(void) |
79 | { | |
80 | u32 cwg = cache_type_cwg(); | |
81 | return cwg ? 4 << cwg : L1_CACHE_BYTES; | |
82 | } | |
83 | ||
84 | #endif /* __ASSEMBLY__ */ | |
f1a0c4aa CM |
85 | |
86 | #endif |