projects / GitHub / exynos8895 / android_kernel_samsung_universal8895.git / blame
| Commit | Line | Data |
|---|---|---|
| 1cac41cb MB |
1 | /* |
| 2 | * MFC_charger.h | |
| 3 | * Samsung MFC Charger Header | |
| 4 | * | |
| 5 | * Copyright (C) 2015 Samsung Electronics, Inc. | |
| 6 | * | |
| 7 | * This software is licensed under the terms of the GNU General Public | |
| 8 | * License version 2, as published by the Free Software Foundation, and | |
| 9 | * may be copied, distributed, and modified under those terms. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | * GNU General Public License for more details. | |
| 15 | * | |
| 16 | */ | |
| 17 | ||
| 18 | #ifndef __MFC_CHARGER_H | |
| 19 | #define __MFC_CHARGER_H __FILE__ | |
| 20 | ||
| 21 | #include <linux/mfd/core.h> | |
| 22 | #include <linux/regulator/machine.h> | |
| 23 | #include <linux/i2c.h> | |
| 24 | #include "../sec_charging_common.h" | |
| 25 | ||
| 26 | #define MFC_FW_BIN_VERSION 0x58 | |
| 27 | #define MFC_FW_BIN_FULL_VERSION 0x00580001 | |
| 28 | #define MFC_FW_BIN_VERSION_ADDR 0x14a8 //fw rev58 address | |
| 29 | #define FW_ADDRES_MAX 7 | |
| 30 | ||
| 31 | /* REGISTER MAPS */ | |
| 32 | #define MFC_CHIP_ID_L_REG 0x00 | |
| 33 | #define MFC_CHIP_ID_H_REG 0x01 | |
| 34 | #define MFC_CHIP_REVISION_REG 0x02 | |
| 35 | #define MFC_CUSTOMER_ID_REG 0x03 | |
| 36 | #define MFC_FW_MAJOR_REV_L_REG 0x04 | |
| 37 | #define MFC_FW_MAJOR_REV_H_REG 0x05 | |
| 38 | #define MFC_FW_MINOR_REV_L_REG 0x06 | |
| 39 | #define MFC_FW_MINOR_REV_H_REG 0x07 | |
| 40 | #define MFC_PRMC_ID_L_REG 0x0A | |
| 41 | #define MFC_PRMC_ID_H_REG 0x0B | |
| 42 | /* RXID BIT[0:47] */ | |
| 43 | #define MFC_WPC_RXID_0_REG 0x10 | |
| 44 | #define MFC_WPC_RXID_1_REG 0x11 | |
| 45 | #define MFC_WPC_RXID_2_REG 0x12 | |
| 46 | #define MFC_WPC_RXID_3_REGs 0x13 | |
| 47 | #define MFC_WPC_RXID_4_REG 0x14 | |
| 48 | #define MFC_WPC_RXID_5_REG 0x15 | |
| 49 | ||
| 50 | #define MFC_STATUS_L_REG 0x20 | |
| 51 | #define MFC_STATUS_H_REG 0x21 | |
| 52 | #define MFC_INT_A_L_REG 0x22 | |
| 53 | #define MFC_INT_A_H_REG 0x23 | |
| 54 | #define MFC_INT_A_ENABLE_L_REG 0x24 | |
| 55 | #define MFC_INT_A_ENABLE_H_REG 0x25 | |
| 56 | #define MFC_INT_A_CLEAR_L_REG 0x26 | |
| 57 | #define MFC_INT_A_CLEAR_H_REG 0x27 | |
| 58 | #define MFC_INT_B_REG 0x28 | |
| 59 | #define MFC_INT_B_ENABLE_REG 0x29 | |
| 60 | #define MFC_INT_B_CLEAR_REG 0x2A | |
| 61 | ||
| 62 | #define MFC_SYS_OP_MODE_REG 0x2B | |
| 63 | #define MFC_BATTERY_CHG_STATUS_REG 0x3A | |
| 64 | /* EPT(End of Power Transfer) cases. PMA has only EOC case */ | |
| 65 | #define MFC_EPT_REG 0x3B | |
| 66 | #define MFC_ADC_VOUT_L_REG 0x3C | |
| 67 | #define MFC_ADC_VOUT_H_REG 0x3D | |
| 68 | #define MFC_VOUT_SET_REG 0x3E | |
| 69 | #define MFC_VRECT_ADJ_REG 0x3F | |
| 70 | #define MFC_ADC_VRECT_L_REG 0x40 | |
| 71 | #define MFC_ADC_VRECT_H_REG 0x41 | |
| 72 | #define MFC_ADC_TX_ISENSE_L_REG 0x42 | |
| 73 | #define MFC_ADC_TX_ISENSE_H_REG 0x43 | |
| 74 | #define MFC_ADC_RX_IOUT_L_REG 0x44 | |
| 75 | #define MFC_ADC_RX_IOUT_H_REG 0x45 | |
| 76 | #define MFC_ADC_DIE_TEMP_L_REG 0x46 /* 8 LSB field is used, Celsius */ | |
| 77 | #define MFC_ADC_DIE_TEMP_H_REG 0x47 /* only 4 MSB[3:0] field is used, Celsius */ | |
| 78 | #define MFC_RX_OP_FREQ_L_REG 0x48 /* kHZ */ | |
| 79 | #define MFC_RX_OP_FREQ_H_REG 0x49 /* kHZ */ | |
| 80 | #define MFC_RX_PING_FREQ_L_REG 0x4A /* kHZ */ | |
| 81 | #define MFC_RX_PING_FREQ_H_REG 0x4B /* kHZ */ | |
| 82 | /* ILim = value * 0.1(A) + 0.1(A) */ | |
| 83 | #define MFC_ILIM_SET_REG 0x4C | |
| 84 | /* Target Vrect is ReadOnly register, and updated by every 10ms | |
| 85 | Its default value is 0x1A90(6800mV). | |
| 86 | Target_Vrect (Iout,Vout) = {Vout + 0.05} + { Vrect(Iout,5V)-Vrect(1A,5V) } * 5/9 | |
| 87 | */ | |
| 88 | #define MFC_TARGET_VRECT_L_REG 0x015B /* default 0x90 */ | |
| 89 | #define MFC_TARGET_VRECT_H_REG 0x015C /* default 0x1A */ | |
| 90 | ||
| 91 | #define MFC_AP2MFC_CMD_L_REG 0x4E | |
| 92 | #define MFC_AP2MFC_CMD_H_REG 0x4F | |
| 93 | #define MFC_BT2MFC_CMD_REG 0xA0 | |
| 94 | ||
| 95 | #define MFC_WPC_PCKT_HEADER_REG 0x50 | |
| 96 | #define MFC_WPC_RX_DATA_COM_REG 0x51 /* WPC Rx to Tx COMMAND */ | |
| 97 | #define MFC_WPC_RX_DATA_VALUE0_REG 0x52 | |
| 98 | #define MFC_WPC_RX_DATA_VALUE1_REG 0x53 | |
| 99 | #define MFC_WPC_RX_DATA_VALUE2_REG 0x54 | |
| 100 | #define MFC_WPC_RX_DATA_VALUE3_REG 0x55 | |
| 101 | #define MFC_PMA_RX_ADVT_CS_REG 0x56 /* PMA Advertisement Reg, 4MSB[3:0] Checksum */ | |
| 102 | #define MFC_PMA_RX_ADVT_MSG_REG 0x57 /* PMA Advertisement Reg, Message */ | |
| 103 | ||
| 104 | #define MFC_WPC_TX_DATA_COM_REG 0x58 | |
| 105 | #define MFC_WPC_TX_DATA_VALUE0_REG 0x59 | |
| 106 | #define MFC_WPC_TX_DATA_VALUE1_REG 0x5A | |
| 107 | ||
| 108 | /* AP2BT DATA VALUE[24:0] */ | |
| 109 | #define MFC_AP2BT_DATA_COM_REG 0xA1 | |
| 110 | #define MFC_AP2BT_DATA_VALUE0_REG 0xA2 | |
| 111 | #define MFC_AP2BT_DATA_VALUE1_REG 0xA3 | |
| 112 | #define MFC_AP2BT_DATA_VALUE2_REG 0xA4 | |
| 113 | #define MFC_AP2BT_DATA_VALUE3_REG 0xA5 | |
| 114 | /* BT2AP DATA VALUE[24:0] */ | |
| 115 | #define MFC_BT2AP_DATA_COM_REG 0xA6 | |
| 116 | #define MFC_BT2AP_DATA_VALUE0_REG 0xA7 | |
| 117 | #define MFC_BT2AP_DATA_VALUE1_REG 0xA8 | |
| 118 | #define MFC_BT2AP_DATA_VALUE2_REG 0xA9 | |
| 119 | #define MFC_BT2AP_DATA_VALUE3_REG 0xAA | |
| 120 | /* TX Max Operating Frequency = 60 MHz/value, default is 148kHz (60MHz/0x195=148) */ | |
| 121 | #define MFC_TX_MAX_OP_FREQ_L_REG 0x60 /* default 0x95 */ | |
| 122 | #define MFC_TX_MAX_OP_FREQ_H_REG 0x61 /* default 0x01 */ | |
| 123 | /* TX Max Operating Frequency = 60 MHz/value, default is 80kHz (60MHz/0x2EE=80) */ | |
| 124 | #define MFC_TX_MIN_OP_FREQ_L_REG 0x62 /* default 0xEE */ | |
| 125 | #define MFC_TX_MIN_OP_FREQ_H_REG 0x63 /* default 0x02 */ | |
| 126 | /* TX Digital Ping Frequency = 60 MHz/value, default is 90kHz (60MHz/0x29B=90) */ | |
| 127 | #define MFC_TX_PING_FREQ_L_REG 0x64 /* default 0x9B */ | |
| 128 | #define MFC_TX_PING_FREQ_H_REG 0x65 /* default 0x02 */ | |
| 129 | /* TX Digital Ping Duty-Cycle, 5%(0x05) ~ 50%(0x32) */ | |
| 130 | #define MFC_TX_PING_DUTY_CYCLE_REG 0x66 /* default 0x32 */ | |
| 131 | #define MFC_TX_INVERTER_CTRL_REG 0x67 | |
| 132 | /* RX Mode Communication Modulation FET Ctrl */ | |
| 133 | #define MFC_RX_CMFET_CTRL_REG 0x68 | |
| 134 | #define MFC_MST_MODE_SEL_REG 0x69 | |
| 135 | #define MFC_RX_OV_CLAMP_REG 0x6A | |
| 136 | #define MFC_RX_COMM_MOD_FET_REG 0x6B | |
| 137 | ||
| 138 | #define MFC_WPC_FOD_0A_REG 0x70 | |
| 139 | #define MFC_WPC_FOD_0B_REG 0x71 | |
| 140 | #define MFC_WPC_FOD_1A_REG 0x72 | |
| 141 | #define MFC_WPC_FOD_1B_REG 0x73 | |
| 142 | #define MFC_WPC_FOD_2A_REG 0x74 | |
| 143 | #define MFC_WPC_FOD_2B_REG 0x75 | |
| 144 | #define MFC_WPC_FOD_3A_REG 0x76 | |
| 145 | #define MFC_WPC_FOD_3B_REG 0x77 | |
| 146 | #define MFC_WPC_FOD_4A_REG 0x78 | |
| 147 | #define MFC_WPC_FOD_4B_REG 0x79 | |
| 148 | #define MFC_WPC_FOD_5A_REG 0x7A | |
| 149 | #define MFC_WPC_FOD_5B_REG 0x7B | |
| 150 | ||
| 151 | #define MFC_PMA_FOD_0A_REG 0x80 | |
| 152 | #define MFC_PMA_FOD_0B_REG 0x81 | |
| 153 | #define MFC_PMA_FOD_1A_REG 0x82 | |
| 154 | #define MFC_PMA_FOD_1B_REG 0x83 | |
| 155 | #define MFC_PMA_FOD_2A_REG 0x84 | |
| 156 | #define MFC_PMA_FOD_2B_REG 0x85 | |
| 157 | #define MFC_PMA_FOD_3A_REG 0x86 | |
| 158 | #define MFC_PMA_FOD_3B_REG 0x87 | |
| 159 | #define MFC_PMA_FOD_4A_REG 0x88 | |
| 160 | #define MFC_PMA_FOD_4B_REG 0x89 | |
| 161 | #define MFC_PMA_FOD_5A_REG 0x8A | |
| 162 | #define MFC_PMA_FOD_5B_REG 0x8B | |
| 163 | ||
| 164 | #define MFC_A4WP_FOD_0A_REG 0x0 | |
| 165 | #define MFC_A4WP_FOD_0B_REG 0x91 | |
| 166 | #define MFC_A4WP_FOD_1A_REG 0x92 | |
| 167 | #define MFC_A4WP_FOD_1B_REG 0x93 | |
| 168 | #define MFC_A4WP_FOD_2A_REG 0x94 | |
| 169 | #define MFC_A4WP_FOD_2B_REG 0x95 | |
| 170 | #define MFC_A4WP_FOD_3A_REG 0x96 | |
| 171 | #define MFC_A4WP_FOD_3B_REG 0x97 | |
| 172 | #define MFC_A4WP_FOD_4A_REG 0x98 | |
| 173 | #define MFC_A4WP_FOD_4B_REG 0x99 | |
| 174 | #define MFC_A4WP_FOD_5A_REG 0x9A | |
| 175 | #define MFC_A4WP_FOD_5B_REG 0x9B | |
| 176 | ||
| 177 | #define MFC_FW_DATA_CODE_0 0xB0 | |
| 178 | #define MFC_FW_DATA_CODE_1 0xB1 | |
| 179 | #define MFC_FW_DATA_CODE_2 0xB2 | |
| 180 | #define MFC_FW_DATA_CODE_3 0xB3 | |
| 181 | #define MFC_FW_DATA_CODE_4 0xB4 | |
| 182 | #define MFC_FW_DATA_CODE_5 0xB5 | |
| 183 | #define MFC_FW_DATA_CODE_6 0xB6 | |
| 184 | #define MFC_FW_DATA_CODE_7 0xB7 | |
| 185 | #define MFC_FW_DATA_CODE_8 0xB8 | |
| 186 | #define MFC_FW_DATA_CODE_9 0xB9 | |
| 187 | #define MFC_FW_DATA_CODE_A 0xBA | |
| 188 | /* Timer code contains ASCII value. (ex. 31 means '1', 3A means ':') */ | |
| 189 | #define MFC_FW_TIMER_CODE_0 0xC0 | |
| 190 | #define MFC_FW_TIMER_CODE_1 0xC1 | |
| 191 | #define MFC_FW_TIMER_CODE_2 0xC2 | |
| 192 | #define MFC_FW_TIMER_CODE_3 0xC3 | |
| 193 | #define MFC_FW_TIMER_CODE_4 0xC4 | |
| 194 | #define MFC_FW_TIMER_CODE_5 0xC5 | |
| 195 | #define MFC_FW_TIMER_CODE_6 0xC6 | |
| 196 | #define MFC_FW_TIMER_CODE_7 0xC7 | |
| 197 | #define MFC_RPP_SCALE_COEF_REG 0xF0 | |
| 198 | enum { | |
| 199 | MFC_PAD_NONE = 0, | |
| 200 | MFC_PAD_WPC, /* 1 */ | |
| 201 | MFC_PAD_WPC_AFC, /* 2 */ | |
| 202 | MFC_PAD_WPC_PACK, /* 3 */ | |
| 203 | MFC_PAD_WPC_PACK_HV, /* 4 */ | |
| 204 | MFC_PAD_WPC_STAND, /* 5 */ | |
| 205 | MFC_PAD_WPC_STAND_HV, /* 6 */ | |
| 206 | MFC_PAD_PMA, /* 7 */ | |
| 207 | MFC_PAD_WPC_VEHICLE, /* 8 */ | |
| 208 | MFC_PAD_WPC_VEHICLE_HV, /* 9 */ | |
| 209 | MFC_PAD_PREPARE_HV, /* 10 */ | |
| 210 | MFC_PAD_A4WP, /* 11 */ | |
| 211 | MFC_PAD_TX, /* 12 */ | |
| 212 | }; | |
| 213 | ||
| 214 | #define MFC_VOUT_CFG_STEP 7 | |
| 215 | static const u8 mfc_idt_vout_val[] = { | |
| 216 | 0x0F, 0x19, 0x23, 0x2D, 0x37, 0x41, 0x14, | |
| 217 | }; | |
| 218 | static const u8 mfc_lsi_vout_val[] = { | |
| 219 | 0x72, 0x78, 0x8C, 0xA0, 0xC8, 0xC8, 0x6E, | |
| 220 | }; | |
| 221 | ||
| 222 | enum { | |
| 223 | MFC_VOUT_5V = 0, /* CC CALL, CV CALL */ | |
| 224 | MFC_VOUT_6V, // 1 | |
| 225 | MFC_VOUT_7V, // 2 | |
| 226 | MFC_VOUT_8V, // 3 | |
| 227 | MFC_VOUT_9V, // 4 | |
| 228 | MFC_VOUT_10V, // 5 | |
| 229 | MFC_VOUT_5_5V, /* CC-CV */ | |
| 230 | }; | |
| 231 | ||
| 232 | /* System Operating Mode Register, Sys_Op_Mode (0x2B) */ | |
| 233 | #define PAD_MODE_MISSING 0 | |
| 234 | #define PAD_MODE_WPC_BASIC 1 | |
| 235 | #define PAD_MODE_WPC_ADV 2 | |
| 236 | #define PAD_MODE_PMA_SR1 3 | |
| 237 | #define PAD_MODE_PMA_SR1E 4 | |
| 238 | #define PAD_MODE_A4WP 5 | |
| 239 | #define PAD_MODE_A4WP_LPM 6 | |
| 240 | #define PAD_MODE_UNKNOWN 7 | |
| 241 | ||
| 242 | /* MFC_WPC_DATA_COM_REG (0x51) : RX Command */ | |
| 243 | #define WPC_COM_UNKNOWN 0x00 | |
| 244 | #define WPC_COM_TX_ID 0x01 | |
| 245 | #define WPC_COM_CHG_STATUS 0x05 | |
| 246 | #define WPC_COM_AFC_SET 0x06 | |
| 247 | #define WPC_COM_AFC_DEBOUNCE 0x07 /* Data Values [ 0~1000mV : 0x0000~0x03E8 ], 2 bytes*/ | |
| 248 | #define WPC_COM_SID_TAG 0x08 | |
| 249 | #define WPC_COM_SID_TOKEN 0x09 | |
| 250 | #define WPC_COM_TX_STANDBY 0x0A | |
| 251 | #define WPC_COM_LED_CONTROL 0x0B /* Data Value LED Enable(0x00), LED Disable(0xFF) */ | |
| 252 | #define WPC_COM_REQ_AFC_TX 0x0C /* Data Value (0x00) */ | |
| 253 | #define WPC_COM_COOLING_CTRL 0x0D /* Data Value ON(0x00), OFF(0xFF) */ | |
| 254 | #define WPC_COM_CHG_LEVEL 0x0F /* Battery level */ | |
| 255 | #define WPC_COM_ENTER_PHM 0x18 /* GEAR entered PHM */ | |
| 256 | ||
| 257 | /* MFC_TX_DATA_COM_REG (0x58) : TX Command */ | |
| 258 | #define WPC_TX_COM_UNKNOWN 0x00 | |
| 259 | #define WPC_TX_COM_TX_ID 0x01 | |
| 260 | #define WPC_TX_COM_AFC_SET 0x02 | |
| 261 | #define WPC_TX_COM_ACK 0x03 | |
| 262 | #define WPC_TX_COM_NAK 0x04 | |
| 263 | #define WPC_TX_COM_CHG_ERR 0x05 | |
| 264 | #define WPC_TX_COM_WPS 0x07 | |
| 265 | ||
| 266 | #define TX_AFC_SET_5V 0x00 | |
| 267 | #define TX_AFC_SET_10V 0x01 | |
| 268 | #define TX_AFC_SET_12V 0x02 | |
| 269 | #define TX_AFC_SET_18V 0x03 | |
| 270 | #define TX_AFC_SET_19V 0x04 | |
| 271 | #define TX_AFC_SET_20V 0x05 | |
| 272 | #define TX_AFC_SET_24V 0x06 | |
| 273 | ||
| 274 | #define TX_ID_UNKNOWN 0x00 | |
| 275 | #define TX_ID_SNGL_PORT_START 0x01 | |
| 276 | #define TX_ID_VEHICLE_PAD 0x11 | |
| 277 | #define TX_ID_SNGL_PORT_END 0x1F | |
| 278 | #define TX_ID_MULTI_PORT_START 0x20 | |
| 279 | #define TX_ID_MULTI_PORT_END 0x2F | |
| 280 | #define TX_ID_STAND_TYPE_START 0x30 | |
| 281 | #define TX_ID_STAND_TYPE_END 0x3F | |
| 282 | #define TX_ID_BATT_PACK_TA 0x41 /* 0x40 ~ 0x41 is N/C*/ | |
| 283 | #define TX_ID_BATT_PACK 0x42 | |
| 284 | #define TX_ID_BATT_PACK_END 0x4F /* reserved 0x40 ~ 0x4F for wireless battery pack */ | |
| 285 | #define TX_ID_DREAM_STAND 0x31 | |
| 286 | #define TX_ID_DREAM_DOWN 0x14 | |
| 287 | #define TX_ID_UNO_TX 0x72 | |
| 288 | #define TX_ID_UNO_TX_B0 0x80 | |
| 289 | #define TX_ID_UNO_TX_B1 0x81 | |
| 290 | #define TX_ID_UNO_TX_B2 0x82 | |
| 291 | #define TX_ID_UNO_TX_MAX 0x9F | |
| 292 | ||
| 293 | #define TX_CHG_ERR_OTP 0x12 | |
| 294 | #define TX_CHG_ERR_OCP 0x13 | |
| 295 | #define TX_CHG_ERR_DARKZONE 0x14 | |
| 296 | #define TX_CHG_ERR_FOD 0x20 ... 0x27 | |
| 297 | ||
| 298 | /* value of WPC_TX_COM_WPS (0x07) */ | |
| 299 | #define WPS_AICL_RESET 0x01 | |
| 300 | ||
| 301 | #define WPC_COM_AFC_DEBOUNCE 0x07 /* Data Values [ 0~1000mV : 0x0000~0x03E8 ], 2 bytes*/ | |
| 302 | ||
| 303 | /* MFC_AP2BT_DATA_COM_REG (0xA1) : Command */ | |
| 304 | #define AP2BT_COM_UNKNOWN 0x00 | |
| 305 | #define AP2BT_COM_TX_ID 0x01 | |
| 306 | #define AP2BT_COM_CHG_STATUS 0x05 | |
| 307 | #define AP2BT_COM_AFC_MODE 0x06 | |
| 308 | #define AP2BT_COM_VRECT_OFFSET 0x07 /* Data Values [ 0~1000mV : 0x0000~0x03E8 ], 2 bytes*/ | |
| 309 | #define AP2BT_COM_SID_TAG 0x08 | |
| 310 | #define AP2BT_COM_SID_TOKEN 0x09 | |
| 311 | #define AP2BT_COM_TX_STANDBY 0x0A | |
| 312 | #define AP2BT_COM_LED_CONTROL 0x0B /* Data Value LED Enable(0x00), LED Disable(0xFF) */ | |
| 313 | #define AP2BT_COM_REQ_AFC_TX 0x0C /* Data Value (0x00) */ | |
| 314 | #define AP2BT_COM_COOLING_CTRL 0x0D /* Data Value ON(0x00), OFF(0xFF) */ | |
| 315 | ||
| 316 | /* MFC_BT2AP_DATA_COM_REG (0xA6) : Command */ | |
| 317 | #define BT2AP_COM_UNKNOWN 0x00 | |
| 318 | #define BT2AP_COM_TX_ID 0x01 | |
| 319 | #define BT2AP_COM_CHG_STATUS 0x05 | |
| 320 | #define BT2AP_COM_AFC_MODE 0x06 | |
| 321 | #define BT2AP_COM_PWR_STATUS 0x07 | |
| 322 | #define BT2AP_COM_SID_TAG 0x08 | |
| 323 | #define BT2AP_COM_SID_TOKEN 0x09 | |
| 324 | #define BT2AP_COM_TX_STANDBY 0x0A | |
| 325 | #define BT2AP_COM_LED_CONTROL 0x0B /* Data Value LED Enable(0x00), LED Disable(0xFF) */ | |
| 326 | #define BT2AP_COM_REQ_AFC_TX 0x0C /* Data Value (0x00) */ | |
| 327 | #define BT2AP_COM_COOLING_CTRL 0x0D /* Data Value ON(0x00), OFF(0xFF) */ | |
| 328 | ||
| 329 | #define MFC_NUM_FOD_REG 12 | |
| 330 | ||
| 331 | /* Command Register, COM_L(0x4E) */ | |
| 332 | #define MFC_CMD_AP2BT_DATA_SHIFT 7 | |
| 333 | #define MFC_CMD_INT_LPM_SHIFT 6 /* set this bit to 0, then INT_LPM LOW, set this bit to 1, then INT_LPM HIGH */ | |
| 334 | #define MFC_CMD_CLEAR_INT_SHIFT 5 | |
| 335 | #define MFC_CMD_SEND_CHG_STS_SHIFT 4 | |
| 336 | #define MFC_CMD_SEND_EOP_SHIFT 3 | |
| 337 | #define MFC_CMD_MCU_RESET_SHIFT 2 | |
| 338 | #define MFC_CMD_TOGGLE_LDO_SHIFT 1 | |
| 339 | #define MFC_CMD_SEND_RX_DATA_SHIFT 0 | |
| 340 | #define MFC_CMD_AP2BT_DATA_MASK (1 << MFC_CMD_AP2BT_DATA_SHIFT) | |
| 341 | #define MFC_CMD_INT_LPM_MASK (1 << MFC_CMD_INT_LPM_SHIFT) | |
| 342 | #define MFC_CMD_CLEAR_INT_MASK (1 << MFC_CMD_CLEAR_INT_SHIFT) | |
| 343 | #define MFC_CMD_SEND_CHG_STS_MASK (1 << MFC_CMD_SEND_CHG_STS_SHIFT) /* MFC MCU sends ChgStatus packet to TX */ | |
| 344 | #define MFC_CMD_SEND_EOP_MASK (1 << MFC_CMD_SEND_EOP_SHIFT) | |
| 345 | #define MFC_CMD_MCU_RESET_MASK (1 << MFC_CMD_MCU_RESET_SHIFT) | |
| 346 | #define MFC_CMD_TOGGLE_LDO_MASK (1 << MFC_CMD_TOGGLE_LDO_SHIFT) | |
| 347 | #define MFC_CMD_SEND_RX_DATA_MASK (1 << MFC_CMD_SEND_RX_DATA_SHIFT) | |
| 348 | ||
| 349 | /* Command Register, COM_H(0x4F) */ | |
| 350 | #define MFC_CMD2_WP_ON_SHIFT 0 | |
| 351 | #define MFC_CMD2_WP_ON_MASK (1 << MFC_CMD2_WP_ON_SHIFT) | |
| 352 | ||
| 353 | /* Chip Revision and Font Register, Chip_Rev (0x02) */ | |
| 354 | #define MFC_CHIP_REVISION_MASK 0xf0 | |
| 355 | #define MFC_CHIP_FONT_MASK 0x0f | |
| 356 | ||
| 357 | /* Status Registers, Status_L (0x20), Status_H (0x21) */ | |
| 358 | #define MFC_STAT_L_STAT_VOUT_SHIFT 7 | |
| 359 | #define MFC_STAT_L_STAT_VRECT_SHIFT 6 | |
| 360 | #define MFC_STAT_L_OP_MODE_SHIFT 5 | |
| 361 | #define MFC_STAT_L_OVER_VOL_SHIFT 4 | |
| 362 | #define MFC_STAT_L_OVER_CURR_SHIFT 3 | |
| 363 | #define MFC_STAT_L_OVER_TEMP_SHIFT 2 | |
| 364 | #define MFC_STAT_L_INT_LPM_SHIFT 1 | |
| 365 | #define MFC_STAT_L_BT2AP_DATA_SHIFT 0 | |
| 366 | ||
| 367 | #define MFC_STAT_L_STAT_VOUT_MASK (1 << MFC_STAT_L_STAT_VOUT_SHIFT) | |
| 368 | #define MFC_STAT_L_STAT_VRECT_MASK (1 << MFC_STAT_L_STAT_VRECT_SHIFT) | |
| 369 | #define MFC_STAT_L_OP_MODE_MASK (1 << MFC_STAT_L_OP_MODE_SHIFT) | |
| 370 | #define MFC_STAT_L_OVER_VOL_MASK (1 << MFC_STAT_L_OVER_VOL_SHIFT) | |
| 371 | #define MFC_STAT_L_OVER_CURR_MASK (1 << MFC_STAT_L_OVER_CURR_SHIFT) | |
| 372 | #define MFC_STAT_L_OVER_TEMP_MASK (1 << MFC_STAT_L_OVER_TEMP_SHIFT) | |
| 373 | #define MFC_STAT_L_INT_LPM_MASK (1 << MFC_STAT_L_INT_LPM_SHIFT) | |
| 374 | #define MFC_STAT_L_BT2AP_DATA_MASK (1 << MFC_STAT_L_BT2AP_DATA_SHIFT) | |
| 375 | ||
| 376 | #define MFC_STAT_H_TX_DATA_RECEIVED_SHFIT 7 | |
| 377 | #define MFC_STAT_H_TX_OVER_CURR_SHIFT 6 | |
| 378 | #define MFC_STAT_H_TX_OVER_TEMP_SHIFT 5 | |
| 379 | #define MFC_STAT_H_TX_FOD_SHIFT 4 | |
| 380 | #define MFC_STAT_H_TX_CON_DISCON_SHIFT 3 | |
| 381 | #define MFC_STAT_H_AC_MISSING_DET_SHIFT 2 | |
| 382 | #define MFC_STAT_H_RESERVED1_SHIFT 1 | |
| 383 | #define MFC_STAT_H_RESERVED0_SHIFT 0 | |
| 384 | #define MFC_STAT_H_TX_DATA_RECEIVED_MASK (1 << MFC_STAT_H_TX_DATA_RECEIVED_SHFIT) | |
| 385 | #define MFC_STAT_H_TX_OVER_CURR_MASK (1 << MFC_STAT_H_TX_OVER_CURR_SHIFT) | |
| 386 | #define MFC_STAT_H_TX_OVER_TEMP_MASK (1 << MFC_STAT_H_TX_OVER_TEMP_SHIFT) | |
| 387 | #define MFC_STAT_H_TX_FOD_MASK (1 << MFC_STAT_H_TX_FOD_SHIFT) | |
| 388 | #define MFC_STAT_H_TX_CON_DISCON_MASK (1 << MFC_STAT_H_TX_CON_DISCON_SHIFT) | |
| 389 | #define MFC_STAT_H_AC_MISSING_DET_MASK (1 << MFC_STAT_H_AC_MISSING_DET_SHIFT) | |
| 390 | #define MFC_STAT_H_RESERVED1_MASK (1 << MFC_STAT_H_RESERVED1_SHIFT) | |
| 391 | #define MFC_STAT_H_RESERVED0_MASK (1 << MFC_STAT_H_RESERVED0_SHIFT) | |
| 392 | ||
| 393 | #define MFC_STAT_OVER_TEMP_SHIFT 7 | |
| 394 | #define MFC_STAT_TX_OVER_CURR_SHIFT 6 | |
| 395 | #define MFC_STAT_TX_OVER_TEMP_SHIFT 5 | |
| 396 | #define MFC_STAT_TX_FOD_SHIFT 4 | |
| 397 | #define MFC_STAT_TX_CONNECT_SHIFT 3 | |
| 398 | #define MFC_STAT_OVER_TEMP_MASK (1 << MFC_STAT_OVER_TEMP_SHIFT) | |
| 399 | #define MFC_STAT_TX_OVER_CURR_MASK (1 << MFC_STAT_TX_OVER_CURR_SHIFT) | |
| 400 | #define MFC_STAT_TX_OVER_TEMP_MASK (1 << MFC_STAT_TX_OVER_TEMP_SHIFT) | |
| 401 | #define MFC_STAT_TX_FOD_MASK (1 << MFC_STAT_TX_FOD_SHIFT) | |
| 402 | #define MFC_STAT_TX_CONNECT_MASK (1 << MFC_STAT_TX_CONNECT_SHIFT) | |
| 403 | ||
| 404 | /* Interrupt Registers, INT_L (0x36), INT_H (0x37) */ | |
| 405 | #define MFC_INT_STAT_VOUT MFC_STAT_VOUT_MASK | |
| 406 | #define MFC_INT_STAT_VRECT MFC_STAT_STAT_VRECT_MASK | |
| 407 | #define MFC_INT_MODE_CHANGE MFC_STAT_MODE_CHANGE_MASK | |
| 408 | #define MFC_INT_TX_DATA_RECEIVED MFC_STAT_TX_DATA_RECEIVED_MASK | |
| 409 | #define MFC_INT_OVER_VOLT MFC_STAT_OVER_VOL_MASK | |
| 410 | #define MFC_INT_OVER_CURR MFC_STAT_OVER_CURR_MASK | |
| 411 | ||
| 412 | #define MFC_INT_OVER_TEMP MFC_STAT_OVER_TEMP_MASK | |
| 413 | #define MFC_INT_TX_OVER_CURR MFC_STAT_TX_OVER_CURR_MASK | |
| 414 | #define MFC_INT_TX_OVER_TEMP MFC_STAT_TX_OVER_TEMP_MASK | |
| 415 | #define MFC_INT_TX_FOD MFC_STAT_TX_FOD_MASK | |
| 416 | #define MFC_INT_TX_CONNECT MFC_STAT_TX_CONNECT_MASK | |
| 417 | ||
| 418 | /* End of Power Transfer Register, EPT (0x3B) (RX only) */ | |
| 419 | #define MFC_WPC_EPT_UNKNOWN 0 | |
| 420 | #define MFC_WPC_EPT_END_OF_CHG 1 | |
| 421 | #define MFC_WPC_EPT_INT_FAULT 2 | |
| 422 | #define MFC_WPC_EPT_OVER_TEMP 3 | |
| 423 | #define MFC_WPC_EPT_OVER_VOL 4 | |
| 424 | #define MFC_WPC_EPT_OVER_CURR 5 | |
| 425 | #define MFC_WPC_EPT_BATT_FAIL 6 | |
| 426 | #define MFC_WPC_EPT_RECONFIG 7 | |
| 427 | #define MFC_WPC_EPT_NO_RESPONSE 8 | |
| 428 | ||
| 429 | /* Proprietary Packet Header Register, PPP_Header(0x50) */ | |
| 430 | #define MFC_HEADER_END_SIG_STRENGTH 0x01 | |
| 431 | #define MFC_HEADER_END_POWER_TRANSFER 0x02 | |
| 432 | #define MFC_HEADER_END_CTR_ERROR 0x03 | |
| 433 | #define MFC_HEADER_END_RECEIVED_POWER 0x04 | |
| 434 | #define MFC_HEADER_END_CHARGE_STATUS 0x05 | |
| 435 | #define MFC_HEADER_POWER_CTR_HOLD_OFF 0x06 | |
| 436 | #define MFC_HEADER_AFC_CONF 0x28 | |
| 437 | #define MFC_HEADER_CONFIGURATION 0x51 | |
| 438 | #define MFC_HEADER_IDENTIFICATION 0x71 | |
| 439 | #define MFC_HEADER_EXTENDED_IDENT 0x81 | |
| 440 | ||
| 441 | ||
| 442 | /* TX Data Command Register, TX Data_COM (0x58) */ | |
| 443 | #define MFC_TX_DATA_COM_UNKNOWN 0x00 | |
| 444 | #define MFC_TX_DATA_COM_TX_ID 0x01 | |
| 445 | #define MFC_TX_DATA_COM_AFC_TX 0x02 | |
| 446 | #define MFC_TX_DATA_COM_ACK 0x03 | |
| 447 | #define MFC_TX_DATA_COM_NAK 0x04 | |
| 448 | ||
| 449 | /* END POWER TRANSFER CODES IN WPC */ | |
| 450 | #define MFC_EPT_CODE_UNKOWN 0x00 | |
| 451 | #define MFC_EPT_CODE_CHARGE_COMPLETE 0x01 | |
| 452 | #define MFC_EPT_CODE_INTERNAL_FAULT 0x02 | |
| 453 | #define MFC_EPT_CODE_OVER_TEMPERATURE 0x03 | |
| 454 | #define MFC_EPT_CODE_OVER_VOLTAGE 0x04 | |
| 455 | #define MFC_EPT_CODE_OVER_CURRENT 0x05 | |
| 456 | #define MFC_EPT_CODE_BATTERY_FAILURE 0x06 | |
| 457 | #define MFC_EPT_CODE_RECONFIGURE 0x07 | |
| 458 | #define MFC_EPT_CODE_NO_RESPONSE 0x08 | |
| 459 | ||
| 460 | #define MFC_POWER_MODE_MASK (0x1 << 0) | |
| 461 | #define MFC_SEND_USER_PKT_DONE_MASK (0x1 << 7) | |
| 462 | #define MFC_SEND_USER_PKT_ERR_MASK (0x3 << 5) | |
| 463 | #define MFC_SEND_ALIGN_MASK (0x1 << 3) | |
| 464 | #define MFC_SEND_EPT_CC_MASK (0x1 << 0) | |
| 465 | #define MFC_SEND_EOC_MASK (0x1 << 0) | |
| 466 | ||
| 467 | #define MFC_PTK_ERR_NO_ERR 0x00 | |
| 468 | #define MFC_PTK_ERR_ERR 0x01 | |
| 469 | #define MFC_PTK_ERR_ILLEGAL_HD 0x02 | |
| 470 | #define MFC_PTK_ERR_NO_DEF 0x03 | |
| 471 | ||
| 472 | #define MFC_FW_RESULT_DOWNLOADING 2 | |
| 473 | #define MFC_FW_RESULT_PASS 1 | |
| 474 | #define MFC_FW_RESULT_FAIL 0 | |
| 475 | ||
| 476 | #define MFC_FLASH_FW_HEX_PATH "mfc/mfc_fw_flash.bin" | |
| 477 | #define MFC_FW_SDCARD_BIN_PATH "/sdcard/mfc_fw_flash.bin" | |
| 478 | ||
| 479 | enum { | |
| 480 | MFC_EVENT_IRQ = 0, | |
| 481 | MFC_IRQS_NR, | |
| 482 | }; | |
| 483 | ||
| 484 | #define MFC_CHIP_ID_MAJOR_1_REG 0x0070 | |
| 485 | #define MFC_CHIP_ID_MAJOR_0_REG 0x0074 | |
| 486 | #define MFC_CHIP_ID_MINOR_REG 0x0078 | |
| 487 | #define MFC_LDO_EN_REG 0x301c | |
| 488 | ||
| 489 | /* PAD Vout */ | |
| 490 | enum { | |
| 491 | PAD_VOUT_5V = 0, | |
| 492 | PAD_VOUT_9V, | |
| 493 | PAD_VOUT_10V, | |
| 494 | PAD_VOUT_12V, | |
| 495 | PAD_VOUT_18V, | |
| 496 | PAD_VOUT_19V, | |
| 497 | PAD_VOUT_20V, | |
| 498 | PAD_VOUT_24V, | |
| 499 | }; | |
| 500 | ||
| 501 | enum { | |
| 502 | MFC_ADC_VOUT = 0, | |
| 503 | MFC_ADC_VRECT, | |
| 504 | MFC_ADC_TX_ISENSE, | |
| 505 | MFC_ADC_RX_IOUT, | |
| 506 | MFC_ADC_DIE_TEMP, | |
| 507 | // MFC_ADC_ALLIGN_X, | |
| 508 | // MFC_ADC_ALLIGN_Y, | |
| 509 | MFC_ADC_OP_FRQ, | |
| 510 | MFC_ADC_PING_FRQ, | |
| 511 | }; | |
| 512 | ||
| 513 | enum { | |
| 514 | MFC_END_SIG_STRENGTH = 0, | |
| 515 | MFC_END_POWER_TRANSFER, /* 1 */ | |
| 516 | MFC_END_CTR_ERROR, /* 2 */ | |
| 517 | MFC_END_RECEIVED_POWER, /* 3 */ | |
| 518 | MFC_END_CHARGE_STATUS, /* 4 */ | |
| 519 | MFC_POWER_CTR_HOLD_OFF, /* 5 */ | |
| 520 | MFC_AFC_CONF_5V, /* 6 */ | |
| 521 | MFC_AFC_CONF_10V, /* 7 */ | |
| 522 | MFC_AFC_CONF_5V_TX, /* 8 */ | |
| 523 | MFC_AFC_CONF_10V_TX, /* 9 */ | |
| 524 | MFC_CONFIGURATION, /* 10 */ | |
| 525 | MFC_IDENTIFICATION, /* 11 */ | |
| 526 | MFC_EXTENDED_IDENT, /* 12 */ | |
| 527 | MFC_LED_CONTROL_ON, /* 13 */ | |
| 528 | MFC_LED_CONTROL_OFF, /* 14 */ | |
| 529 | MFC_FAN_CONTROL_ON, /* 15 */ | |
| 530 | MFC_FAN_CONTROL_OFF, /* 16 */ | |
| 531 | MFC_REQUEST_AFC_TX, /* 17 */ | |
| 532 | MFC_REQUEST_TX_ID, /* 18 */ | |
| 533 | MFC_PHM_ON, /* 19 */ | |
| 534 | }; | |
| 535 | ||
| 536 | enum mfc_irq_source { | |
| 537 | TOP_INT = 0, | |
| 538 | }; | |
| 539 | ||
| 540 | enum mfc_irq { | |
| 541 | MFC_IRQ_STAT_VOUT = 0, | |
| 542 | MFC_IRQ_STAT_VRECT, | |
| 543 | MFC_IRQ_MODE_CHANGE, | |
| 544 | MFC_IRQ_TX_DATA_RECEIVED, | |
| 545 | MFC_IRQ_OVER_VOLT, | |
| 546 | MFC_IRQ_OVER_CURR, | |
| 547 | MFC_IRQ_OVER_TEMP, | |
| 548 | MFC_IRQ_TX_OVER_CURR, | |
| 549 | MFC_IRQ_TX_OVER_TEMP, | |
| 550 | MFC_IRQ_TX_FOD, | |
| 551 | MFC_IRQ_TX_CONNECT, | |
| 552 | MFC_IRQ_NR, | |
| 553 | }; | |
| 554 | ||
| 555 | struct mfc_irq_data { | |
| 556 | int mask; | |
| 557 | enum mfc_irq_source group; | |
| 558 | }; | |
| 559 | ||
| 560 | enum mfc_firmware_mode { | |
| 561 | MFC_RX_FIRMWARE = 0, | |
| 562 | MFC_TX_FIRMWARE, | |
| 563 | }; | |
| 564 | ||
| 565 | enum mfc_ic_revision { | |
| 566 | MFC_IC_REVISION = 0, | |
| 567 | MFC_IC_FONT, | |
| 568 | }; | |
| 569 | ||
| 570 | enum mfc_chip_id { | |
| 571 | MFC_CHIP_IDT = 0, | |
| 572 | MFC_CHIP_LSI, | |
| 573 | }; | |
| 574 | ||
| 575 | enum mfc_headroom { | |
| 576 | MFC_HEADROOM_0 = 0, | |
| 577 | MFC_HEADROOM_1, /* 0.277V */ | |
| 578 | MFC_HEADROOM_2, /* 0.497V */ | |
| 579 | MFC_HEADROOM_3, /* 0.650V */ | |
| 580 | MFC_HEADROOM_4, /* 0.030V */ | |
| 581 | MFC_HEADROOM_5, /* 0.082V */ | |
| 582 | }; | |
| 583 | ||
| 584 | struct mfc_ppp_info { | |
| 585 | u8 header; | |
| 586 | u8 rx_data_com; | |
| 587 | u8 data_val[4]; | |
| 588 | int data_size; | |
| 589 | }; | |
| 590 | ||
| 591 | #define DECLARE_IRQ(idx, _group, _mask) \ | |
| 592 | [(idx)] = { .group = (_group), .mask = (_mask) } | |
| 593 | static const struct mfc_irq_data mfc_irqs[] = { | |
| 594 | DECLARE_IRQ(MFC_IRQ_STAT_VOUT, TOP_INT, 1 << 0), | |
| 595 | }; | |
| 596 | ||
| 597 | //this file is generated by hex2txtOTP9220.exe. DO NOT MODIFY UNLESS YOU KNOW WHAT YOU ARE DOING! | |
| 598 | static const u8 MTPBootloader9320[] = { | |
| 599 | 0x00, 0x04, 0x00, 0x20, 0xE3, 0x00, 0x00, 0x00, 0x41, 0x00, 0x00, 0x00, 0x41, 0x00, 0x00, 0x00, | |
| 600 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
| 601 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x00, 0x00, 0x00, | |
| 602 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
| 603 | 0xFE, 0xE7, 0x00, 0x00, 0xF0, 0xB5, 0x45, 0x49, 0x00, 0x20, 0x0A, 0x88, 0x05, 0x46, 0x93, 0x06, | |
| 604 | 0x00, 0xD5, 0x04, 0x20, 0xD2, 0x06, 0x07, 0xD5, 0x8A, 0x78, 0x0B, 0x79, 0x1A, 0x43, 0x92, 0x07, | |
| 605 | 0x02, 0xD1, 0x20, 0x22, 0x10, 0x43, 0x01, 0x25, 0x3D, 0x4B, 0x5A, 0x22, 0x1A, 0x74, 0x3C, 0x4B, | |
| 606 | 0x20, 0x3B, 0x18, 0x72, 0x02, 0x20, 0x40, 0x1C, 0x20, 0x28, 0xFC, 0xD3, 0x39, 0x4C, 0x00, 0x26, | |
| 607 | 0xA6, 0x81, 0x48, 0x88, 0xE2, 0x13, 0x82, 0x18, 0x00, 0x2D, 0x09, 0xD0, 0x00, 0x20, 0x03, 0xE0, | |
| 608 | 0x45, 0x18, 0xAD, 0x68, 0x15, 0x50, 0x00, 0x1D, 0x8D, 0x88, 0x85, 0x42, 0xF8, 0xD8, 0x08, 0xE0, | |
| 609 | 0x00, 0x20, 0x03, 0xE0, 0x45, 0x18, 0x2D, 0x7A, 0x15, 0x54, 0x40, 0x1C, 0x8D, 0x88, 0x85, 0x42, | |
| 610 | 0xF8, 0xD8, 0x1E, 0x72, 0x2C, 0x48, 0xA0, 0x81, 0x02, 0x20, 0x00, 0x24, 0x23, 0x46, 0x0B, 0xE0, | |
| 611 | 0x5F, 0x18, 0x3E, 0x7A, 0xD5, 0x5C, 0xAE, 0x42, 0x05, 0xD0, 0x3D, 0x72, 0x00, 0x2C, 0x00, 0xD1, | |
| 612 | 0x4B, 0x80, 0x04, 0x20, 0x64, 0x1C, 0x5B, 0x1C, 0x8D, 0x88, 0x9D, 0x42, 0xF0, 0xD8, 0x8C, 0x80, | |
| 613 | 0xF0, 0xBD, 0x23, 0x49, 0x21, 0x48, 0x08, 0x60, 0x1E, 0x48, 0x08, 0x26, 0x40, 0x38, 0x86, 0x83, | |
| 614 | 0x5A, 0x21, 0x01, 0x70, 0x01, 0x22, 0x02, 0x71, 0x05, 0x21, 0x01, 0x72, 0x1D, 0x49, 0x81, 0x81, | |
| 615 | 0x16, 0x4D, 0x00, 0x21, 0x29, 0x80, 0xFF, 0x21, 0x49, 0x1E, 0xFD, 0xD1, 0x01, 0x21, 0x1A, 0x4B, | |
| 616 | 0x49, 0x02, 0x99, 0x80, 0x49, 0x1E, 0x01, 0x82, 0x81, 0x8B, 0x11, 0x43, 0x81, 0x83, 0x02, 0x27, | |
| 617 | 0x28, 0x78, 0x2C, 0x46, 0xC0, 0x07, 0xFB, 0xD0, 0x60, 0x88, 0xA1, 0x88, 0x08, 0x18, 0x80, 0xB2, | |
| 618 | 0x00, 0x22, 0x04, 0xE0, 0x13, 0x19, 0x1B, 0x7A, 0x18, 0x18, 0x80, 0xB2, 0x52, 0x1C, 0x91, 0x42, | |
| 619 | 0xF8, 0xD8, 0xE2, 0x88, 0x82, 0x42, 0x01, 0xD0, 0x2E, 0x80, 0xE9, 0xE7, 0x00, 0x29, 0x03, 0xD0, | |
| 620 | 0xFF, 0xF7, 0x78, 0xFF, 0x20, 0x80, 0xE3, 0xE7, 0x2F, 0x80, 0xE1, 0xE7, 0x00, 0x04, 0x00, 0x20, | |
| 621 | 0x40, 0x5C, 0x00, 0x40, 0x40, 0x30, 0x00, 0x40, 0xFF, 0x01, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, | |
| 622 | 0x80, 0xE1, 0x00, 0xE0, 0x04, 0x0E, 0x00, 0x00, 0x00, 0x34, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, | |
| 623 | }; | |
| 624 | ||
| 625 | #define is_mfc_hv_wireless_type(cable_type) ( \ | |
| 626 | cable_type == MFC_PAD_WPC_AFC || \ | |
| 627 | cable_type == MFC_PAD_WPC_STAND_HV || \ | |
| 628 | cable_type == MFC_PAD_PREPARE_HV || \ | |
| 629 | cable_type == MFC_PAD_WPC_VEHICLE_HV) | |
| 630 | ||
| 631 | struct mfc_charger_platform_data { | |
| 632 | int pad_mode; | |
| 633 | int wpc_det; | |
| 634 | int irq_wpc_det; | |
| 635 | int wpc_int; | |
| 636 | int mst_pwr_en; | |
| 637 | int wpc_en; | |
| 638 | int irq_wpc_int; | |
| 639 | int cs100_status; | |
| 640 | int vout_status; | |
| 641 | int wireless_cc_cv; | |
| 642 | int siop_level; | |
| 643 | u8 capacity; | |
| 644 | int cable_type; | |
| 645 | bool default_voreg; | |
| 646 | int is_charging; | |
| 647 | u32 *fod_a4wp_data_cv; | |
| 648 | u32 *fod_wpc_data_cv; | |
| 649 | u32 *fod_pma_data_cv; | |
| 650 | u32 *fod_a4wp_data; | |
| 651 | u32 *fod_wpc_data; | |
| 652 | u32 *fod_pma_data; | |
| 653 | u32 *fod_hero_5v_data; | |
| 654 | int fod_data_check; | |
| 655 | bool ic_on_mode; | |
| 656 | int hw_rev_changed; /* this is only for noble/zero2 */ | |
| 657 | int otp_firmware_result; | |
| 658 | int tx_firmware_result; | |
| 659 | int wc_ic_grade; | |
| 660 | int wc_ic_rev; | |
| 661 | int otp_firmware_ver; | |
| 662 | int tx_firmware_ver; | |
| 663 | int vout; | |
| 664 | int vrect; | |
| 665 | u8 tx_data_cmd; | |
| 666 | u8 tx_data_val; | |
| 667 | char *wireless_charger_name; | |
| 668 | char *wired_charger_name; | |
| 669 | char *fuelgauge_name; | |
| 670 | int tx_status; | |
| 671 | int wpc_cc_cv_vout; | |
| 672 | int wpc_cv_call_vout; | |
| 673 | int wpc_cc_call_vout; | |
| 674 | int opfq_cnt; | |
| 675 | int hv_vout_wa; | |
| 676 | int mst_switch_delay; | |
| 677 | int wc_cover_rpp; | |
| 678 | int wc_hv_rpp; | |
| 679 | }; | |
| 680 | ||
| 681 | #define mfc_charger_platform_data_t \ | |
| 682 | struct mfc_charger_platform_data | |
| 683 | ||
| 684 | #define MST_MODE_0 0 | |
| 685 | #define MST_MODE_2 1 | |
| 686 | ||
| 687 | struct mfc_charger_data { | |
| 688 | struct i2c_client *client; | |
| 689 | struct device *dev; | |
| 690 | mfc_charger_platform_data_t *pdata; | |
| 691 | struct mutex io_lock; | |
| 692 | const struct firmware *firm_data_bin; | |
| 693 | ||
| 694 | int wc_w_state; | |
| 695 | ||
| 696 | struct power_supply *psy_chg; | |
| 697 | struct wake_lock wpc_wake_lock; | |
| 698 | struct wake_lock mst_wake_lock; | |
| 699 | struct wake_lock wpc_update_lock; | |
| 700 | struct wake_lock wpc_opfq_lock; | |
| 701 | struct wake_lock wpc_afc_vout_lock; | |
| 702 | struct wake_lock wpc_vout_mode_lock; | |
| 5a068558 | 703 | struct wake_lock wpc_tx_id_lock; |
| 1cac41cb MB |
704 | struct workqueue_struct *wqueue; |
| 705 | struct work_struct wcin_work; | |
| 706 | struct delayed_work wpc_det_work; | |
| 707 | struct delayed_work wpc_opfq_work; | |
| 708 | struct delayed_work wpc_isr_work; | |
| 709 | struct delayed_work wpc_tx_id_work; | |
| 710 | struct delayed_work mst_off_work; | |
| 711 | struct delayed_work wpc_int_req_work; | |
| 712 | struct delayed_work wpc_fw_update_work; | |
| 713 | struct delayed_work wpc_afc_vout_work; | |
| 714 | struct delayed_work wpc_fw_booting_work; | |
| 715 | struct delayed_work wpc_vout_mode_work; | |
| 716 | struct delayed_work wpc_cm_fet_work; | |
| 717 | struct delayed_work wpc_i2c_error_work; | |
| 718 | ||
| 719 | u16 addr; | |
| 720 | int size; | |
| 721 | int is_afc; | |
| 722 | int pad_vout; | |
| 723 | int is_mst_on; /* mst */ | |
| 724 | int chip_id; | |
| 725 | int fw_cmd; | |
| 726 | int vout_mode; | |
| 727 | int is_full_status; | |
| 728 | int mst_off_lock; | |
| 729 | bool is_otg_on; | |
| 730 | int led_cover; | |
| 731 | bool is_probed; | |
| 732 | bool is_afc_tx; | |
| 733 | bool tx_id_done; | |
| 734 | int tx_id; | |
| 5a068558 | 735 | int tx_id_cnt; |
| 1cac41cb MB |
736 | u8 device_event; |
| 737 | ||
| 738 | int i2c_error_count; | |
| 739 | }; | |
| 740 | ||
| 741 | #endif /* __MFC_CHARGER_H */ |