[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / arch / arm64 / kernel / asm-offsets.c

/*
 * Based on arch/arm/kernel/asm-offsets.c
 *
 * Copyright (C) 1995-2003 Russell King
 *               2001-2002 Keith Owens
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>
#include <linux/kvm_host.h>
#include <asm/fixmap.h>
#include <asm/thread_info.h>
#include <asm/memory.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include <asm/vdso_datapage.h>
#include <linux/kbuild.h>
#include <linux/arm-smccc.h>

int main(void)
{
  DEFINE(TSK_ACTIVE_MM,		offsetof(struct task_struct, active_mm));
  BLANK();
#ifdef CONFIG_THREAD_INFO_IN_TASK
  DEFINE(TSK_TI_FLAGS,		offsetof(struct task_struct, thread_info.flags));
  DEFINE(TSK_TI_PREEMPT,	offsetof(struct task_struct, thread_info.preempt_count));
  DEFINE(TSK_TI_ADDR_LIMIT,	offsetof(struct task_struct, thread_info.addr_limit));
  DEFINE(TSK_STACK,		offsetof(struct task_struct, stack));
#else
  DEFINE(TI_FLAGS,		offsetof(struct thread_info, flags));
  DEFINE(TI_PREEMPT,		offsetof(struct thread_info, preempt_count));
  DEFINE(TI_ADDR_LIMIT,		offsetof(struct thread_info, addr_limit));
#endif
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
  DEFINE(TSK_TI_TTBR0,		offsetof(struct thread_info, ttbr0));
#endif
  BLANK();
  DEFINE(THREAD_CPU_CONTEXT,	offsetof(struct task_struct, thread.cpu_context));
  BLANK();
  DEFINE(S_X0,			offsetof(struct pt_regs, regs[0]));
  DEFINE(S_X1,			offsetof(struct pt_regs, regs[1]));
  DEFINE(S_X2,			offsetof(struct pt_regs, regs[2]));
  DEFINE(S_X3,			offsetof(struct pt_regs, regs[3]));
  DEFINE(S_X4,			offsetof(struct pt_regs, regs[4]));
  DEFINE(S_X5,			offsetof(struct pt_regs, regs[5]));
  DEFINE(S_X6,			offsetof(struct pt_regs, regs[6]));
  DEFINE(S_X7,			offsetof(struct pt_regs, regs[7]));
  DEFINE(S_LR,			offsetof(struct pt_regs, regs[30]));
  DEFINE(S_SP,			offsetof(struct pt_regs, sp));
#ifdef CONFIG_COMPAT
  DEFINE(S_COMPAT_SP,		offsetof(struct pt_regs, compat_sp));
#endif
  DEFINE(S_PSTATE,		offsetof(struct pt_regs, pstate));
  DEFINE(S_PC,			offsetof(struct pt_regs, pc));
  DEFINE(S_ORIG_X0,		offsetof(struct pt_regs, orig_x0));
  DEFINE(S_SYSCALLNO,		offsetof(struct pt_regs, syscallno));
  DEFINE(S_ORIG_ADDR_LIMIT,	offsetof(struct pt_regs, orig_addr_limit));
  DEFINE(S_FRAME_SIZE,		sizeof(struct pt_regs));
  BLANK();
  DEFINE(MM_CONTEXT_ID,		offsetof(struct mm_struct, context.id.counter));
  BLANK();
  DEFINE(VMA_VM_MM,		offsetof(struct vm_area_struct, vm_mm));
  DEFINE(VMA_VM_FLAGS,		offsetof(struct vm_area_struct, vm_flags));
  BLANK();
  DEFINE(VM_EXEC,	       	VM_EXEC);
  BLANK();
  DEFINE(PAGE_SZ,	       	PAGE_SIZE);
  BLANK();
  DEFINE(DMA_BIDIRECTIONAL,	DMA_BIDIRECTIONAL);
  DEFINE(DMA_TO_DEVICE,		DMA_TO_DEVICE);
  DEFINE(DMA_FROM_DEVICE,	DMA_FROM_DEVICE);
  BLANK();
#ifdef CONFIG_THREAD_INFO_IN_TASK
  DEFINE(CPU_BOOT_STACK,	offsetof(struct secondary_data, stack));
  DEFINE(CPU_BOOT_TASK,		offsetof(struct secondary_data, task));
  BLANK();
#endif
#ifdef CONFIG_KVM_ARM_HOST
  DEFINE(VCPU_CONTEXT,		offsetof(struct kvm_vcpu, arch.ctxt));
  DEFINE(CPU_GP_REGS,		offsetof(struct kvm_cpu_context, gp_regs));
  DEFINE(CPU_USER_PT_REGS,	offsetof(struct kvm_regs, regs));
  DEFINE(CPU_FP_REGS,		offsetof(struct kvm_regs, fp_regs));
  DEFINE(CPU_SP_EL1,		offsetof(struct kvm_regs, sp_el1));
  DEFINE(CPU_ELR_EL1,		offsetof(struct kvm_regs, elr_el1));
  DEFINE(CPU_SPSR,		offsetof(struct kvm_regs, spsr));
  DEFINE(CPU_SYSREGS,		offsetof(struct kvm_cpu_context, sys_regs));
  DEFINE(VCPU_ESR_EL2,		offsetof(struct kvm_vcpu, arch.fault.esr_el2));
  DEFINE(VCPU_FAR_EL2,		offsetof(struct kvm_vcpu, arch.fault.far_el2));
  DEFINE(VCPU_HPFAR_EL2,	offsetof(struct kvm_vcpu, arch.fault.hpfar_el2));
  DEFINE(VCPU_DEBUG_FLAGS,	offsetof(struct kvm_vcpu, arch.debug_flags));
  DEFINE(VCPU_DEBUG_PTR,	offsetof(struct kvm_vcpu, arch.debug_ptr));
  DEFINE(DEBUG_BCR, 		offsetof(struct kvm_guest_debug_arch, dbg_bcr));
  DEFINE(DEBUG_BVR, 		offsetof(struct kvm_guest_debug_arch, dbg_bvr));
  DEFINE(DEBUG_WCR, 		offsetof(struct kvm_guest_debug_arch, dbg_wcr));
  DEFINE(DEBUG_WVR, 		offsetof(struct kvm_guest_debug_arch, dbg_wvr));
  DEFINE(VCPU_HCR_EL2,		offsetof(struct kvm_vcpu, arch.hcr_el2));
  DEFINE(VCPU_MDCR_EL2,	offsetof(struct kvm_vcpu, arch.mdcr_el2));
  DEFINE(VCPU_IRQ_LINES,	offsetof(struct kvm_vcpu, arch.irq_lines));
  DEFINE(VCPU_HOST_CONTEXT,	offsetof(struct kvm_vcpu, arch.host_cpu_context));
  DEFINE(VCPU_HOST_DEBUG_STATE, offsetof(struct kvm_vcpu, arch.host_debug_state));
  DEFINE(VCPU_TIMER_CNTV_CTL,	offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl));
  DEFINE(VCPU_TIMER_CNTV_CVAL,	offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval));
  DEFINE(KVM_TIMER_CNTVOFF,	offsetof(struct kvm, arch.timer.cntvoff));
  DEFINE(KVM_TIMER_ENABLED,	offsetof(struct kvm, arch.timer.enabled));
  DEFINE(VCPU_KVM,		offsetof(struct kvm_vcpu, kvm));
  DEFINE(VCPU_VGIC_CPU,		offsetof(struct kvm_vcpu, arch.vgic_cpu));
  DEFINE(VGIC_V2_CPU_HCR,	offsetof(struct vgic_cpu, vgic_v2.vgic_hcr));
  DEFINE(VGIC_V2_CPU_VMCR,	offsetof(struct vgic_cpu, vgic_v2.vgic_vmcr));
  DEFINE(VGIC_V2_CPU_MISR,	offsetof(struct vgic_cpu, vgic_v2.vgic_misr));
  DEFINE(VGIC_V2_CPU_EISR,	offsetof(struct vgic_cpu, vgic_v2.vgic_eisr));
  DEFINE(VGIC_V2_CPU_ELRSR,	offsetof(struct vgic_cpu, vgic_v2.vgic_elrsr));
  DEFINE(VGIC_V2_CPU_APR,	offsetof(struct vgic_cpu, vgic_v2.vgic_apr));
  DEFINE(VGIC_V2_CPU_LR,	offsetof(struct vgic_cpu, vgic_v2.vgic_lr));
  DEFINE(VGIC_V3_CPU_SRE,	offsetof(struct vgic_cpu, vgic_v3.vgic_sre));
  DEFINE(VGIC_V3_CPU_HCR,	offsetof(struct vgic_cpu, vgic_v3.vgic_hcr));
  DEFINE(VGIC_V3_CPU_VMCR,	offsetof(struct vgic_cpu, vgic_v3.vgic_vmcr));
  DEFINE(VGIC_V3_CPU_MISR,	offsetof(struct vgic_cpu, vgic_v3.vgic_misr));
  DEFINE(VGIC_V3_CPU_EISR,	offsetof(struct vgic_cpu, vgic_v3.vgic_eisr));
  DEFINE(VGIC_V3_CPU_ELRSR,	offsetof(struct vgic_cpu, vgic_v3.vgic_elrsr));
  DEFINE(VGIC_V3_CPU_AP0R,	offsetof(struct vgic_cpu, vgic_v3.vgic_ap0r));
  DEFINE(VGIC_V3_CPU_AP1R,	offsetof(struct vgic_cpu, vgic_v3.vgic_ap1r));
  DEFINE(VGIC_V3_CPU_LR,	offsetof(struct vgic_cpu, vgic_v3.vgic_lr));
  DEFINE(VGIC_CPU_NR_LR,	offsetof(struct vgic_cpu, nr_lr));
  DEFINE(KVM_VTTBR,		offsetof(struct kvm, arch.vttbr));
  DEFINE(KVM_VGIC_VCTRL,	offsetof(struct kvm, arch.vgic.vctrl_base));
#endif
#ifdef CONFIG_CPU_PM
  DEFINE(CPU_SUSPEND_SZ,	sizeof(struct cpu_suspend_ctx));
  DEFINE(CPU_CTX_SP,		offsetof(struct cpu_suspend_ctx, sp));
  DEFINE(MPIDR_HASH_MASK,	offsetof(struct mpidr_hash, mask));
  DEFINE(MPIDR_HASH_SHIFTS,	offsetof(struct mpidr_hash, shift_aff));
  DEFINE(SLEEP_SAVE_SP_SZ,	sizeof(struct sleep_save_sp));
  DEFINE(SLEEP_SAVE_SP_PHYS,	offsetof(struct sleep_save_sp, save_ptr_stash_phys));
  DEFINE(SLEEP_SAVE_SP_VIRT,	offsetof(struct sleep_save_sp, save_ptr_stash));
#endif
  DEFINE(ARM_SMCCC_RES_X0_OFFS,	offsetof(struct arm_smccc_res, a0));
  DEFINE(ARM_SMCCC_RES_X2_OFFS,	offsetof(struct arm_smccc_res, a2));
  BLANK();
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
  DEFINE(TRAMP_VALIAS,		TRAMP_VALIAS);
#endif
  return 0;
}
Commit	Line	Data
0be7320a CM	1	/*
	2	* Based on arch/arm/kernel/asm-offsets.c
	3	*
	4	* Copyright (C) 1995-2003 Russell King
	5	* 2001-2002 Keith Owens
	6	* Copyright (C) 2012 ARM Ltd.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <linux/sched.h>
	22	#include <linux/mm.h>
	23	#include <linux/dma-mapping.h>
c3eb5b14	24	#include <linux/kvm_host.h>
39685f55	25	#include <asm/fixmap.h>
0be7320a CM	26	#include <asm/thread_info.h>
0be7320a CM	27	#include <asm/memory.h>
95322526 LP	28	#include <asm/smp_plat.h>
95322526 LP	29	#include <asm/suspend.h>
0be7320a CM	30	#include <asm/vdso_datapage.h>
0be7320a CM	31	#include <linux/kbuild.h>
a794759d	32	#include <linux/arm-smccc.h>
0be7320a CM	33
	34	int main(void)
	35	{
	36	DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
	37	BLANK();
4ca3c2cf MR	38	#ifdef CONFIG_THREAD_INFO_IN_TASK
	39	DEFINE(TSK_TI_FLAGS, offsetof(struct task_struct, thread_info.flags));
	40	DEFINE(TSK_TI_PREEMPT, offsetof(struct task_struct, thread_info.preempt_count));
	41	DEFINE(TSK_TI_ADDR_LIMIT, offsetof(struct task_struct, thread_info.addr_limit));
	42	DEFINE(TSK_STACK, offsetof(struct task_struct, stack));
	43	#else
0be7320a CM	44	DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
	45	DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
	46	DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit));
d6d869da	47	#endif
b83fbf1e CM	48	#ifdef CONFIG_ARM64_SW_TTBR0_PAN
	49	DEFINE(TSK_TI_TTBR0, offsetof(struct thread_info, ttbr0));
	50	#endif
0be7320a CM	51	BLANK();
	52	DEFINE(THREAD_CPU_CONTEXT, offsetof(struct task_struct, thread.cpu_context));
	53	BLANK();
	54	DEFINE(S_X0, offsetof(struct pt_regs, regs[0]));
	55	DEFINE(S_X1, offsetof(struct pt_regs, regs[1]));
	56	DEFINE(S_X2, offsetof(struct pt_regs, regs[2]));
	57	DEFINE(S_X3, offsetof(struct pt_regs, regs[3]));
	58	DEFINE(S_X4, offsetof(struct pt_regs, regs[4]));
	59	DEFINE(S_X5, offsetof(struct pt_regs, regs[5]));
	60	DEFINE(S_X6, offsetof(struct pt_regs, regs[6]));
	61	DEFINE(S_X7, offsetof(struct pt_regs, regs[7]));
	62	DEFINE(S_LR, offsetof(struct pt_regs, regs[30]));
	63	DEFINE(S_SP, offsetof(struct pt_regs, sp));
	64	#ifdef CONFIG_COMPAT
	65	DEFINE(S_COMPAT_SP, offsetof(struct pt_regs, compat_sp));
	66	#endif
	67	DEFINE(S_PSTATE, offsetof(struct pt_regs, pstate));
	68	DEFINE(S_PC, offsetof(struct pt_regs, pc));
	69	DEFINE(S_ORIG_X0, offsetof(struct pt_regs, orig_x0));
	70	DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno));
4caec816	71	DEFINE(S_ORIG_ADDR_LIMIT, offsetof(struct pt_regs, orig_addr_limit));
0be7320a CM	72	DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
0be7320a CM	73	BLANK();
5aec715d	74	DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
0be7320a CM	75	BLANK();
	76	DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
	77	DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
	78	BLANK();
	79	DEFINE(VM_EXEC, VM_EXEC);
	80	BLANK();
	81	DEFINE(PAGE_SZ, PAGE_SIZE);
	82	BLANK();
0be7320a CM	83	DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
	84	DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
	85	DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
	86	BLANK();
4ca3c2cf MR	87	#ifdef CONFIG_THREAD_INFO_IN_TASK
	88	DEFINE(CPU_BOOT_STACK, offsetof(struct secondary_data, stack));
	89	DEFINE(CPU_BOOT_TASK, offsetof(struct secondary_data, task));
	90	BLANK();
	91	#endif
55c7401d MZ	92	#ifdef CONFIG_KVM_ARM_HOST
	93	DEFINE(VCPU_CONTEXT, offsetof(struct kvm_vcpu, arch.ctxt));
	94	DEFINE(CPU_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs));
	95	DEFINE(CPU_USER_PT_REGS, offsetof(struct kvm_regs, regs));
	96	DEFINE(CPU_FP_REGS, offsetof(struct kvm_regs, fp_regs));
	97	DEFINE(CPU_SP_EL1, offsetof(struct kvm_regs, sp_el1));
	98	DEFINE(CPU_ELR_EL1, offsetof(struct kvm_regs, elr_el1));
	99	DEFINE(CPU_SPSR, offsetof(struct kvm_regs, spsr));
	100	DEFINE(CPU_SYSREGS, offsetof(struct kvm_cpu_context, sys_regs));
	101	DEFINE(VCPU_ESR_EL2, offsetof(struct kvm_vcpu, arch.fault.esr_el2));
	102	DEFINE(VCPU_FAR_EL2, offsetof(struct kvm_vcpu, arch.fault.far_el2));
	103	DEFINE(VCPU_HPFAR_EL2, offsetof(struct kvm_vcpu, arch.fault.hpfar_el2));
b0e626b3	104	DEFINE(VCPU_DEBUG_FLAGS, offsetof(struct kvm_vcpu, arch.debug_flags));
84e690bf AB	105	DEFINE(VCPU_DEBUG_PTR, offsetof(struct kvm_vcpu, arch.debug_ptr));
	106	DEFINE(DEBUG_BCR, offsetof(struct kvm_guest_debug_arch, dbg_bcr));
	107	DEFINE(DEBUG_BVR, offsetof(struct kvm_guest_debug_arch, dbg_bvr));
	108	DEFINE(DEBUG_WCR, offsetof(struct kvm_guest_debug_arch, dbg_wcr));
	109	DEFINE(DEBUG_WVR, offsetof(struct kvm_guest_debug_arch, dbg_wvr));
55c7401d	110	DEFINE(VCPU_HCR_EL2, offsetof(struct kvm_vcpu, arch.hcr_el2));
56c7f5e7	111	DEFINE(VCPU_MDCR_EL2, offsetof(struct kvm_vcpu, arch.mdcr_el2));
55c7401d MZ	112	DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines));
55c7401d MZ	113	DEFINE(VCPU_HOST_CONTEXT, offsetof(struct kvm_vcpu, arch.host_cpu_context));
84e690bf	114	DEFINE(VCPU_HOST_DEBUG_STATE, offsetof(struct kvm_vcpu, arch.host_debug_state));
55c7401d MZ	115	DEFINE(VCPU_TIMER_CNTV_CTL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl));
	116	DEFINE(VCPU_TIMER_CNTV_CVAL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval));
	117	DEFINE(KVM_TIMER_CNTVOFF, offsetof(struct kvm, arch.timer.cntvoff));
	118	DEFINE(KVM_TIMER_ENABLED, offsetof(struct kvm, arch.timer.enabled));
	119	DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
	120	DEFINE(VCPU_VGIC_CPU, offsetof(struct kvm_vcpu, arch.vgic_cpu));
eede821d MZ	121	DEFINE(VGIC_V2_CPU_HCR, offsetof(struct vgic_cpu, vgic_v2.vgic_hcr));
	122	DEFINE(VGIC_V2_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v2.vgic_vmcr));
	123	DEFINE(VGIC_V2_CPU_MISR, offsetof(struct vgic_cpu, vgic_v2.vgic_misr));
	124	DEFINE(VGIC_V2_CPU_EISR, offsetof(struct vgic_cpu, vgic_v2.vgic_eisr));
	125	DEFINE(VGIC_V2_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v2.vgic_elrsr));
	126	DEFINE(VGIC_V2_CPU_APR, offsetof(struct vgic_cpu, vgic_v2.vgic_apr));
	127	DEFINE(VGIC_V2_CPU_LR, offsetof(struct vgic_cpu, vgic_v2.vgic_lr));
2f5fa41a	128	DEFINE(VGIC_V3_CPU_SRE, offsetof(struct vgic_cpu, vgic_v3.vgic_sre));
754d3772 MZ	129	DEFINE(VGIC_V3_CPU_HCR, offsetof(struct vgic_cpu, vgic_v3.vgic_hcr));
	130	DEFINE(VGIC_V3_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v3.vgic_vmcr));
	131	DEFINE(VGIC_V3_CPU_MISR, offsetof(struct vgic_cpu, vgic_v3.vgic_misr));
	132	DEFINE(VGIC_V3_CPU_EISR, offsetof(struct vgic_cpu, vgic_v3.vgic_eisr));
	133	DEFINE(VGIC_V3_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v3.vgic_elrsr));
	134	DEFINE(VGIC_V3_CPU_AP0R, offsetof(struct vgic_cpu, vgic_v3.vgic_ap0r));
	135	DEFINE(VGIC_V3_CPU_AP1R, offsetof(struct vgic_cpu, vgic_v3.vgic_ap1r));
	136	DEFINE(VGIC_V3_CPU_LR, offsetof(struct vgic_cpu, vgic_v3.vgic_lr));
55c7401d MZ	137	DEFINE(VGIC_CPU_NR_LR, offsetof(struct vgic_cpu, nr_lr));
	138	DEFINE(KVM_VTTBR, offsetof(struct kvm, arch.vttbr));
	139	DEFINE(KVM_VGIC_VCTRL, offsetof(struct kvm, arch.vgic.vctrl_base));
95322526	140	#endif
af3cfdbf	141	#ifdef CONFIG_CPU_PM
95322526 LP	142	DEFINE(CPU_SUSPEND_SZ, sizeof(struct cpu_suspend_ctx));
	143	DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp));
	144	DEFINE(MPIDR_HASH_MASK, offsetof(struct mpidr_hash, mask));
	145	DEFINE(MPIDR_HASH_SHIFTS, offsetof(struct mpidr_hash, shift_aff));
	146	DEFINE(SLEEP_SAVE_SP_SZ, sizeof(struct sleep_save_sp));
	147	DEFINE(SLEEP_SAVE_SP_PHYS, offsetof(struct sleep_save_sp, save_ptr_stash_phys));
	148	DEFINE(SLEEP_SAVE_SP_VIRT, offsetof(struct sleep_save_sp, save_ptr_stash));
55c7401d	149	#endif
a794759d JW	150	DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0));
a794759d JW	151	DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
39685f55 WD	152	BLANK();
	153	#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
	154	DEFINE(TRAMP_VALIAS, TRAMP_VALIAS);
	155	#endif
0be7320a CM	156	return 0;
0be7320a CM	157	}