#include <dt-bindings/clock/exynos9610.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "exynos9610-pinctrl.dtsi"
+#include "exynos9610-rmem.dtsi"
+#include "exynos9610-debug.dtsi"
+#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/ufs/ufs.h>
#include "exynos9610-sysmmu.dtsi"
+#include <dt-bindings/soc/samsung/exynos9610-dm.h>
+#include "exynos9610-pm-domains.dtsi"
+#include <dt-bindings/soc/samsung/exynos9610-devfreq.h>
+#include "exynos9610-mfc.dtsi"
+#include "exynos9610-camera.dtsi"
+#include <dt-bindings/soc/samsung/exynos-bcm_dbg.h>
/ {
compatible = "samsung,armv8", "samsung,exynos9610";
pinctrl2 = &pinctrl_2;
pinctrl3 = &pinctrl_3;
pinctrl4 = &pinctrl_4;
-// pinctrl5 = &pinctrl_5;
+ pinctrl5 = &pinctrl_5;
usi0 = &usi_0_shub;
usi1 = &usi_0_shub_i2c;
usi2 = &usi_0_cmgp;
uart5 = &serial_5;
uart6 = &serial_6;
uart7 = &serial_7;
+ fmp0 = &fmp_0;
+ contexthub0 = &contexthub_0;
+ dpp0 = &dpp_0;
+ dpp1 = &dpp_1;
+ dpp2 = &dpp_2;
+ dpp3 = &dpp_3;
+ dsim0 = &dsim_0;
+ decon0 = &decon_f;
+ scaler0 = &scaler_0;
+ mfc0 = &mfc_0;
+ mshc2 = &dwmmc_2;
+ };
+
+ ect {
+ parameter_address = <0x90000000>;
+ parameter_size = <0x19000>;
+ };
+
+ chosen {
+ bootargs = "swiotlb=512 console=ram rootwait ro init=/init clk_ignore_unused bcm_setup=0xffffff80f8e00000 androidboot.hardware=exynos9610 androidboot.debug_level=0x4948 firmware_class.path=/vendor/firmware ecd_setup=disable reserve-fimc=0xffffff80f9fe0000 pmic_info=0x3 ccic_info=0x1 epx_activate=true";
+ linux,initrd-start = <0x84000000>;
+ linux,initrd-end = <0x841FFFFF>;
};
chipid@10000000 {
- compatible = "samsung,exynos9610-chipid";
- reg = <0x0 0x10000000 0x100>;
+ compatible = "samsung,exynos9-chipid";
+ reg = <0x0 0x10000000 0x100>, <0x0 0x2038848 0x10>;
+ };
+
+ arm-pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 82 4>,
+ <0 83 4>,
+ <0 84 4>,
+ <0 85 4>,
+ <0 96 4>,
+ <0 97 4>,
+ <0 98 4>,
+ <0 99 4>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
+ <&cpu3>, <&cpu4>, <&cpu5>,
+ <&cpu6>, <&cpu7>;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ coregroup0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cluster1 {
+ coregroup0 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ };
+
cpu0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
+ cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
+ sched-energy-data = <&A53_ENERGY>;
};
cpu1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+ cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
+ sched-energy-data = <&A53_ENERGY>;
};
cpu2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+ cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
+ sched-energy-data = <&A53_ENERGY>;
};
cpu3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+ cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
+ sched-energy-data = <&A53_ENERGY>;
};
cpu4: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a73", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
+ cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
+ sched-energy-data = <&A73_ENERGY>;
};
cpu5: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a73", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
+ cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
+ sched-energy-data = <&A73_ENERGY>;
};
cpu6: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a73", "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
+ cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
+ sched-energy-data = <&A73_ENERGY>;
};
cpu7: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a73", "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
+ cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
+ sched-energy-data = <&A73_ENERGY>;
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ BOOTCL_CPU_SLEEP: bootcl-cpu-sleep {
+ idle-state-name = "c2";
+ compatible = "exynos,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <35>;
+ exit-latency-us = <90>;
+ min-residency-us = <750>;
+ status = "okay";
+ };
+
+ NONBOOTCL_CPU_SLEEP: nobootcl-cpu-sleep {
+ idle-state-name = "c2";
+ compatible = "exynos,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <30>;
+ exit-latency-us = <75>;
+ min-residency-us = <2000>;
+ status = "okay";
+ };
+ };
+
+ energy-data {
+ A53_ENERGY: a53-energy {
+ capacity-mips = <230>;
+ power-coefficient = <450>;
+ };
+ A73_ENERGY: a73-energy {
+ capacity-mips = <480>;
+ power-coefficient = <870>;
+ };
+ };
+
+ ems {
+ /* Ontime Migration */
+ ontime {
+ /* little cores */
+ coregroup0 {
+ lower-boundary = <0>;
+ upper-boundary = <68>;
+ coverage-ratio = <100>;
+ };
+ /* big cores */
+ coregroup1 {
+ lower-boundary = <17>;
+ upper-boundary = <100>;
+ coverage-ratio = <75>;
+ };
+ };
+
+ /* Load Balance Trigger */
+ #define DEFAULT_RATIO 80
+ lbt {
+ overutil-level0 {
+ cpus = "0-3",
+ "4-7";
+ ratio = <30>,
+ <40>;
+ };
+ overutil-level1 {
+ cpus = "0-7";
+ ratio = <DEFAULT_RATIO>;
+ };
+ };
+
+ /* FRT Migration */
+ frt {
+ /* little cores */
+ coregroup0 {
+ coverage-ratio = <30>;
+ active-ratio = <25>;
+ };
+ /* big cores */
+ coregroup1 {
+ coverage-ratio = <15>;
+ active-ratio = <5>;
+ };
+ };
+
+ prefer-perf-service {
+ prefer-perf0 {
+ boost = <1>;
+ light-task-threshold = <0>;
+ prefer-cpus = "4-7", "0-3";
+ };
+ };
};
};
cpu_on = <0xC4000003>;
};
+ cpupm {
+ #define POWERMODE_TYPE_CLUSTER 0
+ #define POWERMODE_TYPE_SYSTEM 1
+
+ cpd_cl0 {
+ device_type = "cpupm";
+ target-residency = <10000>;
+ psci-index = <128>;
+ type = <POWERMODE_TYPE_CLUSTER>;
+ siblings = "0-3";
+ };
+
+ cpd_cl1 {
+ device_type = "cpupm";
+ target-residency = <3000>;
+ psci-index = <128>;
+ type = <POWERMODE_TYPE_CLUSTER>;
+ siblings = "4-7";
+ entry-allowed = "4-7";
+ };
+
+ sicd {
+ device_type = "cpupm";
+ target-residency = <3000>; /* us */
+ psci-index = <256>;
+ type = <POWERMODE_TYPE_SYSTEM>;
+ siblings = "0-7";
+ entry-allowed = "0-3";
+ system-idle;
+ };
+
+ idle-ip {
+ idle-ip-list =
+ "13970000.pwm", /* [ 0] pwm */
+ "11c30000.adc", /* [ 1] adc */
+ "110c0000.hsi2c", /* [ 2] hsi2c_0 */
+ "110d0000.hsi2c", /* [ 3] hsi2c_1 */
+ "11d00000.hsi2c", /* [ 4] hsi2c_2 */
+ "11d10000.hsi2c", /* [ 5] hsi2c_3 */
+ "11d20000.hsi2c", /* [ 6] hsi2c_4 */
+ "11d30000.hsi2c", /* [ 7] hsi2c_5 */
+ "11d40000.hsi2c", /* [ 8] hsi2c_6 */
+ "11d50000.hsi2c", /* [ 9] hsi2c_7 */
+ "11d60000.hsi2c", /* [10] hsi2c_8 */
+ "11d70000.hsi2c", /* [11] hsi2c_9 */
+ "11d80000.hsi2c", /* [12] hsi2c_10 */
+ "11d90000.hsi2c", /* [13] hsi2c_11 */
+ "138a0000.hsi2c", /* [14] hsi2c_12 */
+ "138b0000.hsi2c", /* [15] hsi2c_13 */
+ "138c0000.hsi2c", /* [16] hsi2c_14 */
+ "138d0000.hsi2c", /* [17] hsi2c_15 */
+ "13920000.hsi2c", /* [18] hsi2c_16 */
+ "13930000.hsi2c", /* [19] hsi2c_17 */
+ "13830000.i2c", /* [20] i2c_0 */
+ "13840000.i2c", /* [21] i2c_1 */
+ "13850000.i2c", /* [22] i2c_2 */
+ "13860000.i2c", /* [23] i2c_3 */
+ "13870000.i2c", /* [24] i2c_4 */
+ "13880000.i2c", /* [25] i2c_5 */
+ "13890000.i2c", /* [26] i2c_6 */
+ "110c0000.spi", /* [27] spi_0 */
+ "11d00000.spi", /* [28] spi_1 */
+ "11d20000.spi", /* [29] spi_2 */
+ "11d40000.spi", /* [30] spi_3 */
+ "11d60000.spi", /* [31] spi_4 */
+ "11d80000.spi", /* [32] spi_5 */
+ "13900000.spi", /* [33] spi_6 */
+ "13910000.spi", /* [34] spi_7 */
+ "13920000.spi", /* [35] spi_8 */
+ "13940000.spi", /* [36] spi_9 */
+ "13520000.ufs", /* [37] ufs */
+ "13500000.dwmmc0", /* [38] dwmmc0 */
+ "13550000.dwmmc2", /* [39] dwmmc2 */
+ "13200000.usb", /* [40] usb */
+ "pd-cam", /* [41] pd-cam */
+ "pd-isp", /* [42] pd-isp */
+ "pd-vipx1", /* [43] pd-vipx1 */
+ "pd-vipx2", /* [44] pd-vipx2 */
+ "pd-g2d", /* [45] pd-g2d */
+ "pd-g3d", /* [46] pd-g3d */
+ "pd-dispaud", /* [47] pd-dispaud */
+ "pd-mfc", /* [48] pd-mfc */
+ "148e0000.dsim"; /* [49] dsim_0 */
+
+ fix-idle-ip = "acpm_dvfs";
+ fix-idle-ip-index = <96>;
+
+ idle-ip-mask =
+ <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>,
+ <10>, <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>,
+ <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>, <31>, <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>,
+ <40>, <41>, <42>, <43>, <44>, <45>, <46>, <48>, <49>, <96>;
+ };
+ };
+
+ exynos-pm {
+ compatible = "samsung,exynos-pm";
+ reg = <0x0 0x11850000 0x1000>,
+ <0x0 0x12301200 0x100>;
+ reg-names = "gpio_alive_base",
+ "gicd_ispendrn_base";
+ num-eint = <24>;
+ num-gic = <16>;
+ suspend_mode_idx = <8>; /* SYS_SLEEP */
+ suspend_psci_idx = <1024>; /* PSCI_SYSTEM_SLEEP */
+ cp_call_mode_idx = <10>; /* SYS_SLEEP_AUD_ON */
+ cp_call_psci_idx = <1024>; /* PSCI_SYSTEM_SLEEP */
+ usbl2_suspend_available = <1>;
+ usbl2_suspend_mode_idx = <12>; /* SYS_SLEEP_USB_ON */
+ conn_req_offset = <0x00c0>; /* PMU_ALIVE__CONNECT_SLEEP_STATUS */
+ pmu_cp_stat_offset = <0x38>; /* PMU_ALIVE__CP_STAT */
+ pmu_gnss_stat_offset = <0x48>; /* PMU_ALIVE__GNSS_STAT */
+ pmu_wlbt_stat_offset = <0x58>; /* PMU_ALIVE__WLBT_STAT */
+ stat_access_mif_offset = <4>; /* PMU_ALIVE__*_STAT__ACCESS_MIF */
+ /* WAKEUP_STAT WAKEUP_STAT4 */
+ wakeup_stat = <0x600>, <0x60c>;
+
+ wakeup_stats {
+ wakeup_stat {
+ ws-name =
+ "EINT", /* [ 0] */
+ "RTC_ALARM", /* [ 1] */
+ "RTC_TICK", /* [ 2] */
+ "TRTC_ALARM", /* [ 3] */
+ "TRTC_TICK", /* [ 4] */
+ "WLBT_RESET_REQ", /* [ 5] */
+ "WLBT_ACTIVE", /* [ 6] */
+ "RESERVED", /* [ 7] */
+ "RESERVED", /* [ 8] */
+ "MMC0", /* [ 9] */
+ "RESERVED", /* [10] */
+ "MMC2", /* [11] */
+ "CMGP_EINT", /* [12] */
+ "USB_REWA", /* [13] */
+ "TIMER", /* [14] */
+ "CP_SCAN_DUMP_REQ", /* [15] */
+ "USBDRD20", /* [16] */
+ "INT_MBOX_WLBT2AP", /* [17] */
+ "INT_MBOX_SHUB2AP", /* [18] */
+ "INT_MBOX_APM2AP", /* [19] */
+ "CP_RESET_REQ", /* [20] */
+ "GNSS_WAKEUP_REQ", /* [21] */
+ "GNSS_RESET_REQ", /* [22] */
+ "GNSS_ACTIVE", /* [23] */
+ "INT_MBOX_CP2AP", /* [24] */
+ "CP_ACTIVE", /* [25] */
+ "INT_MBOX_GNSS2AP", /* [26] */
+ "APM_CPU", /* [27] */
+ "RESERVED", /* [28] */
+ "INT_MBOX_CP2AP_S", /* [29] */
+ "RESERVED", /* [30] */
+ "RESERVED"; /* [31] */
+ };
+ wakeup_stat4 {
+ ws-name =
+ "RESERVED", /* [ 0] */
+ "INT_SHUB_WDT", /* [ 1] */
+ "SPEEDY2_DDI", /* [ 2] */
+ "UART_BT_CTS", /* [ 3] */
+ "UART_BT_RXD"; /* [ 4] */
+ };
+ };
+ };
+
+ exynos-powermode {
+ wakeup-masks {
+ /*
+ * wakeup_mask configuration
+ * SICD SICD_CPD AFTR STOP
+ * LPD LPA ALPA DSTOP
+ * SLEEP SLEEP_VTS_ON SLEEP_AUD_ON FAPO
+ * SLEEP_USB_L2
+ */
+ wakeup-mask {
+ mask = <0x40000000>, <0x0>, <0x0>, <0x0>,
+ <0x0>, <0x0>, <0x0>, <0x0>,
+ <0xD0097E7E>, <0x50097E7E>, <0x50097E7E>, <0x0>,
+ <0xD0097E7E>;
+ mask-offset = <0x610>;
+ stat-offset = <0x600>;
+ };
+ wakeup-mask2 {
+ mask = <0x0>, <0x0>, <0x0>, <0x0>,
+ <0x0>, <0x0>, <0x0>, <0x0>,
+ <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>,
+ <0xFFFF00FF>;
+ mask-offset = <0x614>;
+ stat-offset = <0x604>;
+ };
+ wakeup-mask3 {
+ mask = <0x0>, <0x0>, <0x0>, <0x0>,
+ <0x0>, <0x0>, <0x0>, <0x0>,
+ <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>,
+ <0xFFFF00FF>;
+ mask-offset = <0x618>;
+ stat-offset = <0x608>;
+ };
+ wakeup-mask4 {
+ mask = <0x0>, <0x0>, <0x0>, <0x0>,
+ <0x0>, <0x0>, <0x0>, <0x0>,
+ <0x0>, <0x0>, <0x0>, <0x0>,
+ <0x0>;
+ mask-offset = <0x61c>;
+ stat-offset = <0x610>;
+ };
+ };
+ };
+
gic:interrupt-controller@12300000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
compatible = "samsung,exynos-speedy";
reg = <0x0 0x11a10000 0x2000>;
interrupts = <0 37 0>;
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&speedy_bus>;
status = "disabled";
acpm-ipc-channel = <5>;
};
+ ITMON@0 {
+ compatible = "samsung,exynos-itmon";
+ interrupts = <0 306 0>, /* TREX_D_CORE */
+ <0 320 0>, /* TREX_D_NRT */
+ <0 307 0>; /* TREX_P_CORE */
+ };
+
/* ALIVE */
pinctrl_0: pinctrl@11850000 {
compatible = "samsung,exynos9610-pinctrl";
reg = <0x0 0x11C20000 0x1000>;
interrupts = <0 142 0>, <0 143 0>, <0 144 0>, <0 145 0>,
<0 158 0>, <0 159 0>, <0 160 0>, <0 161 0>,
- <0 162 0>, <0 170 0>, <0 171 0>, <0 172 0>,
+ <0 170 0>, <0 171 0>, <0 172 0>,
<0 173 0>, <0 174 0>, <0 185 0>, <0 196 0>,
<0 197 0>, <0 226 0>, <0 227 0>, <0 228 0>,
- <0 269 0>, <0 270 0>, <0 272 0>, <0 278 0>,
+ <0 270 0>, <0 272 0>, <0 278 0>,
<0 318 0>, <0 319 0>;
+ WB2AP_FEMCTRL_WLBT_00: WB2AP_FEMCTRL_WLBT_00 {
+ samsung,pins = "gpm16-0";
+ samsung,pin-function = <0x6>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <3>;
+ };
+ WB2AP_FEMCTRL_WLBT_01: WB2AP_FEMCTRL_WLBT_01 {
+ samsung,pins = "gpm17-0";
+ samsung,pin-function = <0x6>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <3>;
+ };
+
wakeup-interrupt-controller {
compatible = "samsung,exynos7-wakeup-eint";
};
interrupts = <0 266 0>;
};
-#if 0
/* SHUB */
pinctrl_5: pinctrl@11080000{
compatible = "samsung,exynos9610-pinctrl";
reg = <0x0 0x11080000 0x1000>;
interrupts = <0 116 0>;
};
-#endif
/* USI_SHUB_0 */
usi_0_shub: usi@11013000 {
/* USI_SHUB_0_I2C */
usi_0_shub_i2c: usi@11013004 {
compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x11013018 0x4>;
+ reg = <0x0 0x11013004 0x4>;
/* usi_v2_mode = "i2c" or "spi" or "uart" */
status = "disabled";
};
reg = <0x0 0x110C0000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 112 0>;
-/*
- dma-mode;
- dmas = <&pdma0 25 &pdma0 24>;
-*/
- dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI_SHUB00_QCH>, <&clock MUX_SHUB_USI00>;
- clock-names = "gate_spi_clk", "ipclk_spi0";
+ clock-names = "gate_spi_clk", "ipclk_spi";
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
status = "disabled";
reg = <0x0 0x11D00000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 311 0>;
-/*
- dma-mode;
- dmas = <&pdma0 25 &pdma0 24>;
-*/
- dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI_CMGP00_QCH>, <&clock CMGP00_USI>;
- clock-names = "gate_spi_clk", "ipclk_spi0";
+ clock-names = "gate_spi_clk", "ipclk_spi";
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
status = "disabled";
reg = <0x0 0x11D20000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 312 0>;
-/*
- dma-mode;
- dmas = <&pdma0 25 &pdma0 24>;
-*/
- dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI_CMGP01_QCH>, <&clock CMGP01_USI>;
- clock-names = "gate_spi_clk", "ipclk_spi0";
+ clock-names = "gate_spi_clk", "ipclk_spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_bus>;
status = "disabled";
reg = <0x0 0x11D40000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 313 0>;
-/*
- dma-mode;
- dmas = <&pdma0 25 &pdma0 24>;
-*/
- dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI_CMGP02_QCH>, <&clock CMGP02_USI>;
- clock-names = "gate_spi_clk", "ipclk_spi0";
+ clock-names = "gate_spi_clk", "ipclk_spi";
pinctrl-names = "default";
pinctrl-0 = <&spi3_bus>;
status = "disabled";
reg = <0x0 0x11D60000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 314 0>;
-/*
- dma-mode;
- dmas = <&pdma0 25 &pdma0 24>;
-*/
- dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI_CMGP03_QCH>, <&clock CMGP03_USI>;
- clock-names = "gate_spi_clk", "ipclk_spi0";
+ clock-names = "gate_spi_clk", "ipclk_spi";
pinctrl-names = "default";
pinctrl-0 = <&spi4_bus>;
status = "disabled";
reg = <0x0 0x11D80000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 315 0>;
-/*
- dma-mode;
- dmas = <&pdma0 25 &pdma0 24>;
-*/
- dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI_CMGP04_QCH>, <&clock CMGP04_USI>;
- clock-names = "gate_spi_clk", "ipclk_spi0";
+ clock-names = "gate_spi_clk", "ipclk_spi";
pinctrl-names = "default";
pinctrl-0 = <&spi5_bus>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_SPI_0_QCH>, <&clock SPI0>;
- clock-names = "gate_spi_clk", "ipclk_spi0";
+ clock-names = "gate_spi_clk", "ipclk_spi";
pinctrl-names = "default";
pinctrl-0 = <&spi6_bus>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_SPI_1_QCH>, <&clock SPI1>;
- clock-names = "gate_spi_clk", "ipclk_spi0";
+ clock-names = "gate_spi_clk", "ipclk_spi";
pinctrl-names = "default";
pinctrl-0 = <&spi7_bus>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI00_USI_QCH>, <&clock USI_USI>;
- clock-names = "gate_spi_clk", "ipclk_spi0";
+ clock-names = "gate_spi_clk", "ipclk_spi";
pinctrl-names = "default";
pinctrl-0 = <&spi8_bus>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_SPI_2_QCH>, <&clock SPI2>;
- clock-names = "gate_spi_clk", "ipclk_spi0";
+ clock-names = "gate_spi_clk", "ipclk_spi";
pinctrl-names = "default";
pinctrl-0 = <&spi9_bus>;
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&uart0_bus>; /* or _bus_dual */
samsung,usi-serial-v2;
+ samsung,dbg-uart-ch;
+ samsung,dbg-uart-baud = <115200>;
+ samsung,dbg-word-len = <8>;
clocks = <&clock GATE_UART_QCH>, <&clock UART>;
clock-names = "gate_uart_clk0", "ipclk_uart0";
status = "disabled";
status = "disabled";
};
+ exynos_dm: exynos-dm@17000000 {
+ compatible = "samsung,exynos-dvfs-manager";
+ reg = <0x0 0x17000000 0x0>;
+ acpm-ipc-channel = <1>;
+ dm_domains {
+ cpufreq_cl0 {
+ dm-index = <DM_CPU_CL0>;
+ available = "true";
+ cal_id = <ACPM_DVFS_CPUCL0>;
+ dm_type_name = "dm_cpu_cl0";
+ };
+ cpufreq_cl1 {
+ dm-index = <DM_CPU_CL1>;
+ available = "true";
+ cal_id = <ACPM_DVFS_CPUCL1>;
+ dm_type_name = "dm_cpu_cl1";
+ };
+ devfreq_mif {
+ dm-index = <DM_MIF>;
+ available = "true";
+ policy_use = "true";
+ cal_id = <ACPM_DVFS_MIF>;
+ dm_type_name = "dm_mif";
+ };
+ devfreq_int {
+ dm-index = <DM_INT>;
+ available = "true";
+ policy_use = "true";
+ cal_id = <ACPM_DVFS_INT>;
+ dm_type_name = "dm_int";
+ };
+ devfreq_intcam {
+ dm-index = <DM_INTCAM>;
+ available = "true";
+ cal_id = <ACPM_DVFS_INTCAM>;
+ dm_type_name = "dm_intcam";
+ };
+ devfreq_cam {
+ dm-index = <DM_CAM>;
+ available = "true";
+ cal_id = <ACPM_DVFS_CAM>;
+ dm_type_name = "dm_cam";
+ };
+ devfreq_disp {
+ dm-index = <DM_DISP>;
+ available = "true";
+ cal_id = <ACPM_DVFS_DISP>;
+ dm_type_name = "dm_disp";
+ };
+ devfreq_aud {
+ dm-index = <DM_AUD>;
+ available = "true";
+ cal_id = <ACPM_DVFS_AUD>;
+ dm_type_name = "dm_aud";
+ };
+ dvfs_gpu {
+ dm-index = <DM_GPU>;
+ available = "false";
+ cal_id = <ACPM_DVFS_G3D>;
+ dm_type_name = "dm_gpu";
+ };
+ };
+ };
+
+ exynos_devfreq {
+ compatible = "samsung,exynos-devfreq-root";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ devfreq_0: devfreq_mif@17000010 {
+ compatible = "samsung,exynos-devfreq";
+ reg = <0x0 0x17000010 0x0>;
+ devfreq_type = <DEVFREQ_MIF>;
+ devfreq_domain_name = "dvfs_mif";
+ pm_qos_class = <13>; /* PM_QOS_BUS_THROUGHPUT */
+ pm_qos_class_max = <14>; /* PM_QOS_BUS_THROUGHPUT_MAX */
+ ess_flag = <ESS_FLAG_MIF>;
+ dm-index = <DM_MIF>;
+
+ /* Delay time */
+ use_delay_time = "true";
+ delay_time_list = "20";
+
+ freq_info = <2093000 546000 419000 419000 2093000 419000>;
+ /* initial_freq, default_qos, suspend_freq, min_freq, max_freq reboot_freq */
+
+ /* Booting value */
+ boot_info = <40 2093000>;
+ /* boot_qos_timeout, boot_freq */
+
+ /* governor data */
+ governor = <SIMPLE_INTERACTIVE>;
+
+ bts_update = "false";
+ dfs_id = <ACPM_DVFS_MIF>;
+ acpm-ipc-channel = <1>;
+ use_acpm = "true";
+ update_fvp = "true";
+ };
+
+ devfreq_1: devfreq_int@17000020 {
+ compatible = "samsung,exynos-devfreq";
+ reg = <0x0 0x17000020 0x0>;
+ devfreq_type = <DEVFREQ_INT>;
+ devfreq_domain_name = "dvfs_int";
+ pm_qos_class = <9>; /* PM_QOS_DEVICE_THROUGHPUT */
+ pm_qos_class_max = <11>; /* PM_QOS_DEVICE_THROUGHPUT_MAX */
+ ess_flag = <ESS_FLAG_INT>;
+ dm-index = <DM_INT>;
+
+ /* Delay time */
+ use_delay_time = "false";
+
+ freq_info = <667000 100000 100000 100000 667000 100000>;
+ /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
+
+ /* Booting value */
+ boot_info = <40 667000>;
+ /* boot_qos_timeout, boot_freq */
+
+ /* governor data */
+ governor = <SIMPLE_INTERACTIVE>;
+
+ bts_update = "false";
+ dfs_id = <ACPM_DVFS_INT>;
+ acpm-ipc-channel = <1>;
+ use_acpm = "true";
+ skew {
+ skew_0 {
+ constraint_dm_type = <DM_MIF>;
+ constraint_type = <CONSTRAINT_MIN>;
+ };
+ };
+ };
+
+ devfreq_2: devfreq_intcam@17000030 {
+ compatible = "samsung,exynos-devfreq";
+ reg = <0x0 0x17000030 0x0>;
+ devfreq_type = <DEVFREQ_INTCAM>;
+ devfreq_domain_name = "dvfs_intcam";
+ pm_qos_class = <10>; /* PM_QOS_INTCAM_THROUGHPUT */
+ pm_qos_class_max = <12>; /* PM_QOS_INTCAM_THROUGHPUT_MAX */
+ ess_flag = <ESS_FLAG_INTCAM>;
+ dm-index = <DM_INTCAM>;
+
+ /* Delay time */
+ use_delay_time = "false";
+
+ freq_info = <690000 650000 650000 650000 690000 650000>;
+ /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
+
+ /* Booting value */
+ boot_info = <40 650000>;
+ /* boot_qos_timeout, boot_freq */
+
+ /* governor data */
+ governor = <SIMPLE_INTERACTIVE>;
+
+ bts_update = "false";
+ dfs_id = <ACPM_DVFS_INTCAM>;
+ };
+
+ devfreq_3: devfreq_disp@17000040 {
+ compatible = "samsung,exynos-devfreq";
+ reg = <0x0 0x17000040 0x0>;
+ devfreq_type = <DEVFREQ_DISP>;
+ devfreq_domain_name = "dvfs_disp";
+ pm_qos_class = <17>; /* PM_QOS_DISPLAY_THROUGHPUT */
+ pm_qos_class_max = <18>; /* PM_QOS_DISPLAY_THROUGHPUT_MAX */
+ ess_flag = <ESS_FLAG_DISP>;
+ dm-index = <DM_DISP>;
+
+ /* Delay time */
+ use_delay_time = "false";
+
+ freq_info = <533000 167000 167000 167000 533000 533000>;
+ /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
+
+ /* Booting value */
+ boot_info = <40 533000>;
+ /* boot_qos_timeout, boot_freq */
+
+ /* governor data */
+ governor = <SIMPLE_INTERACTIVE>;
+
+ bts_update = "false";
+ dfs_id = <ACPM_DVFS_DISP>;
+ };
+
+ devfreq_4: devfreq_cam@17000050 {
+ compatible = "samsung,exynos-devfreq";
+ reg = <0x0 0x17000050 0x0>;
+ devfreq_type = <DEVFREQ_CAM>;
+ devfreq_domain_name = "dvfs_cam";
+ pm_qos_class = <19>; /* PM_QOS_CAM_THROUGHPUT */
+ pm_qos_class_max = <21>; /* PM_QOS_CAM_THROUGHPUT_MAX */
+ ess_flag = <ESS_FLAG_ISP>;
+ dm-index = <DM_CAM>;
+
+ /* Delay time */
+ use_delay_time = "false";
+
+ freq_info = <690000 640000 640000 640000 700000 640000>;
+ /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
+
+ /* Booting value */
+ boot_info = <40 690000>;
+ /* boot_qos_timeout, boot_freq */
+
+ /* governor data */
+ governor = <SIMPLE_INTERACTIVE>;
+
+ bts_update = "false";
+
+ dfs_id = <ACPM_DVFS_CAM>;
+ };
+
+ devfreq_5: devfreq_aud@17000060 {
+ compatible = "samsung,exynos-devfreq";
+ reg = <0x0 0x17000060 0x0>;
+ devfreq_type = <DEVFREQ_AUD>;
+ devfreq_domain_name = "dvfs_aud";
+ pm_qos_class = <20>; /* PM_QOS_AUD_THROUGHPUT */
+ pm_qos_class_max = <22>; /* PM_QOS_AUD_THROUGHPUT_MAX */
+ ess_flag = <ESS_FLAG_AUD>;
+ dm-index = <DM_AUD>;
+
+ /* Delay time */
+ use_delay_time = "false";
+
+ freq_info = <393000 393000 393000 393000 1180000 393000>;
+ /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
+
+ /* Booting value */
+ boot_info = <40 393000>;
+ /* boot_qos_timeout, boot_freq */
+
+ /* governor data */
+ governor = <SIMPLE_INTERACTIVE>;
+
+ bts_update = "false";
+ dfs_id = <ACPM_DVFS_AUD>;
+
+ samsung,power-domain = <&pd_dispaud>;
+ pd_name = "pd-dispaud";
+ };
+ };
+
+ tmuctrl_0: BIG@10070000 {
+ compatible = "samsung,exynos9610-tmu";
+ reg = <0x0 0x10070000 0x700>;
+ interrupts = <0 231 0>;
+ tmu_name = "BIG";
+ id = <0>;
+ sensors = <4>; /* P2 */
+ sensing_mode = "max";
+ hotplug_enable = <1>;
+ hotplug_in_threshold = <91>;
+ hotplug_out_threshold = <96>;
+ #include "exynos9610-tmu-sensor-conf.dtsi"
+ };
+
+ tmuctrl_1: LITTLE@10070000 {
+ compatible = "samsung,exynos9610-tmu";
+ reg = <0x0 0x10070000 0x700>;
+ interrupts = <0 231 0>;
+ tmu_name = "LITTLE";
+ id = <1>;
+ sensors = <2>; /* P1 */
+ sensing_mode = "max";
+ #include "exynos9610-tmu-sensor-conf.dtsi"
+ };
+
+ tmuctrl_2: G3D@10070000 {
+ compatible = "samsung,exynos9610-tmu";
+ reg = <0x0 0x10070000 0x700>;
+ interrupts = <0 231 0>;
+ tmu_name = "G3D";
+ id = <2>;
+ sensors = <1>; /* P0 */
+ sensing_mode = "max";
+ #include "exynos9610-tmu-sensor-conf.dtsi"
+ };
+
+ tmuctrl_3: ISP@10070000 {
+ compatible = "samsung,exynos9610-tmu";
+ reg = <0x0 0x10070000 0x700>;
+ interrupts = <0 231 0>;
+ tmu_name = "ISP";
+ id = <3>;
+ sensors = <2>; /* P1 */
+ sensing_mode = "max";
+ #include "exynos9610-tmu-sensor-conf.dtsi"
+ };
+
+ acpm_tmu {
+ acpm-ipc-channel = <7>;
+ };
+
+ thermal-zones {
+ big_thermal: BIG {
+ zone_name = "BIG_THERMAL";
+ polling-delay-passive = <50>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tmuctrl_0>;
+ governor = "power_allocator";
+ sustainable-power = <0>;
+ k_po = <0>;
+ k_pu = <0>;
+ k_i = <0>;
+ i_max = <0>;
+ integral_cutoff = <0>;
+
+ trips {
+ big_cold: big-cold {
+ temperature = <20000>;
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ big_switch_on: big-switch-on {
+ temperature = <63000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "active";
+ };
+ big_control_temp: big-control-temp {
+ temperature = <83000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "passive";
+ };
+ big_alert0: big-alert0 {
+ temperature = <95000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ big_alert1: big-alert1 {
+ temperature = <100000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ big_alert2: big-alert2 {
+ temperature = <105000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ big_alert3: big-alert3 {
+ temperature = <110000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ big_hot: big-hot {
+ temperature = <115000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "hot";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&big_control_temp>;
+ cooling-device = <&cpufreq_domain1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ little_thermal: LITTLE {
+ zone_name = "LITTLE_THERMAL";
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tmuctrl_1>;
+
+ trips {
+ little_alert0: little-alert0 {
+ temperature = <20000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ little_alert1: little-alert1 {
+ temperature = <76000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ little_alert2: little-alert2 {
+ temperature = <81000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ little_alert3: little-alert3 {
+ temperature = <91000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ little_alert4: little-alert4 {
+ temperature = <96000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ little_alert5: little-alert5 {
+ temperature = <101000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ little_alert6: little-alert6 {
+ temperature = <106000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ little_hot: little-hot {
+ temperature = <115000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "hot";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&little_alert0>;
+ /* Corresponds to 1534MHz at freq_table */
+ cooling-device = <&cpufreq_domain0 0 0>;
+ };
+ map1 {
+ trip = <&little_alert1>;
+ /* Corresponds to 1326MHz at freq_table */
+ cooling-device = <&cpufreq_domain0 0 0>;
+ };
+ map2 {
+ trip = <&little_alert2>;
+ /* Corresponds to 1118MHz at freq_table */
+ cooling-device = <&cpufreq_domain0 0 0>;
+ };
+ map3 {
+ trip = <&little_alert3>;
+ /* Corresponds to 910MHz at freq_table */
+ cooling-device = <&cpufreq_domain0 0 0>;
+ };
+ map4 {
+ trip = <&little_alert4>;
+ /* Corresponds to 702MHz at freq_table */
+ cooling-device = <&cpufreq_domain0 0 0>;
+ };
+ map5 {
+ trip = <&little_alert5>;
+ /* Corresponds to 403MHz at freq_table */
+ cooling-device = <&cpufreq_domain0 0 0>;
+ };
+ map6 {
+ trip = <&little_alert6>;
+ /* Corresponds to 403MHz at freq_table */
+ cooling-device = <&cpufreq_domain0 0 0>;
+ };
+ map7 {
+ trip = <&little_hot>;
+ /* Corresponds to 403MHz at freq_table */
+ cooling-device = <&cpufreq_domain0 0 0>;
+ };
+ };
+ };
+
+ gpu_thermal: G3D {
+ zone_name = "G3D_THERMAL";
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&tmuctrl_2>;
+ governor = "power_allocator";
+ sustainable-power = <0>;
+ k_po = <0>;
+ k_pu = <0>;
+ k_i = <0>;
+ i_max = <0>;
+ integral_cutoff = <0>;
+
+ trips {
+ gpu_cold: gpu-cold {
+ temperature = <20000>;
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ gpu_switch_on: gpu-switch-on {
+ temperature = <80000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "active";
+ };
+ gpu_control_temp: gpu-control-temp {
+ temperature = <88000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_alert0: gpu-alert0 {
+ temperature = <95000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ gpu_alert1: gpu-alert1 {
+ temperature = <100000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ gpu_alert2: gpu-alert2 {
+ temperature = <105000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ gpu_alert3: gpu-alert3 {
+ temperature = <110000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ gpu_hot: gpu-hot {
+ temperature = <115000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "hot";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_control_temp>;
+ cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ isp_thermal: ISP {
+ zone_name = "ISP_THERMAL";
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tmuctrl_3>;
+
+ trips {
+ isp_alert0: isp-alert0 {
+ temperature = <20000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ isp_alert1: isp-alert1 {
+ temperature = <76000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ isp_alert2: isp-alert2 {
+ temperature = <81000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ isp_alert3: isp-alert3 {
+ temperature = <91000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ isp_alert4: isp-alert4 {
+ temperature = <96000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ isp_alert5: isp-alert5 {
+ temperature = <101000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ isp_alert6: isp-alert6 {
+ temperature = <106000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "active";
+ };
+ isp_hot: isp-hot {
+ temperature = <115000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "hot";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&isp_alert0>;
+ /* Corresponds to No limit */
+ cooling-device = <&fimc_is 0 0>;
+ };
+ map1 {
+ trip = <&isp_alert1>;
+ /* Corresponds to No limit */
+ cooling-device = <&fimc_is 0 0>;
+ };
+ map2 {
+ trip = <&isp_alert2>;
+ /* Corresponds to 15fps at freq_table */
+ cooling-device = <&fimc_is 0 0>;
+ };
+ map3 {
+ trip = <&isp_alert3>;
+ /* Corresponds to 5fps at freq_table */
+ cooling-device = <&fimc_is 0 0>;
+ };
+ map4 {
+ trip = <&isp_alert4>;
+ /* Corresponds to 5fps at freq_table */
+ cooling-device = <&fimc_is 0 0>;
+ };
+ map5 {
+ trip = <&isp_alert5>;
+ /* Corresponds to 5fps at freq_table */
+ cooling-device = <&fimc_is 0 0>;
+ };
+ map6 {
+ trip = <&isp_alert6>;
+ /* Corresponds to 5fps at freq_table */
+ cooling-device = <&fimc_is 0 0>;
+ };
+ map7 {
+ trip = <&isp_hot>;
+ /* Corresponds to HW trip */
+ cooling-device = <&fimc_is 0 0>;
+ };
+ };
+ };
+ };
+
+ fmp_0: fmp {
+ compatible = "samsung,exynos-fmp";
+ };
+
ufs: ufs@0x13520000 {
/* ----------------------- */
/* 1. SYSTEM CONFIGURATION */
"UFS_EMBD";
/* PM QoS for INT power domain */
-/* ufs-pm-qos-int = <400000>;*/
+ ufs-pm-qos-int = <533000>;
/* DMA coherent callback, should be coupled with 'ufs-sys' */
dma-coherent;
vcc-supply = <&ufs_fixed_vcc>;
vcc-fixed-regulator;
-
+ ufs-power-gpio = <&gpg4 0 0>;
+ ufs-reset-n-gpio = <&gpf0 1 0>;
/* ----------------------- */
/* 3. UFS EXYNOS */
};
};
- watchdog_cl0@10050000 {
+ watchdog_cl0@10050000 { //WDT_CPUCL0
compatible = "samsung,exynos7-wdt";
reg = <0x0 0x10050000 0x100>;
interrupts = <0 232 0>;
index = <0>; /* if little cluster then index is 0*/
};
+ watchdog_cl1@10060000 { //WDT_CPUCL1
+ compatible = "samsung,exynos8-wdt";
+ reg = <0x0 0x10060000 0x100>;
+ interrupts = <0 233 0>;
+ clocks = <&clock OSCCLK>, <&clock GATE_WDT_CLUSTER1_QCH>;
+ clock-names = "rate_watchdog", "gate_watchdog";
+ timeout-sec = <30>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ index = <1>; /* if little cluster then index is 0*/
+ use_multistage_wdt;
+ };
+
exynos_adc: adc@11C30000 {
compatible = "samsung,exynos-adc-v3";
reg = <0x0 0x11C30000 0x100>;
status = "ok";
};
- iommu-domain_dpu {
- compatible = "samsung,exynos-iommu-bus";
+ dpp_0: dpp@0x14884000 { /* GF */
+ compatible = "samsung,exynos9-dpp";
+ #pb-id-cells = <3>;
+ /* DPU_DMA, DPP, DPU_DMA_COMMON */
+ reg = <0x0 0x14884000 0x1000>, <0x0 0x14895000 0x1000>, <0x0 0x14880000 0x110>;
+ /* DPU_DMA IRQ, DPP IRQ */
+ interrupts = <0 210 0>, <0 214 0>;
+ attr = <0x50007>; /* DPP/IDMA/FLIP/BLOCK/AFBC */
+ port = <0>; /* AXI port number */
+
+ /* HW restriction */
+ src_f_w = <16 65534 1>;
+ src_f_h = <16 8190 1>;
+ src_w = <16 2560 1>;
+ src_h = <16 3040 1>;
+ src_xy_align = <1 1>;
+
+ dst_f_w = <16 8190 1>;
+ dst_f_h = <16 8190 1>;
+ dst_w = <16 2560 1>;
+ dst_h = <16 3040 1>;
+ dst_xy_align = <1 1>;
+
+ blk_w = <4 2560 1>;
+ blk_h = <1 3040 1>;
+ blk_xy_align = <1 1>;
+
+ src_h_rot_max = <2160>;
+ };
+
+ dpp_1: dpp@0x14883000 { /* VG0 */
+ compatible = "samsung,exynos9-dpp";
+ #pb-id-cells = <3>;
+ reg = <0x0 0x14883000 0x1000>, <0x0 0x14896000 0x1000>;
+ interrupts = <0 211 0>, <0 215 0>;
+ attr = <0x500B6>; /* DPP/IDMA/HDR10/SCALE/CSC/FLIP/BLOCK */
+ port = <0>; /* AXI port number */
+ };
+
+ dpp_2: dpp@0x14881000 { /* G0 */
+ compatible = "samsung,exynos9-dpp";
+ #pb-id-cells = <3>;
+ reg = <0x0 0x14881000 0x1000>, <0x0 0x14891000 0x1000>;
+ interrupts = <0 208 0>, <0 212 0>;
+ attr = <0x50006>; /* DPP/IDMA/FLIP/BLOCK */
+ port = <0>; /* AXI port number */
+ };
+
+ dpp_3: dpp@0x14882000 { /* G1 */
+ compatible = "samsung,exynos9-dpp";
+ #pb-id-cells = <3>;
+ reg = <0x0 0x14882000 0x1000>, <0x0 0x14892000 0x1000>;
+ interrupts = <0 209 0>, <0 213 0>;
+ attr = <0x50006>; /* DPP/IDMA/FLIP/BLOCK */
+ port = <0>; /* AXI port number */
+ };
+
+ disp_ss: disp_ss@0x14810000 { /* SYSREG_DISPAUD */
+ compatible = "samsung,exynos9-disp_ss";
+ reg = <0x0 0x14811000 0x10>;
+ };
+
+ mipi_phy_dsim: phy_m4s4top_dsi0@0x11860000 {
+ compatible = "samsung,mipi-phy-m4s4-top";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ isolation = <0x070C>;
+ /* PHY reset be controlled from DSIM */
+ /* reg = <0x0 0x14811008 0x4>; */
+ /* reset = <0 1>; */
+ /* init = <4 5>; */ /* PHY reset control path bit of SYSREG */
+ owner = <0>; /* 0: DSI, 1: CSI */
+ #phy-cells = <1>;
+ };
+
+ dsim_0: dsim@0x148E0000 {
+ compatible = "samsung,exynos9-dsim";
+ reg = <0x0 0x148E0000 0x100>;
+ interrupts = <0 204 0>;
+ iommus = <&sysmmu_dpu>;
+ phys = <&mipi_phy_dsim 0>;
+ phy-names = "dsim_dphy";
+
+ /* clock */
+ clock-names = "aclk";
+ clocks = <&clock UMUX_CLKCMU_DISPAUD_BUS>;
+
+ memory-region = <&fb_rmem>;
+ ddi_id = <0xffffffff>;
+ };
+
+ decon_f: decon_f@0x148B0000 {
+ compatible = "samsung,exynos9-decon"; /* exynos9810 */
+ #pb-id-cells = <4>;
+ reg = <0x0 0x148B0000 0x10000>;
+
+ /* interrupt num : FRAME_START, FRMAE_DONE, EXTRA, GPIO_PERIC1(EXT_INT_TE: GPD0[0]) */
+ interrupts = <0 199 0>,
+ <0 200 0>,
+ <0 203 0>,
+ <0 266 0>;
+
+ /* pinctrl */
+ pinctrl-names = "hw_te_on", "hw_te_off";
+ pinctrl-0 = <&decon_f_te_on>;
+ pinctrl-1 = <&decon_f_te_off>;
+
+ max_win = <4>;
+ default_win = <0>;
+ default_idma = <0>;
+ psr_mode = <0>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
+ trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */
+ dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
+
+ /* 0: DSI, 1: eDP, 2:HDMI, 3: WB */
+ out_type = <0>;
+ /* 0: DSI0, 1: DSI1, 2: DSI2 */
+ out_idx = <0>;
+
+ /* power domain */
+ pd_name = "pd-dispaud";
+
+ /* pixel per clock */
+ ppc = <2>;
+
+ chip_ver = <9610>;
+
+ dpp_cnt = <4>;
+ dsim_cnt = <2>;
+ decon_cnt = <3>;
+
#address-cells = <2>;
#size-cells = <1>;
ranges;
- domain-clients = <>;
+ /* EINT for TE */
+ gpios = <&gpc2 3 0xf>;
+ /* sw te pending register */
+ te_eint {
+ /* NWEINT_GPD0_PEND */
+ reg = <0x0 0x139B0a14 0x4>;
+ };
+
+ cam-stat {
+ /* ISPPRE_STATUS(0x1406404C), ISPHQ_STATUS(0x14064054), ISPLP_STATUS(0x1406405C) */
+ reg = <0x0 0x11864024 0x4>;
+ };
};
- iommu-domain_vipx {
- compatible = "samsung,exynos-iommu-bus";
+ abox_gic: abox_gic@0x14AF0000 {
+ compatible = "samsung,abox_gic";
+ status = "okay";
+ reg = <0x0 0x14AF1000 0x1000>, <0x0 0x14AF2000 0x1004>;
+ reg-names = "gicd", "gicc";
+ interrupts = <0 198 0>;
+ };
+
+ abox: abox@0x14A50000 {
+ compatible = "samsung,abox";
+ status = "okay";
+ reg = <0x0 0x14A50000 0x10000>, <0x0 0x14810000 0x3000>, <0x0 0x14B00000 0x35000>;
+ reg-names = "sfr", "sysreg", "sram";
#address-cells = <2>;
#size-cells = <1>;
ranges;
+ quirks = "try to asrc off", "off on suspend", "scsc bt";
+ #sound-dai-cells = <1>;
+ ipc_tx_offset = <0x22000>;
+ ipc_rx_offset = <0x22300>;
+ ipc_tx_ack_offset = <0x222FC>;
+ ipc_rx_ack_offset = <0x225FC>;
+ abox_gic = <&abox_gic>;
+ clocks = <&clock PLL_OUT_AUD>, <&clock GATE_ABOX_QCH_CPU>,
+ <&clock DOUT_CLK_AUD_AUDIF>, <&clock DOUT_CLK_AUD_ACLK>;
+ clock-names = "pll", "cpu", "audif", "bus";
+ uaif_max_div = <512>;
+ iommus = <&sysmmu_abox>;
+ pm_qos_int = <0 0 0 0 0>;
+ pm_qos_aud = <1180000 800000 590000 394000 0>;
+ pd_name = "pd-dispaud";
+
+ abox_rdma_0: abox_rdma@0x14A51000 {
+ compatible = "samsung,abox-rdma";
+ reg = <0x0 0x14A51000 0x100>;
+ id = <0>;
+ type = "normal";
+ };
- domain-clients = <>;
+ abox_rdma_1: abox_rdma@0x14A51100 {
+ compatible = "samsung,abox-rdma";
+ reg = <0x0 0x14A51100 0x100>;
+ id = <1>;
+ type = "normal";
+ };
+
+ abox_rdma_2: abox_rdma@0x14A51200 {
+ compatible = "samsung,abox-rdma";
+ reg = <0x0 0x14A51200 0x100>;
+ id = <2>;
+ type = "normal";
+ };
+
+ abox_rdma_3: abox_rdma@0x14A51300 {
+ compatible = "samsung,abox-rdma";
+ reg = <0x0 0x14A51300 0x100>;
+ id = <3>;
+ type = "sync";
+ };
+
+ abox_rdma_4: abox_rdma@0x14A51400 {
+ compatible = "samsung,abox-rdma";
+ reg = <0x0 0x14A51400 0x100>;
+ id = <4>;
+ type = "call";
+ };
+
+ abox_rdma_5: abox_rdma@0x14A51500 {
+ compatible = "samsung,abox-rdma";
+ reg = <0x0 0x14A51500 0x100>, <0x0 0x14B22600 0x70>;
+ id = <5>;
+ type = "compress";
+ };
+
+ abox_rdma_6: abox_rdma@0x14A51600 {
+ compatible = "samsung,abox-rdma";
+ reg = <0x0 0x14A51600 0x100>;
+ id = <6>;
+ type = "realtime";
+ scsc_bt;
+ };
+
+ abox_rdma_7: abox_rdma@0x14A51700 {
+ compatible = "samsung,abox-rdma";
+ reg = <0x0 0x14A51700 0x100>;
+ id = <7>;
+ type = "normal";
+ };
+
+ abox_wdma_0: abox_wdma@0x14A52000 {
+ compatible = "samsung,abox-wdma";
+ reg = <0x0 0x14A52000 0x100>;
+ id = <0>;
+ type = "normal";
+ scsc_bt;
+ };
+
+ abox_wdma_1: abox_wdma@0x14A52100 {
+ compatible = "samsung,abox-wdma";
+ reg = <0x0 0x14A52100 0x100>;
+ id = <1>;
+ type = "normal";
+ };
+
+ abox_wdma_2: abox_wdma@0x14A52200 {
+ compatible = "samsung,abox-wdma";
+ reg = <0x0 0x14A52200 0x100>;
+ id = <2>;
+ type = "call";
+ };
+
+ abox_wdma_3: abox_wdma@0x14A52300 {
+ compatible = "samsung,abox-wdma";
+ reg = <0x0 0x14A52300 0x100>;
+ id = <3>;
+ type = "realtime";
+ };
+
+ abox_wdma_4: abox_wdma@0x14A52400 {
+ compatible = "samsung,abox-wdma";
+ reg = <0x0 0x14A52400 0x100>;
+ id = <4>;
+ type = "realtime";
+ };
+
+ abox_uaif_0: abox_uaif@0x14A50500 {
+ compatible = "samsung,abox-uaif";
+ reg = <0x0 0x14A50500 0x10>;
+ id = <0>;
+ clocks = <&clock DOUT_CLK_AUD_UAIF0>, <&clock GATE_ABOX_QCH_S_BCLK0>;
+ clock-names = "bclk", "bclk_gate";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&aud_i2s0_bus &aud_i2s0_sdo_bus &aud_codec_mclk>;
+ pinctrl-1 = <&aud_i2s0_idle &aud_codec_mclk_idle>;
+ #sound-dai-cells = <0>;
+ };
+
+ abox_uaif_1: abox_uaif@0x14A50510 {
+ compatible = "samsung,abox-uaif";
+ reg = <0x0 0x14A50510 0x10>;
+ id = <1>;
+ clocks = <&clock DOUT_CLK_AUD_UAIF1>, <&clock GATE_ABOX_QCH_S_BCLK1>;
+ clock-names = "bclk", "bclk_gate";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&aud_i2s1_bus &aud_i2s1_sdo_bus>;
+ pinctrl-1 = <&aud_i2s1_idle>;
+ #sound-dai-cells = <0>;
+ };
+
+ abox_uaif_2: abox_uaif@0x14A50520 {
+ compatible = "samsung,abox-uaif";
+ reg = <0x0 0x14A50520 0x10>;
+ id = <2>;
+ clocks = <&clock DOUT_CLK_AUD_UAIF2>, <&clock GATE_ABOX_QCH_S_BCLK2>;
+ clock-names = "bclk", "bclk_gate";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&aud_i2s2_bus &aud_i2s2_sdo_bus>;
+ pinctrl-1 = <&aud_i2s2_idle>;
+ #sound-dai-cells = <0>;
+ };
+
+ abox_uaif_4: abox_uaif@0x14A50540 {
+ compatible = "samsung,abox-uaif";
+ reg = <0x0 0x14A50540 0x10>;
+ id = <4>;
+ /* UAIF4 is connected to UAIF0 as slave */
+ clocks = <&clock DOUT_CLK_AUD_UAIF0>, <&clock GATE_ABOX_QCH_S_BCLK0>;
+ clock-names = "bclk", "bclk_gate";
+ #sound-dai-cells = <0>;
+ };
+
+ abox_dsif: abox_dsif@0x14A50550 {
+ compatible = "samsung,abox-dsif";
+ reg = <0x0 0x14A50550 0x10>;
+ id = <5>;
+ clocks = <&clock DOUT_CLK_AUD_DSIF>, <&clock GATE_ABOX_QCH_S_BCLK_DSIF>;
+ clock-names = "bclk", "bclk_gate";
+ /* DSIF and UAIF2 shares GPIO
+ * pinctrl-names = "default", "sleep";
+ * pinctrl-0 = <&aud_dsd_bus>;
+ * pinctrl-1 = <&aud_dsd_idle>;
+ */
+ #sound-dai-cells = <0>;
+ };
+
+ abox_spdy: abox_spdy@0x14A50560 {
+ compatible = "samsung,abox-spdy";
+ reg = <0x0 0x14A50560 0x10>;
+ id = <6>;
+ clocks = <&clock DOUT_CLK_AUD_FM>, <&clock GATE_ABOX_QCH_FM>;
+ clock-names = "bclk", "bclk_gate";
+ /* FM SPEEDY GPIO is controlled by FM radio driver
+ * pinctrl-names = "default", "sleep";
+ * pinctrl-0 = <&aud_fm_bus>;
+ * pinctrl-1 = <&aud_fm_idle>;
+ */
+ #sound-dai-cells = <0>;
+ };
+
+ abox_effect: abox_effect@0x14B2E000 {
+ compatible = "samsung,abox-effect";
+ reg = <0x0 0x14B2E000 0x1000>;
+ reg-names = "reg";
+ abox = <&abox>;
+ };
+
+ abox_debug: abox-debug@0 {
+ compatible = "samsung,abox-debug";
+ memory-region = <&abox_rmem>;
+ reg = <0x0 0x0 0x0>;
+ };
+
+ abox_vss: abox_vss@0 {
+ compatible = "samsung,abox-vss";
+ magic_offset = <0x600000>;
+ reg = <0x0 0x0 0x0>;
+ };
+
+ abox_bt: abox_bt@0 {
+ compatible = "samsung,abox-bt";
+ reg = <0x0 0x0 0x0>, <0x0 0x119D0000 0x1000>;
+ reg-names = "sfr", "mailbox";
+ };
+
+ ext_bin_0: ext_bin@0 {
+ status = "enabled";
+ samsung,name = "dsm.bin";
+ samsung,area = <1>; /* 0:SRAM, 1:DRAM, 2:VSS */
+ samsung,offset = <0x502000>;
+ };
+ ext_bin_1: ext_bin@1 {
+ status = "okay";
+ samsung,name = "AP_AUDIO_SLSI.bin";
+ samsung,area = <1>;
+ samsung,offset = <0x7F0000>;
+ };
+ ext_bin_2: ext_bin@2 {
+ status = "okay";
+ samsung,name = "audio_se.bin";
+ samsung,area = <1>;
+ samsung,offset = <0x602000>;
+ };
+ ext_bin_3: ext_bin@3 {
+ status = "disabled";
+ samsung,name = "SoundBoosterParam.bin";
+ samsung,area = <1>;
+ samsung,offset = <0x4FC000>;
+ };
+ ext_bin_4: ext_bin@4 {
+ status = "disabled";
+ samsung,name = "dummy.bin";
+ samsung,area = <1>;
+ samsung,offset = <0x800000>;
+ };
+ ext_bin_5: ext_bin@5 {
+ status = "disabled";
+ samsung,name = "APBiBF_AUDIO_SLSI.bin";
+ samsung,area = <1>;
+ samsung,offset = <0x7EF000>;
+ };
+ ext_bin_6: ext_bin@6 {
+ status = "disabled";
+ samsung,name = "dummy.bin";
+ samsung,area = <1>;
+ samsung,offset = <0x800000>;
+ };
+ ext_bin_7: ext_bin@7 {
+ status = "disabled";
+ samsung,name = "dummy.bin";
+ samsung,area = <1>;
+ samsung,offset = <0x800000>;
+ };
+ };
+
+ udc: usb@13200000 {
+ compatible = "samsung,exynos-dwusb";
+ clocks = <&clock GATE_USB30DRD_QCH_USB30>;
+ clock-names = "hsdrd";
+ reg = <0x0 0x13200000 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ usbdrd_dwc3: dwc3 {
+ compatible = "synopsys,dwc3";
+ reg = <0x0 0x13200000 0x10000>;
+ interrupts = <0 186 0>;
+ //suspend_clk_freq = <66000000>;
+ tx-fifo-resize = <0>;
+ adj-sof-accuracy = <0>;
+ is_not_vbus_pad = <1>;
+ enable_sprs_transfer = <1>;
+ qos_int_level = <100000 200000>;
+ phys = <&usbdrd_phy 0>, <&usbdrd3_phy 1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ /* check susphy support */
+ xhci_l2_support = <0>;
+ /* support usb audio offloading: 1, if not: 0 */
+ usb_audio_offloading = <0>;
+ /* don't support USB L2 sleep */
+ ldos = <0>;
+ /*
+ * dis-u2-freeclk-exists-quirk, dis_u2_susphy_quirk are alternative.
+ * One of them should be selected
+ */
+ snps,dis-u2-freeclk-exists-quirk;
+ /* snps,dis_u2_susphy_quirk; */
+ };
+ };
+
+ usbdrd_phy: phy@131D0000 {
+ compatible = "samsung,exynos-usbdrd-phy";
+ reg = <0x0 0x131D0000 0x200>;
+ clocks = <&clock GATE_USB30DRD_QCH_USB30>, <&clock GATE_USB30DRD_QCH_USBPHY_20CTRL>,
+ <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_0>, <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_1>,
+ <&clock OSCCLK>;
+ clock-names = "hsdrd", "usb20", "usb30_0", "usb30_1", "oscclk";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ pmu_mask = <0x3>;
+ pmu_offset = <0x704>;
+ //pmu_offset_dp = <0x66c>;
+
+ /* USBDP combo phy version - 0x200 */
+ phy_version = <0x300>;
+ /* if it doesn't need phy user mux, */
+ /* you should write "none" */
+ /* but refclk shouldn't be omitted */
+ phyclk_mux = "none";
+ phy_refclk = "oscclk";
+
+ /* if Main phy has the other phy, it must be set to 1. jusf for usbphy_info */
+ has_other_phy = <0>;
+ /* if combo phy is used, it must be set to 1. usbphy_sub_info is enabled */
+ has_combo_phy = <0>;
+ sub_phy_version = <0x300>;
+
+ /* ip type */
+ /* USB3DRD = 0 */
+ /* USB3HOST = 1 */
+ /* USB2DRD = 2 */
+ /* USB2HOST = 3 */
+ ip_type = <0x2>;
+
+ /* for PHY CAL */
+ /* choice only one item */
+ phy_refsel_clockcore = <1>;
+ phy_refsel_ext_osc = <0>;
+ phy_refsel_xtal = <0>;
+ phy_refsel_diff_pad = <0>;
+ phy_refsel_diff_internal = <0>;
+ phy_refsel_diff_single = <0>;
+
+ /* true : 1 , false : 0 */
+ use_io_for_ovc = <0>;
+ common_block_disable = <1>;
+ is_not_vbus_pad = <1>;
+ used_phy_port = <0>;
+
+ status = "disabled";
+
+ #phy-cells = <1>;
+ ranges;
+ };
+
+ usbdrd3_phy: phy@131F0000 {
+ compatible = "samsung,exynos-usbdrd-phy";
+ reg = <0x0 0x131F0000 0x1000>,
+ <0x0 0x131E0000 0x800>;
+ clocks = <&clock GATE_USB30DRD_QCH_USB30>, <&clock GATE_USB30DRD_QCH_USBPHY_20CTRL>,
+ <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_0>, <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_1>,
+ <&clock OSCCLK>;
+ clock-names = "hsdrd", "usb20", "usb30_0", "usb30_1", "oscclk";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ pmu_mask = <0x3>;
+ pmu_offset = <0x704>;
+ //pmu_offset_dp = <0x66c>;
+
+ /* USBDP combo phy version - 0x200 */
+ phy_version = <0x530>;
+ /* if it doesn't need phy user mux, */
+ /* you should write "none" */
+ /* but refclk shouldn't be omitted */
+ phyclk_mux = "none";
+ phy_refclk = "oscclk";
+
+ /* if Main phy has the other phy, it must be set to 1. jusf for usbphy_info */
+ has_other_phy = <1>;
+ /* if combo phy is used, it must be set to 1. usbphy_sub_info is enabled */
+ has_combo_phy = <0>;
+ sub_phy_version = <0x300>;
+
+ /* ip type */
+ /* USB3DRD = 0 */
+ /* USB3HOST = 1 */
+ /* USB2DRD = 2 */
+ /* USB2HOST = 3 */
+ ip_type = <0x0>;
+
+ /* for PHY CAL */
+ /* choice only one item */
+ phy_refsel_clockcore = <1>;
+ phy_refsel_ext_osc = <0>;
+ phy_refsel_xtal = <0>;
+ phy_refsel_diff_pad = <0>;
+ phy_refsel_diff_internal = <0>;
+ phy_refsel_diff_single = <0>;
+
+ /* true : 1 , false : 0 */
+ use_io_for_ovc = <0>;
+ common_block_disable = <1>;
+ is_not_vbus_pad = <1>;
+ used_phy_port = <0>;
+
+ status = "disabled";
+
+ #phy-cells = <1>;
+ ranges;
+ };
+
+
+ iommu-domain_dpu {
+ compatible = "samsung,exynos-iommu-bus";
+ #dma-address-cells = <1>;
+ #dma-size-cells = <1>;
+ ranges;
+
+ /* start address, size */
+ dma-window = <0x10000000 0xEFFF0000>;
+
+ domain-clients = <&dsim_0>;
+ };
+
+ iommu-domain_vipx {
+ compatible = "samsung,exynos-iommu-bus";
+
+ /* #address-cells = <2>; */
+ /* #size-cells = <1>; */
+ /* ranges; */
+ #dma-address-cells = <1>;
+ #dma-size-cells = <1>;
+ dma-window = <0x40000000 0xA0000000>;
+
+ domain-clients = <&vipx>, <&vipx_vertex>;
};
iommu-domain_abox {
#size-cells = <1>;
ranges;
- domain-clients = <>;
+ domain-clients = <&abox>;
};
iommu-domain_isp {
#size-cells = <1>;
ranges;
- domain-clients = <>;
+ domain-clients = <&fimc_is>, <&fimc_is_sensor0>, <&fimc_is_sensor1>,
+ <&fimc_is_sensor2>, <&fimc_is_sensor3>, <&camerapp_gdc>;
};
iommu-domain_mfc {
#size-cells = <1>;
ranges;
- domain-clients = <>;
+ domain-clients = <&mfc_0>;
};
iommu-domain_g2dmscljpeg {
#size-cells = <1>;
ranges;
- domain-clients = <>;
+ domain-clients = <&fimg2d>, <&scaler_0>, <&smfc>;
+ };
+
+ fimg2d: g2d@12E40000 {
+ compatible = "samsung,exynos9610-g2d";
+ reg = <0x0 0x12E40000 0x9000>;
+ interrupts = <0 165 0>;
+ clock-names = "gate";
+ clocks = <&clock GATE_G2D_QCH>;
+ iommus = <&sysmmu_g2d>;
+ hw_ppc =
+ /* sc_up none x1 x1/4 x1/9 x1/16 */
+ <1700 1550 1100 1800 2550 3500 /* rgb32 non-rotated */
+ 1650 1350 1000 1500 2600 3250 /* rgb32 rotated */
+ 1500 1450 1300 1700 2550 5950 /* yuv2p non-rotated */
+ 1600 1000 950 1650 2600 3500 /* yuv2p rotated */
+ 1200 950 950 1350 1550 2050 /* 8+2 non-rotated */
+ 1250 450 450 1100 1450 1850 /* 8+2 rotated */
+ 1900>; /* colorfill */
+
+ g2d_dvfs_table = <667000 667000
+ 533000 533000
+ 400000 400000
+ 200000 200000
+ 100000 100000
+ >;
+ dma-coherent;
+ };
+
+ scaler_0: scaler@12E60000 {
+ compatible = "samsung,exynos5-scaler";
+ reg = <0x0 0x12E60000 0x3000>;
+ interrupts = <0 164 0>;
+ clocks = <&clock GATE_MSCL_QCH>;
+ clock-names = "gate";
+ iommus = <&sysmmu_g2d>;
+ };
+
+ smfc: smfc@12E30000 {
+ compatible = "samsung,exynos8890-jpeg";
+ dma-coherent;
+ reg = <0x0 0x12E30000 0x1000>;
+ interrupts = <0 163 0>;
+ clocks = <&clock GATE_JPEG_QCH>;
+ clock-names = "gate";
+ iommus = <&sysmmu_g2d>;
+ smfc,int_qos_minlock = <534000>;
+ };
+
+ /* mali */
+ mali: mali@11500000 {
+ compatible = "arm,mali";
+ reg = <0x0 0x11500000 0x5000>;
+ interrupts = <0 66 0>,
+ <0 67 0>,
+ <0 65 0>;
+ interrupt-names = "JOB", "MMU", "GPU";
+ g3d_cmu_cal_id = <ACPM_DVFS_G3D>;
+ samsung,power-domain = <&pd_g3d>;
+ g3d_genpd_name = "pd-g3d"; /*KC, RM: pd-g3d, LT,MK: pd-embedded_g3d*/
+ #cooling-cells = <2>; /* min followed by max */
+ governor = "interactive";
+ interactive_info = <764000 75 0>;
+ gpu_dvfs_table_size = <10 7>; /*<row col>*/
+ /* 8 columns freq down up stay mif little middle big */
+ gpu_dvfs_table = < 1053000 95 100 1 2093000 1638000 0
+ 949000 56 90 1 2093000 1638000 0
+ 839000 58 90 1 2093000 1638000 0
+ 764000 58 90 5 1794000 1534000 0
+ 683000 53 70 4 1539000 1456000 0
+ 572000 50 70 1 1539000 1456000 0
+ 455000 54 70 1 676000 702000 0
+ 385000 56 70 1 546000 598000 0
+ 338000 48 70 1 419000 403000 0
+ 260000 48 70 1 419000 403000 0 >;
+ gpu_sustainable_info = <0 0 0 0 0>;
+ gpu_pmqos_cpu_cluster_num = <2>;
+ gpu_pmu_status_reg_offset = <0x4064>;
+ gpu_pmu_status_local_pwr_mask = <0xF>; /*0x1 << 0*/
+ gpu_max_clock = <1053000>;
+ gpu_max_clock_limit = <1053000>;
+ gpu_min_clock = <260000>;
+ gpu_dvfs_start_clock = <260000>;
+ gpu_dvfs_bl_config_clock = <260000>;
+ gpu_default_voltage = <800000>;
+ gpu_cold_minimum_vol = <0>;
+ gpu_voltage_offset_margin = <37500>;
+ gpu_tmu_control = <1>;
+ gpu_temp_throttling_level_num = <6>;
+ gpu_temp_throttling = <764000 572000 455000 338000 260000 260000>;
+ gpu_power_coeff = <625>;
+ gpu_dvfs_time_interval = <5>; /*1 tick : 10ms*/
+ gpu_default_wakeup_lock = <1>;
+ gpu_bus_devfreq = <0>;
+ gpu_dynamic_abb = <0>;
+ gpu_early_clk_gating = <0>;
+ gpu_dvs = <0>;
+ gpu_inter_frame_pm = <0>;
+ gpu_perf_gathering = <0>;
+ gpu_runtime_pm_delay_time = <50>;
+ gpu_dvfs_polling_time = <10>;
+ gpu_pmqos_int_disable = <1>;
+ gpu_pmqos_mif_max_clock = <2093000>;
+ gpu_pmqos_mif_max_clock_base = <572000>;
+ gpu_cl_dvfs_start_base = <572000>;
+ gpu_debug_level = <3>; /*DEBUG(1) INFO(2) WARNING(3) ERROR(4)*/
+ gpu_trace_level = <8>; /*TRACE_ALL*/
+ gpu_bts_support = <1>;
+ gpu_mo_min_clock = <764000>;
+ gpu_boost_gpu_min_lock = <0>;
+ gpu_boost_egl_min_lock = <1248000>;
+ gpu_vk_boost_max_lock = <2000>; /* to activate vk boost, should set proper clock*/
+ gpu_vk_boost_mif_min_lock = <0>;
+ gpu_asv_cali_lock_val = <0>; /*Should check this value when MALI_ASV_CALIBRATION_SUPPORT is enabled*/
+ gpu_set_pmu_duration_reg = <0>; /* only for KC for now*/
+ gpu_set_pmu_duration_val = <0>; /* only for KC for now*/
+ };
+
+ reboot {
+ compatible = "exynos,reboot";
+ pmu_base = <0x11860000>;
+ };
+
+ schedutil_gov {
+ schedutil_domain0: domain@0 {
+ device_type = "schedutil-domain";
+ shared-cpus = "0-3";
+ enabled = <0>; /* Disabled */
+ qos_min_class = <3>;
+ };
+
+ schedutil_domain1: domain@1 {
+ device_type = "schedutil-domain";
+ shared-cpus = "4-7";
+ enabled = <1>; /* Enabled */
+ expired_time = <80>; /* 80ms */
+ qos_min_class = <5>;
+ };
+ };
+
+ schedutil {
+ domain@0 {
+ device_type = "freqvar-tune";
+ shared-cpus = "0-3";
+
+ boost_table = < 0 >;
+ up_rate_limit_table = < 5 >;
+ down_rate_limit_table = < 5 >;
+ upscale_ratio_table = < 80 >;
+ };
+
+ domain@1 {
+ device_type = "freqvar-tune";
+ shared-cpus = "4-7";
+
+ boost_table = < 0 >;
+ up_rate_limit_table = < 5 >;
+ down_rate_limit_table = < 5 >;
+ upscale_ratio_table = < 80 >;
+ };
+ };
+
+ cpufreq {
+ cpufreq_domain0: domain@0 {
+ device_type = "cpufreq-domain";
+ sibling-cpus = "0-3";
+ cal-id = <ACPM_DVFS_CPUCL0>;
+ dm-type = <DM_CPU_CL0>;
+
+ min-freq = <403000>;
+
+ /* PM QoS Class ID */
+ pm_qos-min-class = <3>;
+ pm_qos-max-class = <4>;
+
+ user-boost = <0>;
+
+ #cooling-cells = <2>; /* min followed by max */
+
+ dm-constraints {
+ mif-perf {
+ const-type = <CONSTRAINT_MIN>;
+ dm-type = <DM_MIF>;
+ /* cpu mif */
+ table = < 1742000 845000
+ 1638000 845000
+ 1534000 845000
+ 1456000 845000
+ 1326000 845000
+ 1222000 676000
+ 1118000 676000
+ 1053000 676000
+ 910000 676000
+ 806000 546000
+ 702000 546000
+ 598000 419000
+ 403000 0
+ >;
+ };
+ };
+ };
+
+ cpufreq_domain1: domain@1 {
+ device_type = "cpufreq-domain";
+ sibling-cpus = "4-7";
+ cal-id = <ACPM_DVFS_CPUCL1>;
+ dm-type = <DM_CPU_CL1>;
+
+ min-freq = <936000>;
+
+ /* PM QoS Class ID */
+ pm_qos-min-class = <5>;
+ pm_qos-max-class = <6>;
+
+ #cooling-cells = <2>; /* min followed by max */
+
+ dm-constraints {
+ mif-perf {
+ const-type = <CONSTRAINT_MIN>;
+ dm-type = <DM_MIF>;
+ /* cpu mif */
+ table = < 2314000 2093000
+ 2210000 2093000
+ 2184000 2093000
+ 2080000 2093000
+ 1976000 2093000
+ 1898000 2002000
+ 1768000 2002000
+ 1664000 1014000
+ 1508000 1014000
+ 1456000 845000
+ 1352000 845000
+ 1248000 676000
+ 1144000 676000
+ 1040000 546000
+ 936000 546000
+ 832000 546000
+ 728000 546000 >;
+ };
+ };
+ };
+ };
+
+ dwmmc_2: dwmmc2@13550000 {
+ compatible = "samsung,exynos-dw-mshc";
+ reg = <0x0 0x13550000 0x2000>;
+ reg-names = "dw_mmc";
+ interrupts = <0 147 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock MMC_CARD>;
+ clock-names = "ciu";
+ status = "disabled";
+ };
+
+ contexthub_0: contexthub {
+ compatible = "samsung,exynos-nanohub";
+ interrupts = <0 39 0>,<0 111 0>; /* INTREQ_MAILBOX_SHUB2AP, INTREQ_WDT_SHUB */
+ /* mailbox, sram, dumpgpr, chub reset & cub cpu reset, baaw_p_apm_shub, chub cpu clock */
+ reg = <0x0 0x11980000 0x200>,
+ <0x0 0x11200000 0x40000>,
+ <0x0 0x111f0000 0x100>,
+ <0x0 0x11863d20 0x10>,
+ <0x0 0x11100000 0x100>,
+ <0x0 0x11003010 0x10>;
+ reg-names = "mailbox", "sram", "dumpgpr",
+ "chub_reset", "chub_baaw", "cmu_chub_qch";
+ /* BAAW-P-APM-SHUB */
+ baaw,baaw-p-apm-chub = <0x40300 0x40800 0x11900>;
+ /* none, pass, os.checked.bin, Exynos9610.bin */
+ reset-mode = "block";
+ };
+
+ /* Secure log */
+ seclog {
+ compatible = "samsung,exynos-seclog";
+ interrupts = <0 455 0>;
+ };
+
+ /* tbase */
+ tee {
+ compatible = "samsung,exynos-tee";
+ interrupts = <0 454 0>;
+ };
+
+ baaw_p_wlbt: syscon@12050000 {
+ compatible = "baaw_p_wlbt", "syscon";
+ reg = <0x0 0x12050000 0xff>;
+ };
+
+ dbus_baaw: syscon@14C20000 {
+ compatible = "dbus_baaw", "syscon";
+ reg = <0x0 0x14C20000 0x300>;
+ };
+
+ pbus_baaw: syscon@14C30000 {
+ compatible = "pbus_baaw", "syscon";
+ reg = <0x0 0x14C30000 0x300>;
+ };
+
+ wlbt_remap_base: syscon@14C50000 {
+ compatible = "wlbt_remap", "syscon";
+ reg = <0x0 0x14C50000 0x300>;
+ };
+
+ boot_cfg: syscon@14C60000 {
+ compatible = "boot_cfg", "syscon";
+ reg = <0x0 0x14C60000 0x1200>;
+ };
+
+ /* MAILBOX_AP2WLBT */
+ scsc_wifibt: scsc_wifibt@119c0000 {
+ compatible = "samsung,scsc_wifibt";
+
+ pinctrl-names = "default";
+ pinctrl-0=<&WB2AP_FEMCTRL_WLBT_00 &WB2AP_FEMCTRL_WLBT_01>;
+
+ /* Mailbox Registers */
+ reg = <0x0 0x119c0000 0x180>;
+ /* 10.3.2 External GIC IRQ table */
+ //SPI[42] 74 BLK_ALIVE INTREQ__MAILBOX_WLBT2AP
+ //SPI[28] 60 BLK_ALIVE INTREQ__ALIVE_WLBT_ACTIVE
+ //SPI[72] 104 BLK_WLBT WB2AP_WDOG_RESET_REQ__ALV
+ //SPI[73] 105 BLK_WLBT WB2AP_CFG_REQ__ALV
+ interrupts = <0 42 4>, <0 28 4>, <0 72 4>, <0 73 4>;
+ interrupt-names = "MBOX","ALIVE","WDOG","CFG_REQ";
+ /* PMU alive handle */
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ samsung,baaw_p_wlbt-syscon-phandle = <&baaw_p_wlbt>;
+ samsung,dbus_baaw-syscon-phandle = <&dbus_baaw>;
+ samsung,pbus_baaw-syscon-phandle = <&pbus_baaw>;
+ samsung,wlbt_remap-syscon-phandle = <&wlbt_remap_base>;
+ samsung,boot_cfg-syscon-phandle = <&boot_cfg>;
+ /* MIF / INT / CL0 / CL1 */
+ /* this qos_table should be per-platform. Leave it here until we have multiple platfrom support */
+ qos_table = <
+ 419000 100000 403000 936000 /* SCSC_QOS_MIN */
+ 1014000 533000 910000 1664000 /* SCSC_QOS_MED */
+ 2093000 667000 1742000 2314000 /* SCSC_QOS_MAX */
+ >;
+ /* SMAPPER */
+ smapper_num_banks = <11>;
+ smapper_reg = <0x14c40000 0x10000>;
+ smapper_bank_table {
+ smapper_bank_0 {
+ bank_num = <0x0>;
+ fw_window_start = <0x82000000>;
+ fw_window_size = <0x100000>;
+ num_entries = <160>;
+ is_large = <1>;
+ };
+ smapper_bank_1 {
+ bank_num = <0x1>;
+ fw_window_start = <0x82100000>;
+ fw_window_size = <0x100000>;
+ num_entries = <160>;
+ is_large = <1>;
+ };
+ smapper_bank_2 {
+ bank_num = <0x2>;
+ fw_window_start = <0x82200000>;
+ fw_window_size = <0x100000>;
+ num_entries = <160>;
+ is_large = <1>;
+ };
+ smapper_bank_3 {
+ bank_num = <0x3>;
+ fw_window_start = <0x82300000>;
+ fw_window_size = <0x100000>;
+ num_entries = <160>;
+ is_large = <1>;
+ };
+ smapper_bank_4 {
+ bank_num = <0x4>;
+ fw_window_start = <0x83000000>;
+ fw_window_size = <0x100000>;
+ num_entries = <64>;
+ is_large = <0>;
+ };
+ smapper_bank_5 {
+ bank_num = <0x5>;
+ fw_window_start = <0x83100000>;
+ fw_window_size = <0x100000>;
+ num_entries = <64>;
+ is_large = <0>;
+ };
+ smapper_bank_6 {
+ bank_num = <0x6>;
+ fw_window_start = <0x83200000>;
+ fw_window_size = <0x100000>;
+ num_entries = <64>;
+ is_large = <0>;
+ };
+ smapper_bank_7 {
+ bank_num = <0x7>;
+ fw_window_start = <0x83300000>;
+ fw_window_size = <0x100000>;
+ num_entries = <64>;
+ is_large = <0>;
+ };
+ smapper_bank_8 {
+ bank_num = <0x8>;
+ fw_window_start = <0x83400000>;
+ fw_window_size = <0x100000>;
+ num_entries = <64>;
+ is_large = <0>;
+ };
+ smapper_bank_9 {
+ bank_num = <0x9>;
+ fw_window_start = <0x83500000>;
+ fw_window_size = <0x100000>;
+ num_entries = <64>;
+ is_large = <0>;
+ };
+ smapper_bank_10 {
+ bank_num = <0xa>;
+ fw_window_start = <0x83600000>;
+ fw_window_size = <0x100000>;
+ num_entries = <64>;
+ is_large = <0>;
+ };
+ };
+ };
+
+ fm@14AC0000 {
+ compatible = "samsung,exynos9610-fm";
+ reg = <0x0 0x14AC0000 0x2000>,
+ <0x0 0x14800800 0x10>;
+ clocks = <&clock MUX_AUD_FM>,
+ <&clock GATE_ABOX_QCH_FM>,
+ <&clock DOUT_CLK_AUD_FM>; /* mux_aud_fm, qch_fm, clk_aud_fm */
+ clock-names = "mux_aud_fm", "qch_fm", "clk_aud_fm";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ samsung,power-domain = <&pd_dispaud>;
+ without_elna = <1>;
+ status = "ok";
+ };
+
+ exynos-bcmdbg {
+ compatible = "samsung,exynos-bcm_dbg";
+
+ pd-name = "pd-trex", "pd-dispaud", "pd-g2d", "pd-mfc", "pd-isp",
+ "pd-cam", "pd-vipx1", "pd-vipx2", "pd-usb", "pd-fsys";
+
+ max_define_event = <PRE_DEFINE_EVT_MAX>;
+ bcm_cnt_nr = <4>;
+ /* define_event_index ev0 ev1 ev2 ev3 */
+ define_events = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x4 0x5 0x26 0x27>;
+ default_define_event = <PEAK_LATENCY_FMT_EVT>;
+
+ /* sm_id_mask sm_id_value */
+ define_filter_id = <NO_PRE_DEFINE_EVT 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0>;
+ /* ev0 ev1 ev2 ev3 */
+ define_filter_id_active = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x0 0x0>;
+ /* sm_other_type0 sm_other_mask0 sm_other_value0 */
+ define_filter_other_0 = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x0>;
+ /* sm_other_type1 sm_other_mask1 sm_other_value1 */
+ define_filter_other_1 = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x0>;
+ /* ev0 ev1 ev2 ev3 */
+ define_filter_other_active = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x0 0x0>;
+ /* peak_mask peak_id */
+ define_sample_id = <NO_PRE_DEFINE_EVT 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0>;
+ /* ev0 ev1 ev2 ev3 */
+ define_sample_id_enable = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x1 0x1>;
+ bcm_ip_nr = <31>;
+ initial_run_bcm_ip = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>,
+ <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>, <20>,
+ <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
+ initial_bcm_run = <BCM_STOP>;
+ /* msec (max 500msec) */
+ initial_period = <1>;
+ initial_bcm_mode = <BCM_MODE_INTERVAL>;
+ available_stop_owner = <PANIC_HANDLE CAMERA_DRIVER MODEM_IF ITMON_HANDLE>;
+ buff_size = <0x100000>;
+ };
+
+ vipx: vipx@10D60000 {
+ compatible = "samsung,exynos-vipx";
+ id = <0>;
+ reg = <0x0 0x10D60000 0x10000>, /* VIPX_CPU_SS1 */
+ <0x0 0x10F60000 0x10000>, /* VIPX_CPU_SS2 */
+ <0x0 0x10D90000 0x2000>, /* ITCM(8K) */
+ <0x0 0x10DA0000 0x4000>; /* DTCM(16K) */
+ pinctrl-names = "default","release";
+ pinctrl-0 = <>;
+ pinctrl-1 = <>;
+ clocks = <&clock UMUX_CLKCMU_VIPX1_BUS>,
+ <&clock GATE_VIPX1_QCH>,
+ <&clock UMUX_CLKCMU_VIPX2_BUS>,
+ <&clock GATE_VIPX2_QCH>,
+ <&clock GATE_VIPX2_QCH_LOCAL>;
+ clock-names = "UMUX_CLKCMU_VIPX1_BUS",
+ "GATE_VIPX1_QCH",
+ "UMUX_CLKCMU_VIPX2_BUS",
+ "GATE_VIPX2_QCH",
+ "GATE_VIPX2_QCH_LOCAL";
+
+ interrupts = <0 129 0>,
+ <0 130 0>;
+ iommus = <&sysmmu_vipx1>, <&sysmmu_vipx2>;
+ status = "ok";
+ };
+
+ vipx_vertex: vipx_vertex@10D60000 {
+ compatible = "samsung,exynos-vipx-vertex";
+ id = <0>;
+ reg = <0x0 0x10D60000 0x10000>, /* VIPX_CPU_SS1 */
+ <0x0 0x10F60000 0x10000>, /* VIPX_CPU_SS2 */
+ <0x0 0x10D90000 0x2000>, /* ITCM(8K) */
+ <0x0 0x10DA0000 0x4000>; /* DTCM(16K) */
+ pinctrl-names = "default","release";
+ pinctrl-0 = <>;
+ pinctrl-1 = <>;
+ clocks = <&clock UMUX_CLKCMU_VIPX1_BUS>,
+ <&clock GATE_VIPX1_QCH>,
+ <&clock UMUX_CLKCMU_VIPX2_BUS>,
+ <&clock GATE_VIPX2_QCH>,
+ <&clock GATE_VIPX2_QCH_LOCAL>;
+ clock-names = "UMUX_CLKCMU_VIPX1_BUS",
+ "GATE_VIPX1_QCH",
+ "UMUX_CLKCMU_VIPX2_BUS",
+ "GATE_VIPX2_QCH",
+ "GATE_VIPX2_QCH_LOCAL";
+
+ interrupts = <0 129 0>,
+ <0 130 0>;
+ iommus = <&sysmmu_vipx1>, <&sysmmu_vipx2>;
+ status = "ok";
};
};
projects / GitHub / MotorolaMobilityLLC / kernel-slsi.git / blobdiff