#include <dt-bindings/clock/exynos9610.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "exynos9610-pinctrl.dtsi"
-#include "exynos9610-display-lcd.dtsi"
+#include "exynos9610-rmem.dtsi"
+#include "exynos9610-debug.dtsi"
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/ufs/ufs.h>
#include "exynos9610-sysmmu.dtsi"
#include "exynos9610-pm-domains.dtsi"
#include <dt-bindings/soc/samsung/exynos9610-devfreq.h>
#include "exynos9610-mfc.dtsi"
-#include <dt-bindings/camera/fimc_is.h>
+#include "exynos9610-camera.dtsi"
+#include <dt-bindings/soc/samsung/exynos-bcm_dbg.h>
/ {
compatible = "samsung,armv8", "samsung,exynos9610";
uart6 = &serial_6;
uart7 = &serial_7;
fmp0 = &fmp_0;
+ contexthub0 = &contexthub_0;
dpp0 = &dpp_0;
dpp1 = &dpp_1;
dpp2 = &dpp_2;
mshc2 = &dwmmc_2;
};
+ ect {
+ parameter_address = <0x90000000>;
+ parameter_size = <0x19000>;
+ };
+
+ chosen {
+ bootargs = "swiotlb=512 console=ram rootwait ro init=/init clk_ignore_unused bcm_setup=0xffffff80f8e00000 androidboot.hardware=exynos9610 androidboot.debug_level=0x4948 firmware_class.path=/vendor/firmware ecd_setup=disable reserve-fimc=0xffffff80f9fe0000 pmic_info=0x3 ccic_info=0x1 epx_activate=true";
+ linux,initrd-start = <0x84000000>;
+ linux,initrd-end = <0x841FFFFF>;
+ };
+
chipid@10000000 {
compatible = "samsung,exynos9-chipid";
- reg = <0x0 0x10000000 0x100>;
+ reg = <0x0 0x10000000 0x100>, <0x0 0x2038848 0x10>;
+ };
+
+ arm-pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 82 4>,
+ <0 83 4>,
+ <0 84 4>,
+ <0 85 4>,
+ <0 96 4>,
+ <0 97 4>,
+ <0 98 4>,
+ <0 99 4>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
+ <&cpu3>, <&cpu4>, <&cpu5>,
+ <&cpu6>, <&cpu7>;
};
cpus {
ems {
/* Ontime Migration */
ontime {
- /* between little and middle */
- step0 {
- up-threshold = <215>;
- down-threshold = <170>;
- min-residency-us = <8192>;
+ /* little cores */
+ coregroup0 {
+ lower-boundary = <0>;
+ upper-boundary = <68>;
+ coverage-ratio = <100>;
+ };
+ /* big cores */
+ coregroup1 {
+ lower-boundary = <17>;
+ upper-boundary = <100>;
+ coverage-ratio = <75>;
};
};
overutil-level0 {
cpus = "0-3",
"4-7";
- ratio = <35>,
- <50>;
+ ratio = <30>,
+ <40>;
};
overutil-level1 {
cpus = "0-7";
ratio = <DEFAULT_RATIO>;
};
};
+
+ /* FRT Migration */
+ frt {
+ /* little cores */
+ coregroup0 {
+ coverage-ratio = <30>;
+ active-ratio = <25>;
+ };
+ /* big cores */
+ coregroup1 {
+ coverage-ratio = <15>;
+ active-ratio = <5>;
+ };
+ };
+
+ prefer-perf-service {
+ prefer-perf0 {
+ boost = <1>;
+ light-task-threshold = <0>;
+ prefer-cpus = "4-7", "0-3";
+ };
+ };
};
};
cp_call_psci_idx = <1024>; /* PSCI_SYSTEM_SLEEP */
usbl2_suspend_available = <1>;
usbl2_suspend_mode_idx = <12>; /* SYS_SLEEP_USB_ON */
- extra_wakeup_stat = <0x60c>;
conn_req_offset = <0x00c0>; /* PMU_ALIVE__CONNECT_SLEEP_STATUS */
+ pmu_cp_stat_offset = <0x38>; /* PMU_ALIVE__CP_STAT */
+ pmu_gnss_stat_offset = <0x48>; /* PMU_ALIVE__GNSS_STAT */
+ pmu_wlbt_stat_offset = <0x58>; /* PMU_ALIVE__WLBT_STAT */
+ stat_access_mif_offset = <4>; /* PMU_ALIVE__*_STAT__ACCESS_MIF */
+ /* WAKEUP_STAT WAKEUP_STAT4 */
+ wakeup_stat = <0x600>, <0x60c>;
+
+ wakeup_stats {
+ wakeup_stat {
+ ws-name =
+ "EINT", /* [ 0] */
+ "RTC_ALARM", /* [ 1] */
+ "RTC_TICK", /* [ 2] */
+ "TRTC_ALARM", /* [ 3] */
+ "TRTC_TICK", /* [ 4] */
+ "WLBT_RESET_REQ", /* [ 5] */
+ "WLBT_ACTIVE", /* [ 6] */
+ "RESERVED", /* [ 7] */
+ "RESERVED", /* [ 8] */
+ "MMC0", /* [ 9] */
+ "RESERVED", /* [10] */
+ "MMC2", /* [11] */
+ "CMGP_EINT", /* [12] */
+ "USB_REWA", /* [13] */
+ "TIMER", /* [14] */
+ "CP_SCAN_DUMP_REQ", /* [15] */
+ "USBDRD20", /* [16] */
+ "INT_MBOX_WLBT2AP", /* [17] */
+ "INT_MBOX_SHUB2AP", /* [18] */
+ "INT_MBOX_APM2AP", /* [19] */
+ "CP_RESET_REQ", /* [20] */
+ "GNSS_WAKEUP_REQ", /* [21] */
+ "GNSS_RESET_REQ", /* [22] */
+ "GNSS_ACTIVE", /* [23] */
+ "INT_MBOX_CP2AP", /* [24] */
+ "CP_ACTIVE", /* [25] */
+ "INT_MBOX_GNSS2AP", /* [26] */
+ "APM_CPU", /* [27] */
+ "RESERVED", /* [28] */
+ "INT_MBOX_CP2AP_S", /* [29] */
+ "RESERVED", /* [30] */
+ "RESERVED"; /* [31] */
+ };
+ wakeup_stat4 {
+ ws-name =
+ "RESERVED", /* [ 0] */
+ "INT_SHUB_WDT", /* [ 1] */
+ "SPEEDY2_DDI", /* [ 2] */
+ "UART_BT_CTS", /* [ 3] */
+ "UART_BT_RXD"; /* [ 4] */
+ };
+ };
};
exynos-powermode {
wakeup-masks {
+ /*
+ * wakeup_mask configuration
+ * SICD SICD_CPD AFTR STOP
+ * LPD LPA ALPA DSTOP
+ * SLEEP SLEEP_VTS_ON SLEEP_AUD_ON FAPO
+ * SLEEP_USB_L2
+ */
wakeup-mask {
- /*
- * wakeup_mask configuration
- * SICD SICD_CPD AFTR STOP
- * LPD LPA ALPA DSTOP
- * SLEEP SLEEP_VTS_ON SLEEP_AUD_ON FAPO
- * SLEEP_USB_L2
- */
- wakeup-mask {
- mask = <0x40000000>, <0x0>, <0x0>, <0x0>,
- <0x0>, <0x0>, <0x0>, <0x0>,
- <0xD00D7E7E>, <0x500D7E7E>, <0x500D7E7E>, <0x0>,
- <0xD00D7E7E>;
- mask-offset = <0x610>;
- stat-offset = <0x600>;
- };
- wakeup-mask2 {
- mask = <0x0>, <0x0>, <0x0>, <0x0>,
- <0x0>, <0x0>, <0x0>, <0x0>,
- <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>,
- <0xFFFF00FF>;
- mask-offset = <0x614>;
- stat-offset = <0x604>;
- };
- wakeup-mask3 {
- mask = <0x0>, <0x0>, <0x0>, <0x0>,
- <0x0>, <0x0>, <0x0>, <0x0>,
- <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>,
- <0xFFFF00FF>;
- mask-offset = <0x618>;
- stat-offset = <0x608>;
- };
- wakeup-mask4 {
- mask = <0x0>, <0x0>, <0x0>, <0x0>,
- <0x0>, <0x0>, <0x0>, <0x0>,
- <0x0>, <0x0>, <0x0>, <0x0>,
- <0x0>;
- mask-offset = <0x61c>;
- stat-offset = <0x610>;
- };
+ mask = <0x40000000>, <0x0>, <0x0>, <0x0>,
+ <0x0>, <0x0>, <0x0>, <0x0>,
+ <0xD0097E7E>, <0x50097E7E>, <0x50097E7E>, <0x0>,
+ <0xD0097E7E>;
+ mask-offset = <0x610>;
+ stat-offset = <0x600>;
+ };
+ wakeup-mask2 {
+ mask = <0x0>, <0x0>, <0x0>, <0x0>,
+ <0x0>, <0x0>, <0x0>, <0x0>,
+ <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>,
+ <0xFFFF00FF>;
+ mask-offset = <0x614>;
+ stat-offset = <0x604>;
+ };
+ wakeup-mask3 {
+ mask = <0x0>, <0x0>, <0x0>, <0x0>,
+ <0x0>, <0x0>, <0x0>, <0x0>,
+ <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>,
+ <0xFFFF00FF>;
+ mask-offset = <0x618>;
+ stat-offset = <0x608>;
+ };
+ wakeup-mask4 {
+ mask = <0x0>, <0x0>, <0x0>, <0x0>,
+ <0x0>, <0x0>, <0x0>, <0x0>,
+ <0x0>, <0x0>, <0x0>, <0x0>,
+ <0x0>;
+ mask-offset = <0x61c>;
+ stat-offset = <0x610>;
};
};
};
compatible = "samsung,exynos-speedy";
reg = <0x0 0x11a10000 0x2000>;
interrupts = <0 37 0>;
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&speedy_bus>;
status = "disabled";
<0 170 0>, <0 171 0>, <0 172 0>,
<0 173 0>, <0 174 0>, <0 185 0>, <0 196 0>,
<0 197 0>, <0 226 0>, <0 227 0>, <0 228 0>,
- <0 269 0>, <0 270 0>, <0 272 0>, <0 278 0>,
+ <0 270 0>, <0 272 0>, <0 278 0>,
<0 318 0>, <0 319 0>;
+ WB2AP_FEMCTRL_WLBT_00: WB2AP_FEMCTRL_WLBT_00 {
+ samsung,pins = "gpm16-0";
+ samsung,pin-function = <0x6>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <3>;
+ };
+ WB2AP_FEMCTRL_WLBT_01: WB2AP_FEMCTRL_WLBT_01 {
+ samsung,pins = "gpm17-0";
+ samsung,pin-function = <0x6>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <3>;
+ };
+
wakeup-interrupt-controller {
compatible = "samsung,exynos7-wakeup-eint";
};
pinctrl-names = "default";
pinctrl-0 = <&uart0_bus>; /* or _bus_dual */
samsung,usi-serial-v2;
+ samsung,dbg-uart-ch;
+ samsung,dbg-uart-baud = <115200>;
+ samsung,dbg-word-len = <8>;
clocks = <&clock GATE_UART_QCH>, <&clock UART>;
clock-names = "gate_uart_clk0", "ipclk_uart0";
status = "disabled";
/* Delay time */
use_delay_time = "false";
- freq_info = <667000 100000 667000 100000 667000 100000>;
+ freq_info = <667000 100000 100000 100000 667000 100000>;
/* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
/* Booting value */
/* Delay time */
use_delay_time = "false";
- freq_info = <690000 650000 690000 650000 690000 650000>;
+ freq_info = <690000 650000 650000 650000 690000 650000>;
/* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
/* Booting value */
- boot_info = <40 640000>;
+ boot_info = <40 650000>;
/* boot_qos_timeout, boot_freq */
/* governor data */
/* Delay time */
use_delay_time = "false";
- freq_info = <533000 167000 533000 167000 533000 533000>;
+ freq_info = <533000 167000 167000 167000 533000 533000>;
/* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
/* Booting value */
/* Delay time */
use_delay_time = "false";
- freq_info = <690000 640000 690000 640000 690000 640000>;
+ freq_info = <690000 640000 640000 640000 700000 640000>;
/* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
/* Booting value */
"UFS_EMBD";
/* PM QoS for INT power domain */
-/* ufs-pm-qos-int = <400000>;*/
+ ufs-pm-qos-int = <533000>;
/* DMA coherent callback, should be coupled with 'ufs-sys' */
dma-coherent;
vcc-supply = <&ufs_fixed_vcc>;
vcc-fixed-regulator;
-
+ ufs-power-gpio = <&gpg4 0 0>;
+ ufs-reset-n-gpio = <&gpf0 1 0>;
/* ----------------------- */
/* 3. UFS EXYNOS */
};
};
- watchdog_cl0@10050000 {
+ watchdog_cl0@10050000 { //WDT_CPUCL0
compatible = "samsung,exynos7-wdt";
reg = <0x0 0x10050000 0x100>;
interrupts = <0 232 0>;
index = <0>; /* if little cluster then index is 0*/
};
+ watchdog_cl1@10060000 { //WDT_CPUCL1
+ compatible = "samsung,exynos8-wdt";
+ reg = <0x0 0x10060000 0x100>;
+ interrupts = <0 233 0>;
+ clocks = <&clock OSCCLK>, <&clock GATE_WDT_CLUSTER1_QCH>;
+ clock-names = "rate_watchdog", "gate_watchdog";
+ timeout-sec = <30>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ index = <1>; /* if little cluster then index is 0*/
+ use_multistage_wdt;
+ };
+
exynos_adc: adc@11C30000 {
compatible = "samsung,exynos-adc-v3";
reg = <0x0 0x11C30000 0x100>;
dpp_0: dpp@0x14884000 { /* GF */
compatible = "samsung,exynos9-dpp";
#pb-id-cells = <3>;
- /* DPP, DPU_DMA, DPU_DMA_COMMON */
+ /* DPU_DMA, DPP, DPU_DMA_COMMON */
reg = <0x0 0x14884000 0x1000>, <0x0 0x14895000 0x1000>, <0x0 0x14880000 0x110>;
/* DPU_DMA IRQ, DPP IRQ */
interrupts = <0 210 0>, <0 214 0>;
- attr = <0x50087>; /* DPP/IDMA/HDR10/FLIP/BLOCK/AFBC */
+ attr = <0x50007>; /* DPP/IDMA/FLIP/BLOCK/AFBC */
port = <0>; /* AXI port number */
+
+ /* HW restriction */
+ src_f_w = <16 65534 1>;
+ src_f_h = <16 8190 1>;
+ src_w = <16 2560 1>;
+ src_h = <16 3040 1>;
+ src_xy_align = <1 1>;
+
+ dst_f_w = <16 8190 1>;
+ dst_f_h = <16 8190 1>;
+ dst_w = <16 2560 1>;
+ dst_h = <16 3040 1>;
+ dst_xy_align = <1 1>;
+
+ blk_w = <4 2560 1>;
+ blk_h = <1 3040 1>;
+ blk_xy_align = <1 1>;
+
+ src_h_rot_max = <2160>;
};
dpp_1: dpp@0x14883000 { /* VG0 */
clocks = <&clock UMUX_CLKCMU_DISPAUD_BUS>;
memory-region = <&fb_rmem>;
+ ddi_id = <0xffffffff>;
};
decon_f: decon_f@0x148B0000 {
/* pixel per clock */
ppc = <2>;
+ chip_ver = <9610>;
+
+ dpp_cnt = <4>;
+ dsim_cnt = <2>;
+ decon_cnt = <3>;
+
#address-cells = <2>;
#size-cells = <1>;
ranges;
iommus = <&sysmmu_abox>;
pm_qos_int = <0 0 0 0 0>;
pm_qos_aud = <1180000 800000 590000 394000 0>;
+ pd_name = "pd-dispaud";
abox_rdma_0: abox_rdma@0x14A51000 {
compatible = "samsung,abox-rdma";
compatible = "samsung,abox-rdma";
reg = <0x0 0x14A51700 0x100>;
id = <7>;
- type = "realtime";
+ type = "normal";
};
abox_wdma_0: abox_wdma@0x14A52000 {
compatible = "samsung,abox-wdma";
reg = <0x0 0x14A52300 0x100>;
id = <3>;
- type = "normal";
+ type = "realtime";
};
abox_wdma_4: abox_wdma@0x14A52400 {
abox = <&abox>;
};
- abox_debug: abox_debug@0 {
+ abox_debug: abox-debug@0 {
compatible = "samsung,abox-debug";
memory-region = <&abox_rmem>;
reg = <0x0 0x0 0x0>;
samsung,offset = <0x502000>;
};
ext_bin_1: ext_bin@1 {
- status = "disabled";
+ status = "okay";
samsung,name = "AP_AUDIO_SLSI.bin";
samsung,area = <1>;
samsung,offset = <0x7F0000>;
};
ext_bin_2: ext_bin@2 {
- status = "disabled";
- samsung,name = "APBargeIn_AUDIO_SLSI.bin";
+ status = "okay";
+ samsung,name = "audio_se.bin";
samsung,area = <1>;
- samsung,offset = <0x7EC000>;
+ samsung,offset = <0x602000>;
};
ext_bin_3: ext_bin@3 {
status = "disabled";
iommu-domain_vipx {
compatible = "samsung,exynos-iommu-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- domain-clients = <>;
+ /* #address-cells = <2>; */
+ /* #size-cells = <1>; */
+ /* ranges; */
+ #dma-address-cells = <1>;
+ #dma-size-cells = <1>;
+ dma-window = <0x40000000 0xA0000000>;
+
+ domain-clients = <&vipx>, <&vipx_vertex>;
};
iommu-domain_abox {
smfc,int_qos_minlock = <534000>;
};
- /* G3D */
- mali: mali@11500000 {
- compatible = "arm,mali";
- reg = <0x0 0x11500000 0x5000>;
- interrupts = <0 66 0>, <0 67 0>, <0 65 0>;
- interrupt-names = "JOB", "MMU", "GPU";
- g3d_cmu_cal_id = <ACPM_DVFS_G3D>;
- samsung,power-domain = <&pd_g3d>;
- #cooling-cells = <2>; /* min followed by max */
- };
+ /* mali */
+ mali: mali@11500000 {
+ compatible = "arm,mali";
+ reg = <0x0 0x11500000 0x5000>;
+ interrupts = <0 66 0>,
+ <0 67 0>,
+ <0 65 0>;
+ interrupt-names = "JOB", "MMU", "GPU";
+ g3d_cmu_cal_id = <ACPM_DVFS_G3D>;
+ samsung,power-domain = <&pd_g3d>;
+ g3d_genpd_name = "pd-g3d"; /*KC, RM: pd-g3d, LT,MK: pd-embedded_g3d*/
+ #cooling-cells = <2>; /* min followed by max */
+ governor = "interactive";
+ interactive_info = <764000 75 0>;
+ gpu_dvfs_table_size = <10 7>; /*<row col>*/
+ /* 8 columns freq down up stay mif little middle big */
+ gpu_dvfs_table = < 1053000 95 100 1 2093000 1638000 0
+ 949000 56 90 1 2093000 1638000 0
+ 839000 58 90 1 2093000 1638000 0
+ 764000 58 90 5 1794000 1534000 0
+ 683000 53 70 4 1539000 1456000 0
+ 572000 50 70 1 1539000 1456000 0
+ 455000 54 70 1 676000 702000 0
+ 385000 56 70 1 546000 598000 0
+ 338000 48 70 1 419000 403000 0
+ 260000 48 70 1 419000 403000 0 >;
+ gpu_sustainable_info = <0 0 0 0 0>;
+ gpu_pmqos_cpu_cluster_num = <2>;
+ gpu_pmu_status_reg_offset = <0x4064>;
+ gpu_pmu_status_local_pwr_mask = <0xF>; /*0x1 << 0*/
+ gpu_max_clock = <1053000>;
+ gpu_max_clock_limit = <1053000>;
+ gpu_min_clock = <260000>;
+ gpu_dvfs_start_clock = <260000>;
+ gpu_dvfs_bl_config_clock = <260000>;
+ gpu_default_voltage = <800000>;
+ gpu_cold_minimum_vol = <0>;
+ gpu_voltage_offset_margin = <37500>;
+ gpu_tmu_control = <1>;
+ gpu_temp_throttling_level_num = <6>;
+ gpu_temp_throttling = <764000 572000 455000 338000 260000 260000>;
+ gpu_power_coeff = <625>;
+ gpu_dvfs_time_interval = <5>; /*1 tick : 10ms*/
+ gpu_default_wakeup_lock = <1>;
+ gpu_bus_devfreq = <0>;
+ gpu_dynamic_abb = <0>;
+ gpu_early_clk_gating = <0>;
+ gpu_dvs = <0>;
+ gpu_inter_frame_pm = <0>;
+ gpu_perf_gathering = <0>;
+ gpu_runtime_pm_delay_time = <50>;
+ gpu_dvfs_polling_time = <10>;
+ gpu_pmqos_int_disable = <1>;
+ gpu_pmqos_mif_max_clock = <2093000>;
+ gpu_pmqos_mif_max_clock_base = <572000>;
+ gpu_cl_dvfs_start_base = <572000>;
+ gpu_debug_level = <3>; /*DEBUG(1) INFO(2) WARNING(3) ERROR(4)*/
+ gpu_trace_level = <8>; /*TRACE_ALL*/
+ gpu_bts_support = <1>;
+ gpu_mo_min_clock = <764000>;
+ gpu_boost_gpu_min_lock = <0>;
+ gpu_boost_egl_min_lock = <1248000>;
+ gpu_vk_boost_max_lock = <2000>; /* to activate vk boost, should set proper clock*/
+ gpu_vk_boost_mif_min_lock = <0>;
+ gpu_asv_cali_lock_val = <0>; /*Should check this value when MALI_ASV_CALIBRATION_SUPPORT is enabled*/
+ gpu_set_pmu_duration_reg = <0>; /* only for KC for now*/
+ gpu_set_pmu_duration_val = <0>; /* only for KC for now*/
+ };
reboot {
compatible = "exynos,reboot";
pm_qos-min-class = <3>;
pm_qos-max-class = <4>;
+ user-boost = <0>;
+
#cooling-cells = <2>; /* min followed by max */
dm-constraints {
const-type = <CONSTRAINT_MIN>;
dm-type = <DM_MIF>;
/* cpu mif */
- table = < 1534000 845000
+ table = < 1742000 845000
+ 1638000 845000
+ 1534000 845000
1456000 845000
1326000 845000
1222000 676000
dm-type = <DM_CPU_CL1>;
min-freq = <936000>;
- max-freq = <2288000>;
/* PM QoS Class ID */
pm_qos-min-class = <5>;
const-type = <CONSTRAINT_MIN>;
dm-type = <DM_MIF>;
/* cpu mif */
- table = < 2392000 1794000
- 2288000 1794000
- 2184000 1794000
- 2080000 1539000
- 1976000 1539000
- 1898000 1539000
- 1768000 1352000
+ table = < 2314000 2093000
+ 2210000 2093000
+ 2184000 2093000
+ 2080000 2093000
+ 1976000 2093000
+ 1898000 2002000
+ 1768000 2002000
1664000 1014000
1508000 1014000
1456000 845000
status = "disabled";
};
- contexthub: contexthub_ipc@11980000 {
+ contexthub_0: contexthub {
compatible = "samsung,exynos-nanohub";
interrupts = <0 39 0>,<0 111 0>; /* INTREQ_MAILBOX_SHUB2AP, INTREQ_WDT_SHUB */
/* mailbox, sram, dumpgpr, chub reset & cub cpu reset, baaw_p_apm_shub, chub cpu clock */
/* BAAW-P-APM-SHUB */
baaw,baaw-p-apm-chub = <0x40300 0x40800 0x11900>;
/* none, pass, os.checked.bin, Exynos9610.bin */
- os-type = "os.checked.bin";
reset-mode = "block";
- clocks =
- /* SHUB */
- <&clock UMUX_CLKCMU_SHUB_BUS>,
- /* RPR0521, LIS3MDL */
- <&clock CMGP01_USI>,
- /* BMP280 */
- <&clock CMGP03_USI>,
- /* PRP0521, LIS3MDL, BMP280 are all I2C */
- <&clock CMGP_I2C>;
- clock-names =
- "chub_bus",
- "cmgp_usi01",
- "cmgp_usi03",
- "cmgp_i2c";
};
/* Secure log */
boot_cfg: syscon@14C60000 {
compatible = "boot_cfg", "syscon";
- reg = <0x0 0x14C60000 0x1100>;
+ reg = <0x0 0x14C60000 0x1200>;
};
/* MAILBOX_AP2WLBT */
scsc_wifibt: scsc_wifibt@119c0000 {
compatible = "samsung,scsc_wifibt";
+
+ pinctrl-names = "default";
+ pinctrl-0=<&WB2AP_FEMCTRL_WLBT_00 &WB2AP_FEMCTRL_WLBT_01>;
+
/* Mailbox Registers */
reg = <0x0 0x119c0000 0x180>;
/* 10.3.2 External GIC IRQ table */
/* MIF / INT / CL0 / CL1 */
/* this qos_table should be per-platform. Leave it here until we have multiple platfrom support */
qos_table = <
- 419000 100000 403000 728000 /* SCSC_QOS_MIN */
+ 419000 100000 403000 936000 /* SCSC_QOS_MIN */
1014000 533000 910000 1664000 /* SCSC_QOS_MED */
- 2093000 667000 1534000 2392000 /* SCSC_QOS_MAX */
+ 2093000 667000 1742000 2314000 /* SCSC_QOS_MAX */
>;
/* SMAPPER */
smapper_num_banks = <11>;
compatible = "samsung,exynos9610-fm";
reg = <0x0 0x14AC0000 0x2000>,
<0x0 0x14800800 0x10>;
- elna_gpio = <&gpg1 0 0x1>; /* FM_LNA_EN */
- pinctrl-names = "default";
- pinctrl-0 = <&fm_lna_en>;
clocks = <&clock MUX_AUD_FM>,
<&clock GATE_ABOX_QCH_FM>,
<&clock DOUT_CLK_AUD_FM>; /* mux_aud_fm, qch_fm, clk_aud_fm */
clock-names = "mux_aud_fm", "qch_fm", "clk_aud_fm";
- without_elna = <1>;
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,power-domain = <&pd_dispaud>;
+ without_elna = <1>;
status = "ok";
};
- fimc_is: fimc_is@144B0000 {
- compatible = "samsung,exynos5-fimc-is";
- #pb-id-cells = <6>;
- reg = <0x0 0x14490000 0x100>, /* CSIS COMMON DMA */
- <0x0 0x144B0000 0x10000>, /* FIMC-3AA0 */
- <0x0 0x144B0000 0x10000>, /* FIMC-3AA1 */
- <0x0 0x14600000 0x10000>, /* FIMC_ISP */
- <0x0 0x14640000 0x10000>, /* MC_SCALER */
- <0x0 0x14610000 0x10000>, /* FIMC-VRA (Set A) */
- <0x0 0x14620000 0x10000>, /* FIMC-VRA (Set B) */
- <0x0 0x14440000 0x10000>, /* PAFSTAT_CORE */
- <0x0 0x144A0000 0x10000>; /* PAFSTAT_RDMA0 */
- interrupts = <0 335 0>, /* 3AA0_0 */
- <0 336 0>, /* 3AA0_1 */
- <0 337 0>, /* 3AA1_0 */
- <0 338 0>, /* 3AA1_1 */
- <0 344 0>, /* ISP_0 */
- <0 345 0>, /* ISP_1 */
- <0 348 0>, /* MC_SC_0 */
- <0 346 0>, /* VRA_1 */
- <0 329 0>, /* PAFSTAT0 */
- <0 330 0>; /* PAFSTAT1 */
+ exynos-bcmdbg {
+ compatible = "samsung,exynos-bcm_dbg";
+
+ pd-name = "pd-trex", "pd-dispaud", "pd-g2d", "pd-mfc", "pd-isp",
+ "pd-cam", "pd-vipx1", "pd-vipx2", "pd-usb", "pd-fsys";
+
+ max_define_event = <PRE_DEFINE_EVT_MAX>;
+ bcm_cnt_nr = <4>;
+ /* define_event_index ev0 ev1 ev2 ev3 */
+ define_events = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x4 0x5 0x26 0x27>;
+ default_define_event = <PEAK_LATENCY_FMT_EVT>;
+
+ /* sm_id_mask sm_id_value */
+ define_filter_id = <NO_PRE_DEFINE_EVT 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0>;
+ /* ev0 ev1 ev2 ev3 */
+ define_filter_id_active = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x0 0x0>;
+ /* sm_other_type0 sm_other_mask0 sm_other_value0 */
+ define_filter_other_0 = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x0>;
+ /* sm_other_type1 sm_other_mask1 sm_other_value1 */
+ define_filter_other_1 = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x0>;
+ /* ev0 ev1 ev2 ev3 */
+ define_filter_other_active = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x0 0x0>;
+ /* peak_mask peak_id */
+ define_sample_id = <NO_PRE_DEFINE_EVT 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0>;
+ /* ev0 ev1 ev2 ev3 */
+ define_sample_id_enable = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0>,
+ <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x1 0x1>;
+ bcm_ip_nr = <31>;
+ initial_run_bcm_ip = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>,
+ <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>, <20>,
+ <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
+ initial_bcm_run = <BCM_STOP>;
+ /* msec (max 500msec) */
+ initial_period = <1>;
+ initial_bcm_mode = <BCM_MODE_INTERVAL>;
+ available_stop_owner = <PANIC_HANDLE CAMERA_DRIVER MODEM_IF ITMON_HANDLE>;
+ buff_size = <0x100000>;
+ };
+
+ vipx: vipx@10D60000 {
+ compatible = "samsung,exynos-vipx";
+ id = <0>;
+ reg = <0x0 0x10D60000 0x10000>, /* VIPX_CPU_SS1 */
+ <0x0 0x10F60000 0x10000>, /* VIPX_CPU_SS2 */
+ <0x0 0x10D90000 0x2000>, /* ITCM(8K) */
+ <0x0 0x10DA0000 0x4000>; /* DTCM(16K) */
pinctrl-names = "default","release";
pinctrl-0 = <>;
pinctrl-1 = <>;
- samsung,power-domain = <&pd_isp>;
- clocks = <&clock UMUX_CLKCMU_CAM_BUS>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_3AA>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_RDMA>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_SMMU>,
-
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS0>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS1>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS2>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS3>,
- <&clock CIS_CLK0>,
- <&clock CIS_CLK1>,
- <&clock CIS_CLK2>,
- <&clock CIS_CLK3>,
-
- <&clock UMUX_CLKCMU_ISP_BUS>,
- <&clock UMUX_CLKCMU_ISP_GDC>,
- <&clock UMUX_CLKCMU_ISP_VRA>,
- <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_ISP>,
- <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_MCSC>,
- <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_VRA>,
- <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_GDC>,
- <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0>,
- <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1>;
- clock-names = "UMUX_CLKCMU_CAM_BUS",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_3AA",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_RDMA",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_SMMU",
-
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS0",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS1",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS2",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS3",
- "CIS_CLK0",
- "CIS_CLK1",
- "CIS_CLK2",
- "CIS_CLK3",
-
- "UMUX_CLKCMU_ISP_BUS",
- "UMUX_CLKCMU_ISP_GDC",
- "UMUX_CLKCMU_ISP_VRA",
- "GATE_IS6P10P0_ISP_QCH_S_ISP_ISP",
- "GATE_IS6P10P0_ISP_QCH_S_ISP_MCSC",
- "GATE_IS6P10P0_ISP_QCH_S_ISP_VRA",
- "GATE_IS6P10P0_ISP_QCH_S_ISP_GDC",
- "GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0",
- "GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1";
+ clocks = <&clock UMUX_CLKCMU_VIPX1_BUS>,
+ <&clock GATE_VIPX1_QCH>,
+ <&clock UMUX_CLKCMU_VIPX2_BUS>,
+ <&clock GATE_VIPX2_QCH>,
+ <&clock GATE_VIPX2_QCH_LOCAL>;
+ clock-names = "UMUX_CLKCMU_VIPX1_BUS",
+ "GATE_VIPX1_QCH",
+ "UMUX_CLKCMU_VIPX2_BUS",
+ "GATE_VIPX2_QCH",
+ "GATE_VIPX2_QCH_LOCAL";
+
+ interrupts = <0 129 0>,
+ <0 130 0>;
+ iommus = <&sysmmu_vipx1>, <&sysmmu_vipx2>;
status = "ok";
- iommus = <&sysmmu_isp0>, <&sysmmu_isp1>, <&sysmmu_cam>;
- #cooling-cells = <2>; /* min followed by max */
};
- mipi_phy_csis_m4s4s4: dphy_m4s4s4_csis@0x14510800 {
- /* DCPHY 4.5 Gbps 4lane */
- compatible = "samsung,mipi-phy-m4s4-top";
- samsung,pmu-syscon = <&pmu_system_controller>;
- isolation = <0x70C 0x70C>; /* PMU address offset */
- reg = <0x0 0x14510800 0x4>; /* SYSREG address for reset */
- reset = <4 8>; /* reset bit */
- owner = <1>; /* 0: DSI, 1: CSI */
- #phy-cells = <1>;
- };
-
- mipi_phy_csis_m2s4s4s2: dphy_m2s4s4s2_csis@0x14510800 {
- /* DPHY 2.5 Gbps 4lane */
- compatible = "samsung,mipi-phy-m4s4-mod";
- samsung,pmu-syscon = <&pmu_system_controller>;
- isolation = <0x710 0x710 0x710>; /* PMU address offset */
- reset = <12 16 0>; /* reset bit */
- owner = <1>; /* 0: DSI, 1: CSI */
- #phy-cells = <1>;
- };
-
- fimc_is_sensor0: fimc_is_sensor@14400000 {
- /* REAR/CSIS0 */
- compatible = "samsung,exynos5-fimc-is-sensor";
- #pb-id-cells = <4>;
- reg = <0x0 0x14400000 0x700>, /* MIPI-CSI0 */
- <0x0 0x14400700 0x100>, /* PHY: TOP_M4S4S4 */
-
- <0x0 0x14450000 0x100>, /* VC0 DMA0 */
- <0x0 0x14450400 0x100>, /* VC0 DMA0 COMMON */
- <0x0 0x14450100 0x100>, /* VC1 DMA0 */
- <0x0 0x14450400 0x100>, /* VC1 DMA0 COMMON */
- <0x0 0x14450200 0x100>, /* VC2 DMA0 */
- <0x0 0x14450400 0x100>, /* VC2 DMA0 COMMON */
- <0x0 0x14450300 0x100>, /* VC3 DMA0 */
- <0x0 0x14450400 0x100>, /* VC3 DMA0 COMMON */
-
- <0x0 0x14450000 0x100>, /* VC0 DMA0 */
- <0x0 0x14450400 0x100>, /* VC0 DMA0 COMMON */
- <0x0 0x14460100 0x100>, /* VC1 DMA1 */
- <0x0 0x14460400 0x100>, /* VC1 DMA1 COMMON */
- <0x0 0x14460200 0x100>, /* VC2 DMA1 */
- <0x0 0x14460400 0x100>, /* VC2 DMA1 COMMON */
- <0x0 0x14460300 0x100>, /* VC3 DMA1 */
- <0x0 0x14460400 0x100>; /* VC3 DMA1 COMMON */
- interrupts = <0 325 0>, /* MIPI-CSI0 */
- <0 331 0>, /* VC0 DMA0 */
- <0 331 0>, /* VC1 DMA0 */
- <0 331 0>, /* VC2 DMA0 */
- <0 331 0>, /* VC3 DMA0 */
-
- <0 331 0>, /* VC0 DMA0 */
- <0 332 0>, /* VC1 DMA1 */
- <0 332 0>, /* VC2 DMA1 */
- <0 332 0>; /* VC3 DMA1 */
- samsung,power-domain = <&pd_cam>;
- phys = <&mipi_phy_csis_m4s4s4 0>;
- phy-names = "csis_dphy";
- clocks = <&clock CIS_CLK0>,
- <&clock CIS_CLK1>,
- <&clock CIS_CLK2>,
- <&clock CIS_CLK3>,
-
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS0>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS1>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS2>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS3>,
-
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3>;
- clock-names = "CIS_CLK0",
- "CIS_CLK1",
- "CIS_CLK2",
- "CIS_CLK3",
-
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS0",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS1",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS2",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS3",
-
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3";
- iommus = <&sysmmu_cam>;
- };
-
- fimc_is_sensor1: fimc_is_sensor@14410000 {
- /* FRONT/CSIS1 */
- compatible = "samsung,exynos5-fimc-is-sensor";
- #pb-id-cells = <4>;
- reg = <0x0 0x14410000 0x700>, /* MIPI-CSI0 */
- <0x0 0x14410700 0x100>, /* PHY: TOP_M2S4S4S2 */
-
- <0x0 0x14460000 0x100>, /* VC0 DMA1 */
- <0x0 0x14460400 0x100>, /* VC0 DMA1 COMMON */
- <0x0 0x14460100 0x100>, /* VC1 DMA1 */
- <0x0 0x14460400 0x100>, /* VC1 DMA1 COMMON */
- <0x0 0x14460200 0x100>, /* VC2 DMA1 */
- <0x0 0x14460400 0x100>, /* VC2 DMA1 COMMON */
- <0x0 0x14460300 0x100>, /* VC3 DMA1 */
- <0x0 0x14460400 0x100>, /* VC3 DMA1 COMMON */
-
- <0x0 0x14460000 0x100>, /* VC1 DMA1 */
- <0x0 0x14460400 0x100>, /* VC1 DMA1 COMMON */
- <0x0 0x14460100 0x100>, /* VC2 DMA1 */
- <0x0 0x14460400 0x100>, /* VC2 DMA1 COMMON */
- <0x0 0x14460200 0x100>, /* VC1 DMA1 */
- <0x0 0x14460400 0x100>, /* VC1 DMA1 COMMON */
- <0x0 0x14460300 0x100>, /* VC3 DMA1 */
- <0x0 0x14460400 0x100>; /* VC3 DMA1 COMMON */
- interrupts = <0 326 0>, /* MIPI-CSI1 */
- <0 332 0>, /* VC0 DMA1 */
- <0 332 0>, /* VC1 DMA1 */
- <0 332 0>, /* VC2 DMA1 */
- <0 332 0>, /* VC3 DMA1 */
-
- <0 332 0>, /* VC1 DMA2 */
- <0 332 0>, /* VC2 DMA1 */
- <0 332 0>, /* VC1 DMA1 */
- <0 332 0>; /* VC3 DMA1 */
- samsung,power-domain = <&pd_cam>;
- phys = <&mipi_phy_csis_m2s4s4s2 0>;
- phy-names = "csis_dphy";
- clocks = <&clock CIS_CLK0>,
- <&clock CIS_CLK1>,
- <&clock CIS_CLK2>,
- <&clock CIS_CLK3>,
-
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS0>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS1>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS2>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS3>,
-
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3>;
- clock-names = "CIS_CLK0",
- "CIS_CLK1",
- "CIS_CLK2",
- "CIS_CLK3",
-
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS0",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS1",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS2",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS3",
-
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3";
- iommus = <&sysmmu_cam>;
- };
-
- fimc_is_sensor2: fimc_is_sensor@14420000 {
- /* REAR2/CSIS2 */
- compatible = "samsung,exynos5-fimc-is-sensor";
- #pb-id-cells = <4>;
- reg = <0x0 0x14420000 0x700>, /* MIPI-CSI0 */
- <0x0 0x14420700 0x100>, /* PHY: TOP_M4S4S4_2nd */
-
- <0x0 0x14470000 0x100>, /* VC0 DMA2 */
- <0x0 0x14470400 0x100>, /* VC0 DMA2 COMMON */
- <0x0 0x14470100 0x100>, /* VC1 DMA2 */
- <0x0 0x14470400 0x100>, /* VC1 DMA2 COMMON */
- <0x0 0x14470200 0x100>, /* VC2 DMA2 */
- <0x0 0x14470400 0x100>, /* VC2 DMA2 COMMON */
- <0x0 0x14470300 0x100>, /* VC3 DMA2 */
- <0x0 0x14470400 0x100>; /* VC3 DMA2 COMMON */
- interrupts = <0 327 0>, /* MIPI-CSI2 */
- <0 333 0>, /* VC0 DMA2 */
- <0 333 0>, /* VC1 DMA2 */
- <0 333 0>, /* VC2 DMA2 */
- <0 333 0>; /* VC3 DMA2 */
- samsung,power-domain = <&pd_cam>;
- phys = <&mipi_phy_csis_m4s4s4 1>;
- phy-names = "csis_dphy";
- clocks = <&clock CIS_CLK0>,
- <&clock CIS_CLK1>,
- <&clock CIS_CLK2>,
- <&clock CIS_CLK3>,
-
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS0>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS1>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS2>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS3>,
-
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3>;
- clock-names = "CIS_CLK0",
- "CIS_CLK1",
- "CIS_CLK2",
- "CIS_CLK3",
-
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS0",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS1",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS2",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS3",
-
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3";
- iommus = <&sysmmu_cam>;
- };
-
- fimc_is_sensor3: fimc_is_sensor@14430000 {
- /* IRIS/CSIS3 */
- compatible = "samsung,exynos5-fimc-is-sensor";
- #pb-id-cells = <4>;
- reg = <0x0 0x14430000 0x0700>, /* MIPI-CSI0 */
- <0x0 0x14430700 0x100>, /* PHY: TOP_M2S4S4S2 */
-
- <0x0 0x14480000 0x100>, /* VC0 DMA3 */
- <0x0 0x14480400 0x100>, /* VC0 DMA3 COMMON */
- <0x0 0x14480100 0x100>, /* VC1 DMA3 */
- <0x0 0x14480400 0x100>, /* VC1 DMA3 COMMON */
- <0x0 0x14480200 0x100>, /* VC2 DMA3 */
- <0x0 0x14480400 0x100>, /* VC2 DMA3 COMMON */
- <0x0 0x14480300 0x100>, /* VC3 DMA3 */
- <0x0 0x14480400 0x100>; /* VC3 DMA3 COMMON */
- interrupts = <0 328 0>, /* MIPI-CSI3 */
- <0 334 0>, /* VC0 DMA3 */
- <0 334 0>, /* VC1 DMA3 */
- <0 334 0>, /* VC2 DMA3 */
- <0 334 0>; /* VC3 DMA3 */
- samsung,power-domain = <&pd_cam>;
- phys = <&mipi_phy_csis_m2s4s4s2 2>;
- phy-names = "csis_dphy";
- clocks = <&clock CIS_CLK0>,
- <&clock CIS_CLK1>,
- <&clock CIS_CLK2>,
- <&clock CIS_CLK3>,
-
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS0>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS1>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS2>,
- <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS3>,
-
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2>,
- <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3>;
- clock-names = "CIS_CLK0",
- "CIS_CLK1",
- "CIS_CLK2",
- "CIS_CLK3",
-
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS0",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS1",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS2",
- "GATE_DFTMUX_TOP_QCH_CLK_CSIS3",
-
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2",
- "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3";
- iommus = <&sysmmu_cam>;
- };
-
- fimc_is_pafstat0: fimc_is_pafstat@14440000 {
- /* PAFSTAT CORE0 */
- compatible = "samsung,exynos5-fimc-is-pafstat";
- reg = <0x0 0x14440000 0x1000>,
- <0x0 0x14448000 0x1000>; /* PAFSTAT CONTEXT0 */
- interrupts = <0 329 0>;
+ vipx_vertex: vipx_vertex@10D60000 {
+ compatible = "samsung,exynos-vipx-vertex";
id = <0>;
- };
-
- fimc_is_pafstat1: fimc_is_pafstat@14444000 {
- /* PDP CORE1 */
- compatible = "samsung,exynos5-fimc-is-pafstat";
- reg = <0x0 0x14444000 0x1000>,
- <0x0 0x1444C000 0x1000>; /* PAFSTAT CONTEXT1 */
- interrupts = <0 330 0>;
- id = <1>;
- };
-
- camerapp_gdc: gdc@14630000 {
- compatible = "samsung,exynos5-camerapp-gdc";
- #pb-id-cells = <6>;
- reg = <0x0 0x14630000 0x10000>; /* GDC */
- interrupts = <0 347 0>; /* GDC */
+ reg = <0x0 0x10D60000 0x10000>, /* VIPX_CPU_SS1 */
+ <0x0 0x10F60000 0x10000>, /* VIPX_CPU_SS2 */
+ <0x0 0x10D90000 0x2000>, /* ITCM(8K) */
+ <0x0 0x10DA0000 0x4000>; /* DTCM(16K) */
pinctrl-names = "default","release";
pinctrl-0 = <>;
pinctrl-1 = <>;
- camerapp_gdc,intcam_qos_minlock = <667000>;
- samsung,power-domain = <&pd_isp>;
- clocks = <&clock UMUX_CLKCMU_ISP_GDC>,
- <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_GDC>;
- clock-names = "gate",
- "gate2";
+ clocks = <&clock UMUX_CLKCMU_VIPX1_BUS>,
+ <&clock GATE_VIPX1_QCH>,
+ <&clock UMUX_CLKCMU_VIPX2_BUS>,
+ <&clock GATE_VIPX2_QCH>,
+ <&clock GATE_VIPX2_QCH_LOCAL>;
+ clock-names = "UMUX_CLKCMU_VIPX1_BUS",
+ "GATE_VIPX1_QCH",
+ "UMUX_CLKCMU_VIPX2_BUS",
+ "GATE_VIPX2_QCH",
+ "GATE_VIPX2_QCH_LOCAL";
+
+ interrupts = <0 129 0>,
+ <0 130 0>;
+ iommus = <&sysmmu_vipx1>, <&sysmmu_vipx2>;
status = "ok";
- iommus = <&sysmmu_isp0>;
- #cooling-cells = <2>; /* min followed by max */
};
};
projects / GitHub / MotorolaMobilityLLC / kernel-slsi.git / blobdiff