/* * SAMSUNG EXYNOS9610 SoC device tree source * * Copyright (c) 2017 Samsung Electronics Co., Ltd. * http://www.samsung.com * * SAMSUNG EXYNOS9610 SoC device nodes are listed in this file. * EXYNOS9610 based board files can include this file and provide * values for board specfic bindings. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include #include #include "exynos9610-pinctrl.dtsi" #include "exynos9610-display-lcd.dtsi" #include #include #include "exynos9610-sysmmu.dtsi" / { compatible = "samsung,armv8", "samsung,exynos9610"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <1>; aliases { pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; pinctrl3 = &pinctrl_3; pinctrl4 = &pinctrl_4; pinctrl5 = &pinctrl_5; usi0 = &usi_0_shub; usi1 = &usi_0_shub_i2c; usi2 = &usi_0_cmgp; usi3 = &usi_0_cmgp_i2c; usi4 = &usi_1_cmgp; usi5 = &usi_1_cmgp_i2c; usi6 = &usi_2_cmgp; usi7 = &usi_2_cmgp_i2c; usi8 = &usi_3_cmgp; usi9 = &usi_3_cmgp_i2c; usi10 = &usi_4_cmgp; usi11 = &usi_4_cmgp_i2c; usi12 = &usi_peri_uart; usi13 = &usi_peri_cami2c_0; usi14 = &usi_peri_cami2c_1; usi15 = &usi_peri_cami2c_2; usi16 = &usi_peri_cami2c_3; usi17 = &usi_peri_spi_0; usi18 = &usi_peri_spi_1; usi19 = &usi_peri_usi_0; usi20 = &usi_peri_usi_0_i2c; usi21 = &usi_peri_spi_2; hsi2c0 = &hsi2c_0; hsi2c1 = &hsi2c_1; hsi2c2 = &hsi2c_2; hsi2c3 = &hsi2c_3; hsi2c4 = &hsi2c_4; hsi2c5 = &hsi2c_5; hsi2c6 = &hsi2c_6; hsi2c7 = &hsi2c_7; hsi2c8 = &hsi2c_8; hsi2c9 = &hsi2c_9; hsi2c10 = &hsi2c_10; hsi2c11 = &hsi2c_11; hsi2c12 = &hsi2c_12; hsi2c13 = &hsi2c_13; hsi2c14 = &hsi2c_14; hsi2c15 = &hsi2c_15; hsi2c16 = &hsi2c_16; hsi2c17 = &hsi2c_17; spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; spi3 = &spi_3; spi4 = &spi_4; spi5 = &spi_5; spi6 = &spi_6; spi7 = &spi_7; spi8 = &spi_8; spi9 = &spi_9; uart0 = &serial_0; uart1 = &serial_1; uart2 = &serial_2; uart3 = &serial_3; uart4 = &serial_4; uart5 = &serial_5; uart6 = &serial_6; uart7 = &serial_7; dpp0 = &dpp_0; dpp1 = &dpp_1; dpp2 = &dpp_2; dpp3 = &dpp_3; dsim0 = &dsim_0; decon0 = &decon_f; }; chipid@10000000 { compatible = "samsung,exynos9-chipid"; reg = <0x0 0x10000000 0x100>; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu0: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ }; cpu1: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; }; cpu2: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; }; cpu3: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; }; cpu4: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a73", "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ }; cpu5: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a73", "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; }; cpu6: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a73", "arm,armv8"; reg = <0x0 0x102>; enable-method = "psci"; }; cpu7: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a73", "arm,armv8"; reg = <0x0 0x103>; enable-method = "psci"; }; }; psci { compatible = "arm,psci"; method = "smc"; cpu_suspend = <0xC4000001>; cpu_off = <0x84000002>; cpu_on = <0xC4000003>; }; gic:interrupt-controller@12300000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x0 0x12301000 0x1000>, <0x0 0x12302000 0x1000>, <0x0 0x12304000 0x2000>, <0x0 0x12306000 0x2000>; interrupts = <1 9 0xf04>; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , ; clock-frequency = <26000000>; use-clocksource-only; use-physical-timer; }; clock: clock-controller@0x12100000 { compatible = "samsung,exynos9610-clock"; reg = <0x0 0x12100000 0x8000>; #clock-cells = <1>; acpm-ipc-channel = <0>; }; mct@10040000 { compatible = "samsung,exynos4210-mct"; reg = <0x0 0x10040000 0x800>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&mct_map>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, <11>; clocks = <&clock OSCCLK>, <&clock GATE_MCT_QCH>; clock-names = "fin_pll", "mct"; use-clockevent-only; mct_map: mct-map { #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; interrupt-map = <0 &gic 0 234 0>, <1 &gic 0 235 0>, <2 &gic 0 236 0>, <3 &gic 0 237 0>, <4 &gic 0 238 0>, <5 &gic 0 239 0>, <6 &gic 0 240 0>, <7 &gic 0 241 0>, <8 &gic 0 242 0>, <9 &gic 0 243 0>, <10 &gic 0 244 0>, <11 &gic 0 245 0>; }; }; speedy@11a10000 { compatible = "samsung,exynos-speedy"; reg = <0x0 0x11a10000 0x2000>; interrupts = <0 37 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&speedy_bus>; status = "disabled"; }; acpm { compatible = "samsung,exynos-acpm"; #address-cells = <2>; #size-cells = <1>; acpm-ipc-channel = <4>; fvmap_offset = <0x6000>; reg = <0x0 0x11820000 0x1000>; /* TIMER_APM */ reg-names = "timer_apm"; peritimer-cnt = <0xFFFF>; }; acpm_ipc { compatible = "samsung,exynos-acpm-ipc"; #address-cells = <2>; #size-cells = <1>; interrupts = <0 38 0>; /* AP2APM MAILBOX SPI NUM*/ reg = <0x0 0x11900000 0x1000>, /* AP2APM MAILBOX */ <0x0 0x2039000 0x15000>; /* APM SRAM */ initdata-base = <0x6F00>; num-timestamps = <32>; debug-log-level = <0>; logging-period = <500>; dump-base = <0x203C000>; dump-size = <0x12000>; /* 72KB */ }; acpm_dvfs { compatible = "samsung,exynos-acpm-dvfs"; acpm-ipc-channel = <5>; }; /* ALIVE */ pinctrl_0: pinctrl@11850000 { compatible = "samsung,exynos9610-pinctrl"; reg = <0x0 0x11850000 0x1000>; interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; wakeup-interrupt-controller { compatible = "samsung,exynos7-wakeup-eint"; }; }; /* CMGP */ pinctrl_1: pinctrl@11C20000{ compatible = "samsung,exynos9610-pinctrl"; reg = <0x0 0x11C20000 0x1000>; interrupts = <0 142 0>, <0 143 0>, <0 144 0>, <0 145 0>, <0 158 0>, <0 159 0>, <0 160 0>, <0 161 0>, <0 162 0>, <0 170 0>, <0 171 0>, <0 172 0>, <0 173 0>, <0 174 0>, <0 185 0>, <0 196 0>, <0 197 0>, <0 226 0>, <0 227 0>, <0 228 0>, <0 269 0>, <0 270 0>, <0 272 0>, <0 278 0>, <0 318 0>, <0 319 0>; wakeup-interrupt-controller { compatible = "samsung,exynos7-wakeup-eint"; }; }; /* DISPAUD */ pinctrl_2: pinctrl@14A60000{ compatible = "samsung,exynos9610-pinctrl"; reg = <0x0 0x14A60000 0x1000>; }; /* FSYS */ pinctrl_3: pinctrl@13490000 { compatible = "samsung,exynos9610-pinctrl"; reg = <0x0 0x13490000 0x1000>; interrupts = <0 150 0>; }; /* TOP */ pinctrl_4: pinctrl@139B0000 { compatible = "samsung,exynos9610-pinctrl"; reg = <0x0 0x139B0000 0x1000>; interrupts = <0 266 0>; }; /* SHUB */ pinctrl_5: pinctrl@11080000{ compatible = "samsung,exynos9610-pinctrl"; reg = <0x0 0x11080000 0x1000>; interrupts = <0 116 0>; }; /* USI_SHUB_0 */ usi_0_shub: usi@11013000 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x11013000 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_SHUB_0_I2C */ usi_0_shub_i2c: usi@11013004 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x11013018 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_0_CMGP */ usi_0_cmgp: usi@11C12000 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x11C12000 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_0_CMGP_I2C */ usi_0_cmgp_i2c: usi@11C12004 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x11C12004 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_1_CMGP */ usi_1_cmgp: usi@11C12010 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x11C12010 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_1_CMGP_I2C */ usi_1_cmgp_i2c: usi@11C12014 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x11C12014 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_2_CMGP */ usi_2_cmgp: usi@11C12020 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x11C12020 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_2_CMGP_I2C */ usi_2_cmgp_i2c: usi@11C12024 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x11C12024 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_3_CMGP */ usi_3_cmgp: usi@11C12030 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x11C12030 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_3_CMGP_I2C */ usi_3_cmgp_i2c: usi@11C12034 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x11C12034 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_4_CMGP */ usi_4_cmgp: usi@11C12040 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x11C12040 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_4_CMGP_I2C */ usi_4_cmgp_i2c: usi@11C12044 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x11C12044 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_PERI_UART */ usi_peri_uart: usi@10011010 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x10011010 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_PERI_CAMI2C_0 */ usi_peri_cami2c_0: usi@10011020 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x10011020 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_PERI_CAMI2C_1 */ usi_peri_cami2c_1: usi@10011024 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x10011024 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_PERI_CAMI2C_2 */ usi_peri_cami2c_2: usi@10011028 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x10011028 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_PERI_CAMI2C_3 */ usi_peri_cami2c_3: usi@1001102C { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x1001102C 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_PERI_SPI_0 */ usi_peri_spi_0: usi@10011030 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x10011030 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_PERI_SPI_1 */ usi_peri_spi_1: usi@10011034 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x10011034 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_PERI_USI_0 */ usi_peri_usi_0: usi@1001103C { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x1001103C 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_PERI_USI_0_I2C */ usi_peri_usi_0_i2c: usi@10011040 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x10011040 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_PERI_SPI_2 */ usi_peri_spi_2: usi@10011038 { compatible = "samsung,exynos-usi-v2"; reg = <0x0 0x10011038 0x4>; /* usi_v2_mode = "i2c" or "spi" or "uart" */ status = "disabled"; }; /* USI_0_SHUB */ hsi2c_0: hsi2c@110C0000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x110C0000 0x1000>; interrupts = <0 112 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c0_bus>; clocks = <&clock MUX_SHUB_USI00>, <&clock GATE_USI_SHUB00_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gph0 0 0x1>; gpio_sda= <&gph0 1 0x1>; status = "disabled"; }; /* USI_0_SHUB_I2C */ hsi2c_1: hsi2c@110D0000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x110D0000 0x1000>; interrupts = <0 117 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c1_bus>; clocks = <&clock MUX_SHUB_I2C>, <&clock GATE_I2C_SHUB00_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gph0 2 0x1>; gpio_sda= <&gph0 3 0x1>; status = "disabled"; }; /* USI_0_CMGP */ hsi2c_2: hsi2c@11D00000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x11D00000 0x1000>; interrupts = <0 311 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c2_bus>; clocks = <&clock CMGP00_USI>, <&clock GATE_USI_CMGP00_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpm0 0 0x1>; gpio_sda= <&gpm1 0 0x1>; status = "disabled"; }; /* USI_0_CMGP_I2C */ hsi2c_3: hsi2c@11D10000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x11D10000 0x1000>; interrupts = <0 273 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c3_bus>; clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP00_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpm2 0 0x1>; gpio_sda= <&gpm3 0 0x1>; status = "disabled"; }; /* USI_1_CMGP */ hsi2c_4: hsi2c@11D20000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x11D20000 0x1000>; interrupts = <0 312 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c4_bus>; clocks = <&clock CMGP01_USI>, <&clock GATE_USI_CMGP01_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpm4 0 0x1>; gpio_sda= <&gpm5 0 0x1>; status = "disabled"; }; /* USI_1_CMGP_I2C */ hsi2c_5: hsi2c@11D30000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x11D30000 0x1000>; interrupts = <0 274 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c5_bus>; clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP01_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpm6 0 0x1>; gpio_sda= <&gpm7 0 0x1>; status = "disabled"; }; /* USI_2_CMGP */ hsi2c_6: hsi2c@11D40000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x11D40000 0x1000>; interrupts = <0 313 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c6_bus>; clocks = <&clock CMGP02_USI>, <&clock GATE_USI_CMGP02_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpm8 0 0x1>; gpio_sda= <&gpm9 0 0x1>; status = "disabled"; }; /* USI_2_CMGP_I2C */ hsi2c_7: hsi2c@11D50000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x11D50000 0x1000>; interrupts = <0 275 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c7_bus>; clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP02_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpm10 0 0x1>; gpio_sda= <&gpm11 0 0x1>; status = "disabled"; }; /* USI_3_CMGP */ hsi2c_8: hsi2c@11D60000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x11D60000 0x1000>; interrupts = <0 314 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c8_bus>; clocks = <&clock CMGP03_USI>, <&clock GATE_USI_CMGP03_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpm12 0 0x1>; gpio_sda= <&gpm13 0 0x1>; status = "disabled"; }; /* USI_3_CMGP_I2C */ hsi2c_9: hsi2c@11D70000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x11D70000 0x1000>; interrupts = <0 276 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c9_bus>; clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP03_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpm14 0 0x1>; gpio_sda= <&gpm15 0 0x1>; status = "disabled"; }; /* USI_4_CMGP */ hsi2c_10: hsi2c@11D80000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x11D80000 0x1000>; interrupts = <0 315 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c10_bus>; clocks = <&clock CMGP04_USI>, <&clock GATE_USI_CMGP04_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpm16 0 0x1>; gpio_sda= <&gpm17 0 0x1>; status = "disabled"; }; /* USI_4_CMGP_I2C */ hsi2c_11: hsi2c@11D90000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x11D90000 0x1000>; interrupts = <0 277 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c11_bus>; clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP04_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpm18 0 0x1>; gpio_sda= <&gpm19 0 0x1>; status = "disabled"; }; /* USI_PERI_CAMI2C_0 */ hsi2c_12: hsi2c@138A0000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x138A0000 0x1000>; interrupts = <0 257 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c12_bus>; clocks = <&clock I2C>, <&clock GATE_CAMI2C_0_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpc0 1 0x1>; gpio_sda= <&gpc0 0 0x1>; status = "disabled"; }; /* USI_PERI_CAMI2C_1 */ hsi2c_13: hsi2c@138B0000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x138B0000 0x1000>; interrupts = <0 258 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c13_bus>; clocks = <&clock I2C>, <&clock GATE_CAMI2C_1_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpc0 3 0x1>; gpio_sda= <&gpc0 2 0x1>; status = "disabled"; }; /* USI_PERI_CAMI2C_2 */ hsi2c_14: hsi2c@138C0000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x138C0000 0x1000>; interrupts = <0 259 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c14_bus>; clocks = <&clock I2C>, <&clock GATE_CAMI2C_2_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpc0 5 0x1>; gpio_sda= <&gpc0 4 0x1>; status = "disabled"; }; /* USI_PERI_CAMI2C_3 */ hsi2c_15: hsi2c@138D0000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x138D0000 0x1000>; interrupts = <0 260 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c15_bus>; clocks = <&clock I2C>, <&clock GATE_CAMI2C_3_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpc0 7 0x1>; gpio_sda= <&gpc0 6 0x1>; status = "disabled"; }; /* USI_PERI_USI_0 */ hsi2c_16: hsi2c@13920000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x13920000 0x1000>; interrupts = <0 267 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c16_bus>; clocks = <&clock USI_USI>, <&clock GATE_USI00_USI_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpc1 0 0x1>; gpio_sda= <&gpc1 1 0x1>; status = "disabled"; }; /* USI_PERI_USI_0_I2C */ hsi2c_17: hsi2c@13930000 { compatible = "samsung,exynos5-hsi2c"; samsung,check-transdone-int; default-clk = <200000000>; reg = <0x0 0x13930000 0x1000>; interrupts = <0 268 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&hsi2c17_bus>; clocks = <&clock USI_I2C>, <&clock GATE_USI00_I2C_QCH>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; samsung,scl-clk-stretching; samsung,usi-i2c-v2; gpio_scl= <&gpc1 2 0x1>; gpio_sda= <&gpc1 3 0x1>; status = "disabled"; }; /* USI_0_SHUB */ spi_0: spi@110C0000 { compatible = "samsung,exynos-spi"; reg = <0x0 0x110C0000 0x100>; samsung,spi-fifosize = <64>; interrupts = <0 112 0>; /* dma-mode; dmas = <&pdma0 25 &pdma0 24>; */ dma-names = "tx", "rx"; swap-mode; #address-cells = <1>; #size-cells = <0>; clocks = <&clock GATE_USI_SHUB00_QCH>, <&clock MUX_SHUB_USI00>; clock-names = "gate_spi_clk", "ipclk_spi0"; pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; status = "disabled"; }; /* USI_0_CMGP */ spi_1: spi@11D00000 { compatible = "samsung,exynos-spi"; reg = <0x0 0x11D00000 0x100>; samsung,spi-fifosize = <64>; interrupts = <0 311 0>; /* dma-mode; dmas = <&pdma0 25 &pdma0 24>; */ dma-names = "tx", "rx"; swap-mode; #address-cells = <1>; #size-cells = <0>; clocks = <&clock GATE_USI_CMGP00_QCH>, <&clock CMGP00_USI>; clock-names = "gate_spi_clk", "ipclk_spi0"; pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; status = "disabled"; }; /* USI_1_CMGP */ spi_2: spi@11D20000 { compatible = "samsung,exynos-spi"; reg = <0x0 0x11D20000 0x100>; samsung,spi-fifosize = <64>; interrupts = <0 312 0>; /* dma-mode; dmas = <&pdma0 25 &pdma0 24>; */ dma-names = "tx", "rx"; swap-mode; #address-cells = <1>; #size-cells = <0>; clocks = <&clock GATE_USI_CMGP01_QCH>, <&clock CMGP01_USI>; clock-names = "gate_spi_clk", "ipclk_spi0"; pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; status = "disabled"; }; /* USI_2_CMGP */ spi_3: spi@11D40000 { compatible = "samsung,exynos-spi"; reg = <0x0 0x11D40000 0x100>; samsung,spi-fifosize = <64>; interrupts = <0 313 0>; /* dma-mode; dmas = <&pdma0 25 &pdma0 24>; */ dma-names = "tx", "rx"; swap-mode; #address-cells = <1>; #size-cells = <0>; clocks = <&clock GATE_USI_CMGP02_QCH>, <&clock CMGP02_USI>; clock-names = "gate_spi_clk", "ipclk_spi0"; pinctrl-names = "default"; pinctrl-0 = <&spi3_bus>; status = "disabled"; }; /* USI_3_CMGP */ spi_4: spi@11D60000 { compatible = "samsung,exynos-spi"; reg = <0x0 0x11D60000 0x100>; samsung,spi-fifosize = <64>; interrupts = <0 314 0>; /* dma-mode; dmas = <&pdma0 25 &pdma0 24>; */ dma-names = "tx", "rx"; swap-mode; #address-cells = <1>; #size-cells = <0>; clocks = <&clock GATE_USI_CMGP03_QCH>, <&clock CMGP03_USI>; clock-names = "gate_spi_clk", "ipclk_spi0"; pinctrl-names = "default"; pinctrl-0 = <&spi4_bus>; status = "disabled"; }; /* USI_4_CMGP */ spi_5: spi@11D80000 { compatible = "samsung,exynos-spi"; reg = <0x0 0x11D80000 0x100>; samsung,spi-fifosize = <64>; interrupts = <0 315 0>; /* dma-mode; dmas = <&pdma0 25 &pdma0 24>; */ dma-names = "tx", "rx"; swap-mode; #address-cells = <1>; #size-cells = <0>; clocks = <&clock GATE_USI_CMGP04_QCH>, <&clock CMGP04_USI>; clock-names = "gate_spi_clk", "ipclk_spi0"; pinctrl-names = "default"; pinctrl-0 = <&spi5_bus>; status = "disabled"; }; /* USI_PERI_SPI_0 */ spi_6: spi@13900000 { compatible = "samsung,exynos-spi"; reg = <0x0 0x13900000 0x100>; samsung,spi-fifosize = <64>; interrupts = <0 254 0>; /* dma-mode; dmas = <&pdma0 19 &pdma0 18>; */ dma-names = "tx", "rx"; swap-mode; #address-cells = <1>; #size-cells = <0>; clocks = <&clock GATE_SPI_0_QCH>, <&clock SPI0>; clock-names = "gate_spi_clk", "ipclk_spi0"; pinctrl-names = "default"; pinctrl-0 = <&spi6_bus>; status = "disabled"; }; /* USI_PERI_SPI_1 */ spi_7: spi@13910000 { compatible = "samsung,exynos-spi"; reg = <0x0 0x13910000 0x100>; samsung,spi-fifosize = <64>; interrupts = <0 255 0>; /* dma-mode; dmas = <&pdma0 21 &pdma0 20>; */ dma-names = "tx", "rx"; swap-mode; #address-cells = <1>; #size-cells = <0>; clocks = <&clock GATE_SPI_1_QCH>, <&clock SPI1>; clock-names = "gate_spi_clk", "ipclk_spi0"; pinctrl-names = "default"; pinctrl-0 = <&spi7_bus>; status = "disabled"; }; /* USI_PERI_USI_0 */ spi_8: spi@13920000 { compatible = "samsung,exynos-spi"; reg = <0x0 0x13920000 0x100>; samsung,spi-fifosize = <64>; interrupts = <0 267 0>; /* dma-mode; dmas = <&pdma0 25 &pdma0 24>; */ dma-names = "tx", "rx"; swap-mode; #address-cells = <1>; #size-cells = <0>; clocks = <&clock GATE_USI00_USI_QCH>, <&clock USI_USI>; clock-names = "gate_spi_clk", "ipclk_spi0"; pinctrl-names = "default"; pinctrl-0 = <&spi8_bus>; status = "disabled"; }; /* SPI USI_PERI_SPI_2 */ spi_9: spi@13940000 { compatible = "samsung,exynos-spi"; reg = <0x0 0x13940000 0x100>; samsung,spi-fifosize = <256>; interrupts = <0 256 0>; /* dma-mode; dmas = <&pdma0 23 &pdma0 22>; */ dma-names = "tx", "rx"; swap-mode; #address-cells = <1>; #size-cells = <0>; clocks = <&clock GATE_SPI_2_QCH>, <&clock SPI2>; clock-names = "gate_spi_clk", "ipclk_spi0"; pinctrl-names = "default"; pinctrl-0 = <&spi9_bus>; status = "disabled"; }; /* USI_PERI_UART */ serial_0: uart@13820000 { compatible = "samsung,exynos-uart"; samsung,separate-uart-clk; reg = <0x0 0x13820000 0x100>; samsung,fifo-size = <256>; interrupts = <0 246 0>; pinctrl-names = "default"; pinctrl-0 = <&uart0_bus>; /* or _bus_dual */ samsung,usi-serial-v2; clocks = <&clock GATE_UART_QCH>, <&clock UART>; clock-names = "gate_uart_clk0", "ipclk_uart0"; status = "disabled"; }; /* USI_0_SHUB */ serial_1: uart@110C0000 { compatible = "samsung,exynos-uart"; samsung,separate-uart-clk; reg = <0x0 0x110C0000 0x100>; samsung,fifo-size = <64>; interrupts = <0 112 0>; pinctrl-names = "default"; pinctrl-0 = <&uart1_bus_single>; /* or _bus_dual */ samsung,usi-serial-v2; clocks = <&clock GATE_USI_SHUB00_QCH>, <&clock MUX_SHUB_USI00>; clock-names = "gate_uart_clk1", "ipclk_uart1"; status = "disabled"; }; /* USI_0_CMGP */ serial_2: uart@11D00000 { compatible = "samsung,exynos-uart"; samsung,separate-uart-clk; reg = <0x0 0x11D00000 0x100>; samsung,fifo-size = <64>; interrupts = <0 311 0>; pinctrl-names = "default"; pinctrl-0 = <&uart2_bus_single>; /* or _bus_dual */ samsung,usi-serial-v2; clocks = <&clock GATE_USI_CMGP00_QCH>, <&clock CMGP00_USI>; clock-names = "gate_uart_clk2", "ipclk_uart2"; status = "disabled"; }; /* USI_1_CMGP */ serial_3: uart@11D20000 { compatible = "samsung,exynos-uart"; samsung,separate-uart-clk; reg = <0x0 0x11D20000 0x100>; samsung,fifo-size = <64>; interrupts = <0 312 0>; pinctrl-names = "default"; pinctrl-0 = <&uart3_bus_single>; /* or _bus_dual */ samsung,usi-serial-v2; clocks = <&clock GATE_USI_CMGP01_QCH>, <&clock CMGP01_USI>; clock-names = "gate_uart_clk3", "ipclk_uart3"; status = "disabled"; }; /* USI_2_CMGP */ serial_4: uart@11D40000 { compatible = "samsung,exynos-uart"; samsung,separate-uart-clk; reg = <0x0 0x11D40000 0x100>; samsung,fifo-size = <64>; interrupts = <0 313 0>; pinctrl-names = "default"; pinctrl-0 = <&uart4_bus_single>; /* or _bus_dual */ samsung,usi-serial-v2; clocks = <&clock GATE_USI_CMGP02_QCH>, <&clock CMGP02_USI>; clock-names = "gate_uart_clk4", "ipclk_uart4"; status = "disabled"; }; /* USI_3_CMGP */ serial_5: uart@11D60000 { compatible = "samsung,exynos-uart"; samsung,separate-uart-clk; reg = <0x0 0x11D60000 0x100>; samsung,fifo-size = <64>; interrupts = <0 314 0>; pinctrl-names = "default"; pinctrl-0 = <&uart5_bus_single>; /* or _bus_dual */ samsung,usi-serial-v2; clocks = <&clock GATE_USI_CMGP03_QCH>, <&clock CMGP03_USI>; clock-names = "gate_uart_clk5", "ipclk_uart5"; status = "disabled"; }; /* USI_4_CMGP */ serial_6: uart@11D80000 { compatible = "samsung,exynos-uart"; samsung,separate-uart-clk; reg = <0x0 0x11D80000 0x100>; samsung,fifo-size = <64>; interrupts = <0 315 0>; pinctrl-names = "default"; pinctrl-0 = <&uart6_bus_single>; /* or _bus_dual */ samsung,usi-serial-v2; clocks = <&clock GATE_USI_CMGP04_QCH>, <&clock CMGP04_USI>; clock-names = "gate_uart_clk6", "ipclk_uart6"; status = "disabled"; }; /* USI_PERI_USI_0 */ serial_7: uart@13920000 { compatible = "samsung,exynos-uart"; samsung,separate-uart-clk; reg = <0x0 0x13920000 0x100>; samsung,fifo-size = <64>; interrupts = <0 267 0>; pinctrl-names = "default"; pinctrl-0 = <&uart7_bus_single>; /* or _bus_dual */ samsung,usi-serial-v2; clocks = <&clock GATE_USI00_USI_QCH>, <&clock USI_USI>; clock-names = "gate_uart_clk7", "ipclk_uart7"; status = "disabled"; }; /* I2C_0 */ i2c_0: i2c@13830000 { compatible = "samsung,s3c2440-i2c"; reg = <0x0 0x13830000 0x100>; interrupts = <0 247 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_bus>; clocks = <&clock GATE_I2C_0_QCH>, <&clock GATE_I2C_0_QCH>; clock-names = "rate_i2c", "gate_i2c"; status = "disabled"; }; /* I2C_1 */ i2c_1: i2c@13840000 { compatible = "samsung,s3c2440-i2c"; reg = <0x0 0x13840000 0x100>; interrupts = <0 248 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_bus>; clocks = <&clock GATE_I2C_1_QCH>, <&clock GATE_I2C_1_QCH>; clock-names = "rate_i2c", "gate_i2c"; status = "disabled"; }; /* I2C_2 */ i2c_2: i2c@13850000 { compatible = "samsung,s3c2440-i2c"; reg = <0x0 0x13850000 0x100>; interrupts = <0 249 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_bus>; clocks = <&clock GATE_I2C_2_QCH>, <&clock GATE_I2C_2_QCH>; clock-names = "rate_i2c", "gate_i2c"; status = "disabled"; }; /* I2C_3 */ i2c_3: i2c@13860000 { compatible = "samsung,s3c2440-i2c"; reg = <0x0 0x13860000 0x100>; interrupts = <0 250 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_bus>; clocks = <&clock GATE_I2C_3_QCH>, <&clock GATE_I2C_3_QCH>; clock-names = "rate_i2c", "gate_i2c"; status = "disabled"; }; /* I2C_4 */ i2c_4: i2c@13870000 { compatible = "samsung,s3c2440-i2c"; reg = <0x0 0x13870000 0x100>; interrupts = <0 251 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c4_bus>; clocks = <&clock GATE_I2C_4_QCH>, <&clock GATE_I2C_4_QCH>; clock-names = "rate_i2c", "gate_i2c"; status = "disabled"; }; /* I2C_5 */ i2c_5: i2c@13880000 { compatible = "samsung,s3c2440-i2c"; reg = <0x0 0x13880000 0x100>; interrupts = <0 252 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c5_bus>; clocks = <&clock GATE_I2C_5_QCH>, <&clock GATE_I2C_5_QCH>; clock-names = "rate_i2c", "gate_i2c"; status = "disabled"; }; /* I2C_6 */ i2c_6: i2c@13890000 { compatible = "samsung,s3c2440-i2c"; reg = <0x0 0x13890000 0x100>; interrupts = <0 253 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c6_bus>; clocks = <&clock GATE_I2C_6_QCH>, <&clock GATE_I2C_6_QCH>; clock-names = "rate_i2c", "gate_i2c"; status = "disabled"; }; tmuctrl_0: BIG@10070000 { compatible = "samsung,exynos9610-tmu"; reg = <0x0 0x10070000 0x700>; interrupts = <0 231 0>; tmu_name = "BIG"; id = <0>; sensors = <4>; /* P2 */ sensing_mode = "max"; hotplug_enable = <1>; hotplug_in_threshold = <91>; hotplug_out_threshold = <96>; #include "exynos9610-tmu-sensor-conf.dtsi" }; tmuctrl_1: LITTLE@10070000 { compatible = "samsung,exynos9610-tmu"; reg = <0x0 0x10070000 0x700>; interrupts = <0 231 0>; tmu_name = "LITTLE"; id = <1>; sensors = <2>; /* P1 */ sensing_mode = "max"; #include "exynos9610-tmu-sensor-conf.dtsi" }; tmuctrl_2: G3D@10070000 { compatible = "samsung,exynos9610-tmu"; reg = <0x0 0x10070000 0x700>; interrupts = <0 231 0>; tmu_name = "G3D"; id = <2>; sensors = <1>; /* P0 */ sensing_mode = "max"; #include "exynos9610-tmu-sensor-conf.dtsi" }; tmuctrl_3: ISP@10070000 { compatible = "samsung,exynos9610-tmu"; reg = <0x0 0x10070000 0x700>; interrupts = <0 231 0>; tmu_name = "ISP"; id = <3>; sensors = <2>; /* P1 */ sensing_mode = "max"; #include "exynos9610-tmu-sensor-conf.dtsi" }; fimc_is: dummy@1A000000 { }; acpm_tmu { acpm-ipc-channel = <7>; }; thermal-zones { big_thermal: BIG { zone_name = "BIG_THERMAL"; polling-delay-passive = <50>; polling-delay = <1000>; thermal-sensors = <&tmuctrl_0>; governor = "power_allocator"; sustainable-power = <0>; k_po = <0>; k_pu = <0>; k_i = <0>; i_max = <0>; integral_cutoff = <0>; trips { big_cold: big-cold { temperature = <20000>; hysteresis = <5000>; /* millicelsius */ type = "active"; }; big_switch_on: big-switch-on { temperature = <63000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "active"; }; big_control_temp: big-control-temp { temperature = <83000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "passive"; }; big_alert0: big-alert0 { temperature = <95000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; big_alert1: big-alert1 { temperature = <100000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; big_alert2: big-alert2 { temperature = <105000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; big_alert3: big-alert3 { temperature = <110000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; big_hot: big-hot { temperature = <115000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "hot"; }; }; cooling-maps { map0 { trip = <&big_control_temp>; cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; little_thermal: LITTLE { zone_name = "LITTLE_THERMAL"; polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tmuctrl_1>; trips { little_alert0: little-alert0 { temperature = <20000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; little_alert1: little-alert1 { temperature = <76000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; little_alert2: little-alert2 { temperature = <81000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; little_alert3: little-alert3 { temperature = <91000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; little_alert4: little-alert4 { temperature = <96000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; little_alert5: little-alert5 { temperature = <101000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; little_alert6: little-alert6 { temperature = <106000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; little_hot: little-hot { temperature = <115000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "hot"; }; }; cooling-maps { map0 { trip = <&little_alert0>; /* Corresponds to 1534MHz at freq_table */ cooling-device = <&cpu0 0 0>; }; map1 { trip = <&little_alert1>; /* Corresponds to 1326MHz at freq_table */ cooling-device = <&cpu0 0 0>; }; map2 { trip = <&little_alert2>; /* Corresponds to 1118MHz at freq_table */ cooling-device = <&cpu0 0 0>; }; map3 { trip = <&little_alert3>; /* Corresponds to 910MHz at freq_table */ cooling-device = <&cpu0 0 0>; }; map4 { trip = <&little_alert4>; /* Corresponds to 702MHz at freq_table */ cooling-device = <&cpu0 0 0>; }; map5 { trip = <&little_alert5>; /* Corresponds to 403MHz at freq_table */ cooling-device = <&cpu0 0 0>; }; map6 { trip = <&little_alert6>; /* Corresponds to 403MHz at freq_table */ cooling-device = <&cpu0 0 0>; }; map7 { trip = <&little_hot>; /* Corresponds to 403MHz at freq_table */ cooling-device = <&cpu0 0 0>; }; }; }; gpu_thermal: G3D { zone_name = "G3D_THERMAL"; polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tmuctrl_2>; governor = "power_allocator"; sustainable-power = <0>; k_po = <0>; k_pu = <0>; k_i = <0>; i_max = <0>; integral_cutoff = <0>; trips { gpu_cold: gpu-cold { temperature = <20000>; hysteresis = <5000>; /* millicelsius */ type = "active"; }; gpu_switch_on: gpu-switch-on { temperature = <80000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "active"; }; gpu_control_temp: gpu-control-temp { temperature = <88000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "passive"; }; gpu_alert0: gpu-alert0 { temperature = <95000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; gpu_alert1: gpu-alert1 { temperature = <100000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; gpu_alert2: gpu-alert2 { temperature = <105000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; gpu_alert3: gpu-alert3 { temperature = <110000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; gpu_hot: gpu-hot { temperature = <115000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "hot"; }; }; cooling-maps { map0 { trip = <&gpu_control_temp>; cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; isp_thermal: ISP { zone_name = "ISP_THERMAL"; polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tmuctrl_3>; trips { isp_alert0: isp-alert0 { temperature = <20000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; isp_alert1: isp-alert1 { temperature = <76000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; isp_alert2: isp-alert2 { temperature = <81000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; isp_alert3: isp-alert3 { temperature = <91000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; isp_alert4: isp-alert4 { temperature = <96000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; isp_alert5: isp-alert5 { temperature = <101000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; isp_alert6: isp-alert6 { temperature = <106000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; isp_hot: isp-hot { temperature = <115000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "hot"; }; }; cooling-maps { map0 { trip = <&isp_alert0>; /* Corresponds to No limit */ cooling-device = <&fimc_is 0 0>; }; map1 { trip = <&isp_alert1>; /* Corresponds to No limit */ cooling-device = <&fimc_is 0 0>; }; map2 { trip = <&isp_alert2>; /* Corresponds to 15fps at freq_table */ cooling-device = <&fimc_is 0 0>; }; map3 { trip = <&isp_alert3>; /* Corresponds to 5fps at freq_table */ cooling-device = <&fimc_is 0 0>; }; map4 { trip = <&isp_alert4>; /* Corresponds to 5fps at freq_table */ cooling-device = <&fimc_is 0 0>; }; map5 { trip = <&isp_alert5>; /* Corresponds to 5fps at freq_table */ cooling-device = <&fimc_is 0 0>; }; map6 { trip = <&isp_alert6>; /* Corresponds to 5fps at freq_table */ cooling-device = <&fimc_is 0 0>; }; map7 { trip = <&isp_hot>; /* Corresponds to HW trip */ cooling-device = <&fimc_is 0 0>; }; }; }; }; ufs: ufs@0x13520000 { /* ----------------------- */ /* 1. SYSTEM CONFIGURATION */ /* ----------------------- */ compatible ="samsung,exynos-ufs"; #address-cells = <2>; #size-cells = <1>; ranges; reg = <0x0 0x13520000 0x200>, /* 0: HCI standard */ <0x0 0x13521100 0x200>, /* 1: Vendor specificed */ <0x0 0x13510000 0x8000>, /* 2: UNIPRO */ <0x0 0x13530000 0x100>; /* 3: UFS protector */ interrupts = <0 157 0>; pinctrl-names = "default"; pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; clocks = /* aclk clock */ <&clock GATE_UFS_EMBD_QCH_UFS>, /* unipro clocks */ <&clock UFS_EMBD>; clock-names = /* aclk clocks */ "GATE_UFS_EMBD_QCH_UFS", /* unipro clocks */ "UFS_EMBD"; /* PM QoS for INT power domain */ /* ufs-pm-qos-int = <400000>;*/ /* DMA coherent callback, should be coupled with 'ufs-sys' */ dma-coherent; /* UFS PHY isolation and TCXO control */ samsung,pmu-phandle = <&pmu_system_controller>; /* TCXO exclusive control */ tcxo-ex-ctrl = <0>; /* UFS IO coherency */ samsung,sysreg-fsys-phandle = <&sysreg_fsys_system_controller>; /* ----------------------- */ /* 2. UFS COMMON */ /* ----------------------- */ freq-table-hz = <0 0>, <0 0>; vcc-supply = <&ufs_fixed_vcc>; vcc-fixed-regulator; /* ----------------------- */ /* 3. UFS EXYNOS */ /* ----------------------- */ hw-rev = ; /* power mode change */ ufs,pmd-attr-lane = /bits/ 8 <1>; ufs,pmd-attr-gear = /bits/ 8 <3>; /* hiberantion */ ufs-rx-min-activate-time-cap = <3>; ufs-rx-hibern8-time-cap = <2>; ufs-tx-hibern8-time-cap = <2>; /* board type for UFS CAL */ brd-for-cal = <0>; fmp-id = <0>; smu-id = <0>; /* ----------------------- */ /* 4. ADDITIONAL NODES */ /* ----------------------- */ ufs-phy { #address-cells = <2>; #size-cells = <1>; ranges; reg = <0x0 0x13524000 0x800>; }; ufs-dma-coherency { #address-cells = <2>; #size-cells = <1>; offset = <0x1010>; mask = <(BIT_8 | BIT_9)>; val = <(BIT_8 | BIT_9)>; }; }; ufs_fixed_vcc: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "ufs-vcc"; gpio = <&gpg4 0 0>; regulator-boot-on; enable-active-high; }; exynos-pmu { compatible = "samsung,exynos-pmu"; samsung,syscon-phandle = <&pmu_system_controller>; }; pmu_system_controller: system-controller@11860000 { compatible = "samsung,exynos9610-pmu", "syscon"; reg = <0x0 0x11860000 0x10000>; }; exynos-sysreg-fsys { compatible = "samsung,exynos-sysreg-fsys"; samsung,syscon-phandle = <&sysreg_fsys_system_controller>; }; sysreg_fsys_system_controller: system-controller@13410000 { compatible = "samsung,exynos9610-sysreg-fsys", "syscon"; reg = <0x0 0x13410000 0x1020>; }; /* DMA */ amba { #address-cells = <2>; #size-cells = <1>; compatible = "arm,amba-bus"; interrupt-parent = <&gic>; ranges; pdma0: pdma0@120C0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0x120C0000 0x1000>; interrupts = <0 294 0>; clocks = <&clock GATE_PDMA_CORE_QCH>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; #dma-multi-irq = <1>; dma-arwrapper = <0x120C4400>, <0x120C4420>, <0x120C4440>, <0x120C4460>, <0x120C4480>, <0x120C44A0>, <0x120C44C0>, <0x120C44E0>; dma-awwrapper = <0x120C4404>, <0x120C4424>, <0x120C4444>, <0x120C4464>, <0x120C4484>, <0x120C44A4>, <0x120C44C4>, <0x120C44E4>; dma-instwrapper = <0x120C4500>; dma-mask-bit = <36>; coherent-mask-bit = <36>; }; }; watchdog_cl0@10050000 { compatible = "samsung,exynos7-wdt"; reg = <0x0 0x10050000 0x100>; interrupts = <0 232 0>; clocks = <&clock OSCCLK>, <&clock GATE_WDT_CLUSTER0_QCH>; clock-names = "rate_watchdog", "gate_watchdog"; timeout-sec = <30>; samsung,syscon-phandle = <&pmu_system_controller>; index = <0>; /* if little cluster then index is 0*/ }; exynos_adc: adc@11C30000 { compatible = "samsung,exynos-adc-v3"; reg = <0x0 0x11C30000 0x100>; sysreg = <0x11C10000>; interrupts = <0 271 0>; #io-channel-cells = <1>; io-channel-ranges; clocks = <&clock GATE_ADC_CMGP_QCH_S0>; clock-names = "gate_adcif"; }; rtc@11A20000 { compatible = "samsung,exynos8-rtc"; reg = <0x0 0x11A20000 0x100>; interrupts = <0 29 0>, <0 30 0>; use-chub-only; }; sec_pwm: pwm@13970000 { compatible = "samsung,s3c6400-pwm"; reg = <0x0 0x13970000 0x1000>; samsung,pwm-outputs = <0>, <1>, <2>, <3>, <4>; #pwm-cells = <3>; clocks = <&clock GATE_PWM_MOTOR_QCH>, <&clock OSCCLK>; clock-names = "pwm_pclk", "pwm_sclk"; status = "ok"; }; dpp_0: dpp@0x14884000 { /* GF */ compatible = "samsung,exynos9-dpp"; #pb-id-cells = <3>; reg = <0x0 0x14884000 0x1000>, <0x0 0x14895000 0x1000>, <0x0 0x14880000 0x110>; interrupts = <0 210 0>, <0 214 0>; attr = <0x50087>; /* DPP/IDMA/HDR10/FLIP/BLOCK/AFBC */ }; dpp_1: dpp@0x14883000 { /* VG0 */ compatible = "samsung,exynos9-dpp"; #pb-id-cells = <3>; reg = <0x0 0x14883000 0x1000>, <0x0 0x14896000 0x1000>; interrupts = <0 211 0>, <0 215 0>; attr = <0x500B6>; /* DPP/IDMA/HDR10/SCALE/CSC/FLIP/BLOCK */ }; dpp_2: dpp@0x14881000 { /* G0 */ compatible = "samsung,exynos9-dpp"; #pb-id-cells = <3>; /* DPP, DPU_DMA, DPU_DMA_COMMON */ reg = <0x0 0x14881000 0x1000>, <0x0 0x14891000 0x1000>; /* DPU_DMA IRQ, DPP IRQ */ interrupts = <0 208 0>, <0 212 0>; attr = <0x50006>; /* DPP/IDMA/FLIP/BLOCK */ }; dpp_3: dpp@0x14882000 { /* G1 */ compatible = "samsung,exynos9-dpp"; #pb-id-cells = <3>; reg = <0x0 0x14882000 0x1000>, <0x0 0x14892000 0x1000>; interrupts = <0 209 0>, <0 213 0>; attr = <0x50006>; /* DPP/IDMA/FLIP/BLOCK */ }; disp_ss: disp_ss@0x14810000 { /* SYSREG_DISPAUD */ compatible = "samsung,exynos9-disp_ss"; reg = <0x0 0x14811000 0x10>; }; mipi_phy_dsim: phy_m4s4top_dsi0@0x11860000 { compatible = "samsung,mipi-phy-m4s4-top"; samsung,pmu-syscon = <&pmu_system_controller>; isolation = <0x070C>; /* PHY reset be controlled from DSIM */ /* reg = <0x0 0x14811008 0x4>; */ /* reset = <0 1>; */ /* init = <4 5>; */ /* PHY reset control path bit of SYSREG */ owner = <0>; /* 0: DSI, 1: CSI */ #phy-cells = <1>; }; dsim_0: dsim@0x148E0000 { compatible = "samsung,exynos9-dsim"; reg = <0x0 0x148E0000 0x100>; interrupts = <0 204 0>; iommus = <&sysmmu_dpu>; phys = <&mipi_phy_dsim 0>; phy-names = "dsim_dphy"; /* clock */ clock-names = "aclk"; clocks = <&clock UMUX_CLKCMU_DISPAUD_BUS>; }; decon_f: decon_f@0x148B0000 { compatible = "samsung,exynos9-decon"; /* exynos9810 */ #pb-id-cells = <4>; reg = <0x0 0x148B0000 0x10000>; /* interrupt num : FRAME_START, FRMAE_DONE, EXTRA, GPIO_PERIC1(EXT_INT_TE: GPD0[0]) */ interrupts = <0 199 0>, <0 200 0>, <0 203 0>, <0 266 0>; /* pinctrl */ pinctrl-names = "hw_te_on", "hw_te_off"; pinctrl-0 = <&decon_f_te_on>; pinctrl-1 = <&decon_f_te_off>; max_win = <4>; default_win = <0>; default_idma = <2>; psr_mode = <2>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */ trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */ dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */ /* 0: DSI, 1: eDP, 2:HDMI, 3: WB */ out_type = <0>; /* 0: DSI0, 1: DSI1, 2: DSI2 */ out_idx = <0>; #address-cells = <2>; #size-cells = <1>; ranges; /* EINT for TE */ gpios = <&gpc2 3 0xf>; /* sw te pending register */ te_eint { /* NWEINT_GPD0_PEND */ reg = <0x0 0x139B0a14 0x4>; }; cam-stat { /* ISPPRE_STATUS(0x1406404C), ISPHQ_STATUS(0x14064054), ISPLP_STATUS(0x1406405C) */ reg = <0x0 0x11864024 0x4>; }; }; udc: usb@13200000 { compatible = "samsung,exynos-dwusb"; clocks = <&clock GATE_USB30DRD_QCH_USB30>; clock-names = "hsdrd"; reg = <0x0 0x13200000 0x10000>; #address-cells = <2>; #size-cells = <1>; ranges; status = "disabled"; usbdrd_dwc3: dwc3 { compatible = "synopsys,dwc3"; reg = <0x0 0x13200000 0x10000>; interrupts = <0 186 0>; //suspend_clk_freq = <66000000>; tx-fifo-resize = <0>; adj-sof-accuracy = <0>; is_not_vbus_pad = <1>; enable_sprs_transfer = <1>; qos_int_level = <100000 200000>; phys = <&usbdrd_phy 0>, <&usbdrd3_phy 1>; phy-names = "usb2-phy", "usb3-phy"; /* check susphy support */ xhci_l2_support = <0>; /* support usb audio offloading: 1, if not: 0 */ usb_audio_offloading = <0>; /* don't support USB L2 sleep */ ldos = <0>; /* * dis-u2-freeclk-exists-quirk, dis_u2_susphy_quirk are alternative. * One of them should be selected */ snps,dis-u2-freeclk-exists-quirk; /* snps,dis_u2_susphy_quirk; */ }; }; usbdrd_phy: phy@131D0000 { compatible = "samsung,exynos-usbdrd-phy"; reg = <0x0 0x131D0000 0x200>; clocks = <&clock GATE_USB30DRD_QCH_USB30>, <&clock GATE_USB30DRD_QCH_USBPHY_20CTRL>, <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_0>, <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_1>, <&clock OSCCLK>; clock-names = "hsdrd", "usb20", "usb30_0", "usb30_1", "oscclk"; samsung,pmu-syscon = <&pmu_system_controller>; pmu_mask = <0x3>; pmu_offset = <0x704>; //pmu_offset_dp = <0x66c>; /* USBDP combo phy version - 0x200 */ phy_version = <0x300>; /* if it doesn't need phy user mux, */ /* you should write "none" */ /* but refclk shouldn't be omitted */ phyclk_mux = "none"; phy_refclk = "oscclk"; /* if Main phy has the other phy, it must be set to 1. jusf for usbphy_info */ has_other_phy = <0>; /* if combo phy is used, it must be set to 1. usbphy_sub_info is enabled */ has_combo_phy = <0>; sub_phy_version = <0x300>; /* ip type */ /* USB3DRD = 0 */ /* USB3HOST = 1 */ /* USB2DRD = 2 */ /* USB2HOST = 3 */ ip_type = <0x2>; /* for PHY CAL */ /* choice only one item */ phy_refsel_clockcore = <1>; phy_refsel_ext_osc = <0>; phy_refsel_xtal = <0>; phy_refsel_diff_pad = <0>; phy_refsel_diff_internal = <0>; phy_refsel_diff_single = <0>; /* true : 1 , false : 0 */ use_io_for_ovc = <0>; common_block_disable = <1>; is_not_vbus_pad = <1>; used_phy_port = <0>; status = "disabled"; #phy-cells = <1>; ranges; }; usbdrd3_phy: phy@131F0000 { compatible = "samsung,exynos-usbdrd-phy"; reg = <0x0 0x131F0000 0x1000>, <0x0 0x131E0000 0x800>; clocks = <&clock GATE_USB30DRD_QCH_USB30>, <&clock GATE_USB30DRD_QCH_USBPHY_20CTRL>, <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_0>, <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_1>, <&clock OSCCLK>; clock-names = "hsdrd", "usb20", "usb30_0", "usb30_1", "oscclk"; samsung,pmu-syscon = <&pmu_system_controller>; pmu_mask = <0x3>; pmu_offset = <0x704>; //pmu_offset_dp = <0x66c>; /* USBDP combo phy version - 0x200 */ phy_version = <0x530>; /* if it doesn't need phy user mux, */ /* you should write "none" */ /* but refclk shouldn't be omitted */ phyclk_mux = "none"; phy_refclk = "oscclk"; /* if Main phy has the other phy, it must be set to 1. jusf for usbphy_info */ has_other_phy = <1>; /* if combo phy is used, it must be set to 1. usbphy_sub_info is enabled */ has_combo_phy = <0>; sub_phy_version = <0x300>; /* ip type */ /* USB3DRD = 0 */ /* USB3HOST = 1 */ /* USB2DRD = 2 */ /* USB2HOST = 3 */ ip_type = <0x0>; /* for PHY CAL */ /* choice only one item */ phy_refsel_clockcore = <1>; phy_refsel_ext_osc = <0>; phy_refsel_xtal = <0>; phy_refsel_diff_pad = <0>; phy_refsel_diff_internal = <0>; phy_refsel_diff_single = <0>; /* true : 1 , false : 0 */ use_io_for_ovc = <0>; common_block_disable = <1>; is_not_vbus_pad = <1>; used_phy_port = <0>; status = "disabled"; #phy-cells = <1>; ranges; }; iommu-domain_dpu { compatible = "samsung,exynos-iommu-bus"; #address-cells = <2>; #size-cells = <1>; ranges; domain-clients = <&dsim_0>; }; iommu-domain_vipx { compatible = "samsung,exynos-iommu-bus"; #address-cells = <2>; #size-cells = <1>; ranges; domain-clients = <>; }; iommu-domain_abox { compatible = "samsung,exynos-iommu-bus"; #address-cells = <2>; #size-cells = <1>; ranges; domain-clients = <>; }; iommu-domain_isp { compatible = "samsung,exynos-iommu-bus"; #address-cells = <2>; #size-cells = <1>; ranges; domain-clients = <>; }; iommu-domain_mfc { compatible = "samsung,exynos-iommu-bus"; #address-cells = <2>; #size-cells = <1>; ranges; domain-clients = <>; }; iommu-domain_g2dmscljpeg { compatible = "samsung,exynos-iommu-bus"; #address-cells = <2>; #size-cells = <1>; ranges; domain-clients = <>; }; /* G3D */ mali: mali@11500000 { compatible = "arm,mali"; reg = <0x0 0x11500000 0x5000>; interrupts = <0 66 0>, <0 67 0>, <0 65 0>; interrupt-names = "JOB", "MMU", "GPU"; g3d_cmu_cal_id = ; /*samsung,power-domain = <&pd_g3d>;*/ #cooling-cells = <2>; /* min followed by max */ }; reboot { compatible = "exynos,reboot"; pmu_base = <0x11860000>; }; };