Commit | Line | Data |
---|---|---|
3c2a0909 S |
1 | /* |
2 | * Broadcom PCIE | |
3 | * Software-specific definitions shared between device and host side | |
4 | * Explains the shared area between host and dongle | |
5 | * | |
4c205efb | 6 | * Copyright (C) 1999-2018, Broadcom Corporation |
3c2a0909 S |
7 | * |
8 | * Unless you and Broadcom execute a separate written software license | |
9 | * agreement governing use of this software, this software is licensed to you | |
10 | * under the terms of the GNU General Public License version 2 (the "GPL"), | |
11 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | |
12 | * following added to such license: | |
13 | * | |
14 | * As a special exception, the copyright holders of this software give you | |
15 | * permission to link this software with independent modules, and to copy and | |
16 | * distribute the resulting executable under terms of your choice, provided that | |
17 | * you also meet, for each linked independent module, the terms and conditions of | |
18 | * the license of that module. An independent module is a module which is not | |
19 | * derived from this software. The special exception does not apply to any | |
20 | * modifications of the software. | |
21 | * | |
22 | * Notwithstanding the above, under no circumstances may you combine this | |
23 | * software in any way with any other Broadcom software provided under a license | |
24 | * other than the GPL, without Broadcom's express prior written consent. | |
25 | * | |
26 | * | |
27 | * <<Broadcom-WL-IPTag/Open:>> | |
28 | * | |
29 | * $Id: bcmpcie.h 678914 2017-01-11 15:34:26Z $ | |
30 | */ | |
31 | ||
32 | ||
33 | #ifndef _bcmpcie_h_ | |
34 | #define _bcmpcie_h_ | |
35 | ||
36 | #include <bcmutils.h> | |
37 | ||
38 | #define ADDR_64(x) (x.addr) | |
39 | #define HIGH_ADDR_32(x) ((uint32) (((sh_addr_t) x).high_addr)) | |
40 | #define LOW_ADDR_32(x) ((uint32) (((sh_addr_t) x).low_addr)) | |
41 | ||
42 | typedef struct { | |
43 | uint32 low_addr; | |
44 | uint32 high_addr; | |
45 | } sh_addr_t; | |
46 | ||
47 | ||
48 | /* May be overridden by 43xxxxx-roml.mk */ | |
49 | #if !defined(BCMPCIE_MAX_TX_FLOWS) | |
50 | #define BCMPCIE_MAX_TX_FLOWS 40 | |
51 | #endif /* ! BCMPCIE_MAX_TX_FLOWS */ | |
52 | ||
53 | #define PCIE_SHARED_VERSION_7 0x00007 | |
54 | #define PCIE_SHARED_VERSION_6 0x00006 /* rev6 is compatible with rev 5 */ | |
55 | #define PCIE_SHARED_VERSION_5 0x00005 /* rev6 is compatible with rev 5 */ | |
56 | /** | |
57 | * Feature flags enabled in dongle. Advertised by dongle to DHD via the PCIe Shared structure that | |
58 | * is located in device memory. | |
59 | */ | |
60 | #define PCIE_SHARED_VERSION PCIE_SHARED_VERSION_7 | |
61 | #define PCIE_SHARED_VERSION_MASK 0x000FF | |
62 | #define PCIE_SHARED_ASSERT_BUILT 0x00100 | |
63 | #define PCIE_SHARED_ASSERT 0x00200 | |
64 | #define PCIE_SHARED_TRAP 0x00400 | |
65 | #define PCIE_SHARED_IN_BRPT 0x00800 | |
66 | #define PCIE_SHARED_SET_BRPT 0x01000 | |
67 | #define PCIE_SHARED_PENDING_BRPT 0x02000 | |
68 | /* BCMPCIE_SUPPORT_TX_PUSH_RING 0x04000 obsolete */ | |
69 | #define PCIE_SHARED_EVT_SEQNUM 0x08000 | |
70 | #define PCIE_SHARED_DMA_INDEX 0x10000 | |
71 | ||
72 | /* WAR: D11 txstatus through unused status field of PCIe completion header */ | |
73 | #define PCIE_SHARED_D2H_D11_TX_STATUS 0x40000000 /* using flags2 in shared area */ | |
74 | #define PCIE_SHARED_H2D_D11_TX_STATUS 0x80000000 /* using flags2 in shared area */ | |
75 | ||
76 | /** | |
77 | * There are host types where a device interrupt can 'race ahead' of data written by the device into | |
78 | * host memory. The dongle can avoid this condition using a variety of techniques (read barrier, | |
79 | * using PCIe Message Signalled Interrupts, or by using the PCIE_DMA_INDEX feature). Unfortunately | |
80 | * these techniques have drawbacks on router platforms. For these platforms, it was decided to not | |
81 | * avoid the condition, but to detect the condition instead and act on it. | |
82 | * D2H M2M DMA Complete Sync mechanism: Modulo-253-SeqNum or XORCSUM | |
83 | */ | |
84 | #define PCIE_SHARED_D2H_SYNC_SEQNUM 0x20000 | |
85 | #define PCIE_SHARED_D2H_SYNC_XORCSUM 0x40000 | |
86 | #define PCIE_SHARED_D2H_SYNC_MODE_MASK \ | |
87 | (PCIE_SHARED_D2H_SYNC_SEQNUM | PCIE_SHARED_D2H_SYNC_XORCSUM) | |
88 | #define PCIE_SHARED_IDLE_FLOW_RING 0x80000 | |
89 | #define PCIE_SHARED_2BYTE_INDICES 0x100000 | |
90 | ||
91 | #define PCIE_SHARED2_EXTENDED_TRAP_DATA 0x00000001 /* using flags2 in shared area */ | |
92 | ||
93 | /* dongle supports fatal buf log collection */ | |
94 | #define PCIE_SHARED_FATAL_LOGBUG_VALID 0x200000 | |
95 | ||
96 | /* Implicit DMA with corerev 19 and after */ | |
97 | #define PCIE_SHARED_IDMA 0x400000 | |
98 | ||
99 | /* MSI support */ | |
100 | #define PCIE_SHARED_D2H_MSI_MULTI_MSG 0x800000 | |
101 | ||
102 | /* IFRM with corerev 19 and after */ | |
103 | #define PCIE_SHARED_IFRM 0x1000000 | |
104 | ||
105 | /** | |
106 | * From Rev6 and above, suspend/resume can be done using two handshake methods. | |
107 | * 1. Using ctrl post/ctrl cmpl messages (Default rev6) | |
108 | * 2. Using Mailbox data (old method as used in rev5) | |
109 | * This shared flag indicates whether to overide rev6 default method and use mailbox for | |
110 | * suspend/resume. | |
111 | */ | |
112 | #define PCIE_SHARED_USE_MAILBOX 0x2000000 | |
113 | ||
114 | /* Firmware compiled for mfgbuild purposes */ | |
115 | #define PCIE_SHARED_MFGBUILD_FW 0x4000000 | |
116 | ||
117 | /* Firmware could use DB0 value as host timestamp */ | |
118 | #define PCIE_SHARED_TIMESTAMP_DB0 0x8000000 | |
119 | /* Firmware could use Hostready (IPC rev7) */ | |
120 | #define PCIE_SHARED_HOSTRDY_SUPPORT 0x10000000 | |
121 | ||
122 | /* When set, Firmwar does not support OOB Device Wake based DS protocol */ | |
123 | #define PCIE_SHARED_NO_OOB_DW 0x20000000 | |
124 | ||
125 | /* When set, Firmwar supports Inband DS protocol */ | |
126 | #define PCIE_SHARED_INBAND_DS 0x40000000 | |
127 | ||
128 | /* Implicit DMA WAR for 4347B0 PCIe memory retention */ | |
129 | #define PCIE_SHARED_IDMA_RETENTION_DS 0x80000000 | |
130 | ||
131 | #define PCIE_SHARED_D2H_MAGIC 0xFEDCBA09 | |
132 | #define PCIE_SHARED_H2D_MAGIC 0x12345678 | |
133 | ||
134 | /** | |
135 | * Message rings convey messages between host and device. They are unidirectional, and are located | |
136 | * in host memory. | |
137 | * | |
138 | * This is the minimal set of message rings, known as 'common message rings': | |
139 | */ | |
140 | #define BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT 0 | |
141 | #define BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT 1 | |
142 | #define BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE 2 | |
143 | #define BCMPCIE_D2H_MSGRING_TX_COMPLETE 3 | |
144 | #define BCMPCIE_D2H_MSGRING_RX_COMPLETE 4 | |
145 | #define BCMPCIE_COMMON_MSGRING_MAX_ID 4 | |
146 | ||
147 | #define BCMPCIE_H2D_COMMON_MSGRINGS 2 | |
148 | #define BCMPCIE_D2H_COMMON_MSGRINGS 3 | |
149 | #define BCMPCIE_COMMON_MSGRINGS 5 | |
150 | ||
151 | #define BCMPCIE_H2D_MSGRINGS(max_tx_flows) \ | |
152 | (BCMPCIE_H2D_COMMON_MSGRINGS + (max_tx_flows)) | |
153 | ||
154 | /* different ring types */ | |
155 | #define BCMPCIE_H2D_RING_TYPE_CTRL_SUBMIT 0x1 | |
156 | #define BCMPCIE_H2D_RING_TYPE_TXFLOW_RING 0x2 | |
157 | #define BCMPCIE_H2D_RING_TYPE_RXBUFPOST 0x3 | |
158 | #define BCMPCIE_H2D_RING_TYPE_TXSUBMIT 0x4 | |
159 | #define BCMPCIE_H2D_RING_TYPE_DBGBUF_SUBMIT 0x5 | |
160 | ||
161 | #define BCMPCIE_D2H_RING_TYPE_CTRL_CPL 0x1 | |
162 | #define BCMPCIE_D2H_RING_TYPE_TX_CPL 0x2 | |
163 | #define BCMPCIE_D2H_RING_TYPE_RX_CPL 0x3 | |
164 | #define BCMPCIE_D2H_RING_TYPE_DBGBUF_CPL 0x4 | |
165 | #define BCMPCIE_D2H_RING_TYPE_AC_RX_COMPLETE 0x5 | |
166 | ||
167 | /** | |
168 | * H2D and D2H, WR and RD index, are maintained in the following arrays: | |
169 | * - Array of all H2D WR Indices | |
170 | * - Array of all H2D RD Indices | |
171 | * - Array of all D2H WR Indices | |
172 | * - Array of all D2H RD Indices | |
173 | * | |
174 | * The offset of the WR or RD indexes (for common rings) in these arrays are | |
175 | * listed below. Arrays ARE NOT indexed by a ring's id. | |
176 | * | |
177 | * D2H common rings WR and RD index start from 0, even though their ringids | |
178 | * start from BCMPCIE_H2D_COMMON_MSGRINGS | |
179 | */ | |
180 | ||
181 | #define BCMPCIE_H2D_RING_IDX(h2d_ring_id) (h2d_ring_id) | |
182 | ||
183 | enum h2dring_idx { | |
184 | /* H2D common rings */ | |
185 | BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT_IDX = | |
186 | BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT), | |
187 | BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT_IDX = | |
188 | BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT), | |
189 | ||
190 | /* First TxPost's WR or RD index starts after all H2D common rings */ | |
191 | BCMPCIE_H2D_MSGRING_TXFLOW_IDX_START = | |
192 | BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_COMMON_MSGRINGS) | |
193 | }; | |
194 | ||
195 | #define BCMPCIE_D2H_RING_IDX(d2h_ring_id) \ | |
196 | ((d2h_ring_id) - BCMPCIE_H2D_COMMON_MSGRINGS) | |
197 | ||
198 | enum d2hring_idx { | |
199 | /* D2H Common Rings */ | |
200 | BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE_IDX = | |
201 | BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE), | |
202 | BCMPCIE_D2H_MSGRING_TX_COMPLETE_IDX = | |
203 | BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_TX_COMPLETE), | |
204 | BCMPCIE_D2H_MSGRING_RX_COMPLETE_IDX = | |
205 | BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_RX_COMPLETE) | |
206 | }; | |
207 | ||
208 | /** | |
209 | * Macros for managing arrays of RD WR indices: | |
210 | * rw_index_sz: | |
211 | * - in dongle, rw_index_sz is known at compile time | |
212 | * - in host/DHD, rw_index_sz is derived from advertized pci_shared flags | |
213 | * | |
214 | * ring_idx: See h2dring_idx and d2hring_idx | |
215 | */ | |
216 | ||
217 | /** Offset of a RD or WR index in H2D or D2H indices array */ | |
218 | #define BCMPCIE_RW_INDEX_OFFSET(rw_index_sz, ring_idx) \ | |
219 | ((rw_index_sz) * (ring_idx)) | |
220 | ||
221 | /** Fetch the address of RD or WR index in H2D or D2H indices array */ | |
222 | #define BCMPCIE_RW_INDEX_ADDR(indices_array_base, rw_index_sz, ring_idx) \ | |
223 | (void *)((uint32)(indices_array_base) + \ | |
224 | BCMPCIE_RW_INDEX_OFFSET((rw_index_sz), (ring_idx))) | |
225 | ||
226 | /** H2D DMA Indices array size: given max flow rings */ | |
227 | #define BCMPCIE_H2D_RW_INDEX_ARRAY_SZ(rw_index_sz, max_tx_flows) \ | |
228 | ((rw_index_sz) * BCMPCIE_H2D_MSGRINGS(max_tx_flows)) | |
229 | ||
230 | /** D2H DMA Indices array size */ | |
231 | #define BCMPCIE_D2H_RW_INDEX_ARRAY_SZ(rw_index_sz) \ | |
232 | ((rw_index_sz) * BCMPCIE_D2H_COMMON_MSGRINGS) | |
233 | ||
234 | /** | |
235 | * This type is used by a 'message buffer' (which is a FIFO for messages). Message buffers are used | |
236 | * for host<->device communication and are instantiated on both sides. ring_mem_t is instantiated | |
237 | * both in host as well as device memory. | |
238 | */ | |
239 | typedef struct ring_mem { | |
240 | uint16 idx; /* ring id */ | |
241 | uint8 type; | |
242 | uint8 rsvd; | |
243 | uint16 max_item; /* Max number of items in flow ring */ | |
244 | uint16 len_items; /* Items are fixed size. Length in bytes of one item */ | |
245 | sh_addr_t base_addr; /* 64 bits address, either in host or device memory */ | |
246 | } ring_mem_t; | |
247 | ||
248 | ||
249 | /** | |
250 | * Per flow ring, information is maintained in device memory, eg at what address the ringmem and | |
251 | * ringstate are located. The flow ring itself can be instantiated in either host or device memory. | |
252 | * | |
253 | * Perhaps this type should be renamed to make clear that it resides in device memory only. | |
254 | */ | |
255 | typedef struct ring_info { | |
256 | uint32 ringmem_ptr; /* ring mem location in dongle memory */ | |
257 | ||
258 | /* Following arrays are indexed using h2dring_idx and d2hring_idx, and not | |
259 | * by a ringid. | |
260 | */ | |
261 | ||
262 | /* 32bit ptr to arrays of WR or RD indices for all rings in dongle memory */ | |
263 | uint32 h2d_w_idx_ptr; /* Array of all H2D ring's WR indices */ | |
264 | uint32 h2d_r_idx_ptr; /* Array of all H2D ring's RD indices */ | |
265 | uint32 d2h_w_idx_ptr; /* Array of all D2H ring's WR indices */ | |
266 | uint32 d2h_r_idx_ptr; /* Array of all D2H ring's RD indices */ | |
267 | ||
268 | /* PCIE_DMA_INDEX feature: Dongle uses mem2mem DMA to sync arrays in host. | |
269 | * Host may directly fetch WR and RD indices from these host-side arrays. | |
270 | * | |
271 | * 64bit ptr to arrays of WR or RD indices for all rings in host memory. | |
272 | */ | |
273 | sh_addr_t h2d_w_idx_hostaddr; /* Array of all H2D ring's WR indices */ | |
274 | sh_addr_t h2d_r_idx_hostaddr; /* Array of all H2D ring's RD indices */ | |
275 | sh_addr_t d2h_w_idx_hostaddr; /* Array of all D2H ring's WR indices */ | |
276 | sh_addr_t d2h_r_idx_hostaddr; /* Array of all D2H ring's RD indices */ | |
277 | ||
278 | uint16 max_tx_flowrings; /* maximum number of H2D rings: common + flow */ | |
279 | uint16 max_submission_queues; /* maximum number of H2D rings: common + flow */ | |
280 | uint16 max_completion_rings; /* maximum number of H2D rings: common + flow */ | |
281 | uint16 max_vdevs; /* max number of virtual interfaces supported */ | |
282 | ||
283 | sh_addr_t ifrm_w_idx_hostaddr; /* Array of all H2D ring's WR indices for IFRM */ | |
284 | } ring_info_t; | |
285 | ||
286 | /** | |
287 | * A structure located in TCM that is shared between host and device, primarily used during | |
288 | * initialization. | |
289 | */ | |
290 | typedef struct { | |
291 | /** shared area version captured at flags 7:0 */ | |
292 | uint32 flags; | |
293 | ||
294 | uint32 trap_addr; | |
295 | uint32 assert_exp_addr; | |
296 | uint32 assert_file_addr; | |
297 | uint32 assert_line; | |
298 | uint32 console_addr; /**< Address of hnd_cons_t */ | |
299 | ||
300 | uint32 msgtrace_addr; | |
301 | ||
302 | uint32 fwid; | |
303 | ||
304 | /* Used for debug/flow control */ | |
305 | uint16 total_lfrag_pkt_cnt; | |
306 | uint16 max_host_rxbufs; /* rsvd in spec */ | |
307 | ||
308 | uint32 dma_rxoffset; /* rsvd in spec */ | |
309 | ||
310 | /** these will be used for sleep request/ack, d3 req/ack */ | |
311 | uint32 h2d_mb_data_ptr; | |
312 | uint32 d2h_mb_data_ptr; | |
313 | ||
314 | /* information pertinent to host IPC/msgbuf channels */ | |
315 | /** location in the TCM memory which has the ring_info */ | |
316 | uint32 rings_info_ptr; | |
317 | ||
318 | /** block of host memory for the scratch buffer */ | |
319 | uint32 host_dma_scratch_buffer_len; | |
320 | sh_addr_t host_dma_scratch_buffer; | |
321 | ||
322 | /** block of host memory for the dongle to push the status into */ | |
323 | uint32 device_rings_stsblk_len; | |
324 | sh_addr_t device_rings_stsblk; | |
325 | ||
326 | uint32 buzz_dbg_ptr; /* BUZZZ state format strings and trace buffer */ | |
327 | ||
328 | /* rev6 compatible changes */ | |
329 | uint32 flags2; | |
330 | uint32 host_cap; | |
331 | ||
332 | /* location in the host address space to write trap indication. | |
333 | * At this point for the current rev of the spec, firmware will | |
334 | * support only indications to 32 bit host addresses. | |
335 | */ | |
336 | sh_addr_t host_trap_addr; | |
337 | ||
338 | /* location for host fatal error log buffer start address */ | |
339 | uint32 device_fatal_logbuf_start; | |
340 | ||
341 | /* location in host memory for offloaded modules */ | |
342 | sh_addr_t hoffload_addr; | |
343 | } pciedev_shared_t; | |
344 | ||
345 | extern pciedev_shared_t pciedev_shared; | |
346 | ||
347 | /* host capabilities */ | |
348 | #define HOSTCAP_PCIEAPI_VERSION_MASK 0x000000FF | |
349 | #define HOSTCAP_H2D_VALID_PHASE 0x00000100 | |
350 | #define HOSTCAP_H2D_ENABLE_TRAP_ON_BADPHASE 0x00000200 | |
351 | #define HOSTCAP_H2D_ENABLE_HOSTRDY 0x00000400 | |
352 | #define HOSTCAP_DB0_TIMESTAMP 0x00000800 | |
353 | #define HOSTCAP_DS_NO_OOB_DW 0x00001000 | |
354 | #define HOSTCAP_DS_INBAND_DW 0x00002000 | |
355 | #define HOSTCAP_H2D_IDMA 0x00004000 | |
356 | #define HOSTCAP_H2D_IFRM 0x00008000 | |
357 | #define HOSTCAP_H2D_DAR 0x00010000 | |
358 | #define HOSTCAP_EXTENDED_TRAP_DATA 0x00020000 | |
359 | #define HOSTCAP_TXSTATUS_METADATA 0x00040000 | |
360 | ||
361 | /** | |
362 | * Mailboxes notify a remote party that an event took place, using interrupts. They use hardware | |
363 | * support. | |
364 | */ | |
365 | ||
366 | /* H2D mail box Data */ | |
367 | #define H2D_HOST_D3_INFORM 0x00000001 | |
368 | #define H2D_HOST_DS_ACK 0x00000002 | |
369 | #define H2D_HOST_DS_NAK 0x00000004 | |
370 | #define H2D_HOST_CONS_INT 0x80000000 /**< h2d int for console cmds */ | |
371 | #define H2D_FW_TRAP 0x20000000 /**< h2d force TRAP */ | |
372 | #define H2D_HOST_D0_INFORM_IN_USE 0x00000008 | |
373 | #define H2D_HOST_D0_INFORM 0x00000010 | |
374 | #define H2D_HOST_IDMA_INITED 0x00000080 | |
375 | #define H2DMB_DS_HOST_SLEEP_INFORM H2D_HOST_D3_INFORM | |
376 | #define H2DMB_DS_DEVICE_SLEEP_ACK H2D_HOST_DS_ACK | |
377 | #define H2DMB_DS_DEVICE_SLEEP_NAK H2D_HOST_DS_NAK | |
378 | #define H2DMB_D0_INFORM_IN_USE H2D_HOST_D0_INFORM_IN_USE | |
379 | #define H2DMB_D0_INFORM H2D_HOST_D0_INFORM | |
380 | #define H2DMB_DS_ACTIVE 0x00000020 | |
381 | #define H2DMB_DS_DEVICE_WAKE 0x00000040 | |
382 | #define H2DMB_FW_TRAP H2D_FW_TRAP | |
383 | #define H2DMB_HOST_CONS_INT H2D_HOST_CONS_INT | |
384 | #define H2DMB_DS_DEVICE_WAKE_ASSERT H2DMB_DS_DEVICE_WAKE | |
385 | #define H2DMB_DS_DEVICE_WAKE_DEASSERT H2DMB_DS_ACTIVE | |
386 | ||
387 | /* D2H mail box Data */ | |
388 | #define D2H_DEV_D3_ACK 0x00000001 | |
389 | #define D2H_DEV_DS_ENTER_REQ 0x00000002 | |
390 | #define D2H_DEV_DS_EXIT_NOTE 0x00000004 | |
391 | #define D2H_DEV_FWHALT 0x10000000 | |
392 | #define D2H_DEV_EXT_TRAP_DATA 0x20000000 | |
393 | #define D2H_DEV_IDMA_INITED 0x00000010 | |
394 | #define D2H_FWTRAP_MASK 0x0000001F /* Adding maskbits for TRAP information */ | |
395 | #define D2HMB_DS_HOST_SLEEP_ACK D2H_DEV_D3_ACK | |
396 | #define D2HMB_DS_DEVICE_SLEEP_ENTER_REQ D2H_DEV_DS_ENTER_REQ | |
397 | #define D2HMB_DS_DEVICE_SLEEP_EXIT D2H_DEV_DS_EXIT_NOTE | |
398 | #define D2HMB_DS_HOST_SLEEP_EXIT_ACK 0x00000008 | |
399 | #define D2HMB_FWHALT D2H_DEV_FWHALT | |
400 | #define D2H_DEV_MB_MASK (D2H_DEV_D3_ACK | D2H_DEV_DS_ENTER_REQ | \ | |
401 | D2H_DEV_DS_EXIT_NOTE | D2H_DEV_IDMA_INITED | D2H_DEV_FWHALT | \ | |
402 | D2H_FWTRAP_MASK | D2H_DEV_EXT_TRAP_DATA) | |
403 | #define D2H_DEV_MB_INVALIDATED(x) ((!x) || (x & ~D2H_DEV_MB_MASK)) | |
404 | ||
405 | ||
406 | /** These macro's operate on type 'inuse_lclbuf_pool_t' and are used by firmware only */ | |
407 | #define NEXTTXP(i, d) ((((i)+1) >= (d)) ? 0 : ((i)+1)) | |
408 | #define NTXPACTIVE(r, w, d) (((r) <= (w)) ? ((w)-(r)) : ((d)-(r)+(w))) | |
409 | #define NTXPAVAIL(r, w, d) (((d) - NTXPACTIVE((r), (w), (d))) > 1) | |
410 | ||
411 | /* Function can be used to notify host of FW halt */ | |
412 | #define READ_AVAIL_SPACE(w, r, d) \ | |
413 | ((w >= r) ? (w - r) : (d - r)) | |
414 | ||
415 | #define WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d) ((w >= r) ? (d - w) : (r - w)) | |
416 | #define WRITE_SPACE_AVAIL(r, w, d) (d - (NTXPACTIVE(r, w, d)) - 1) | |
417 | #define CHECK_WRITE_SPACE(r, w, d) \ | |
418 | ((r) > (w)) ? ((r) - (w) - 1) : ((r) == 0 || (w) == 0) ? ((d) - (w) - 1) : ((d) - (w)) | |
419 | #define CHECK_NOWRITE_SPACE(r, w, d) \ | |
420 | (((r) == (w) + 1) || (((r) == 0) && ((w) == ((d) - 1)))) | |
421 | ||
422 | ||
423 | #define WRT_PEND(x) ((x)->wr_pending) | |
424 | #define DNGL_RING_WPTR(msgbuf) (*((msgbuf)->tcm_rs_w_ptr)) /**< advanced by producer */ | |
425 | #define BCMMSGBUF_RING_SET_W_PTR(msgbuf, a) (DNGL_RING_WPTR(msgbuf) = (a)) | |
426 | ||
427 | #define DNGL_RING_RPTR(msgbuf) (*((msgbuf)->tcm_rs_r_ptr)) /**< advanced by consumer */ | |
428 | #define BCMMSGBUF_RING_SET_R_PTR(msgbuf, a) (DNGL_RING_RPTR(msgbuf) = (a)) | |
429 | ||
430 | #define MODULO_RING_IDX(x, y) ((x) % (y)->bitmap_size) | |
431 | ||
432 | #define RING_READ_PTR(x) ((x)->ringstate->r_offset) | |
433 | #define RING_WRITE_PTR(x) ((x)->ringstate->w_offset) | |
434 | #define RING_START_PTR(x) ((x)->ringmem->base_addr.low_addr) | |
435 | #define RING_MAX_ITEM(x) ((x)->ringmem->max_item) | |
436 | #define RING_LEN_ITEMS(x) ((x)->ringmem->len_items) | |
437 | #define HOST_RING_BASE(x) ((x)->dma_buf.va) | |
438 | #define HOST_RING_END(x) ((uint8 *)HOST_RING_BASE((x)) + \ | |
439 | ((RING_MAX_ITEM((x))-1)*RING_LEN_ITEMS((x)))) | |
440 | #endif /* _bcmpcie_h_ */ |