Commit | Line | Data |
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32760332 JJ |
1 | #include "../cmucal.h" |
2 | #include "cmucal-node.h" | |
3 | #include "cmucal-sfr.h" | |
4 | ||
5 | /*=================CMUCAL version: S5E9610================================*/ | |
6 | ||
7 | /*====================The section of PLL rate tables===================*/ | |
8 | struct cmucal_pll_table pll_shared0_rate_table[] = { | |
9 | PLL_RATE_MPS(1599000000, 246, 4, 0), | |
10 | }; | |
11 | ||
12 | struct cmucal_pll_table pll_shared1_rate_table[] = { | |
13 | PLL_RATE_MPS(1332500000, 205, 4, 0), | |
14 | }; | |
15 | ||
16 | struct cmucal_pll_table pll_mmc_rate_table[] = { | |
17 | PLL_RATE_MPSK(799999878, 31, 1, 0, -15124), | |
18 | }; | |
19 | ||
20 | struct cmucal_pll_table pll_cpucl0_rate_table[] = { | |
21 | PLL_RATE_MPS(1049750000, 323, 4, 1), | |
22 | PLL_RATE_MPS(1449500000, 223, 4, 0), | |
23 | PLL_RATE_MPS(1850333252, 427, 6, 0), | |
24 | PLL_RATE_MPS(300083344, 277, 6, 2), | |
25 | PLL_RATE_MPS(600166687, 277, 6, 1), | |
26 | }; | |
27 | ||
28 | struct cmucal_pll_table pll_cpucl1_rate_table[] = { | |
29 | PLL_RATE_MPS(1499333374, 346, 3, 1), | |
30 | PLL_RATE_MPS(1898000000, 292, 4, 0), | |
31 | PLL_RATE_MPS(2400666748, 277, 3, 0), | |
32 | PLL_RATE_MPS(549899963, 423, 5, 2), | |
33 | PLL_RATE_MPS(850200012, 327, 5, 1), | |
34 | }; | |
35 | ||
36 | struct cmucal_pll_table pll_aud_rate_table[] = { | |
37 | PLL_RATE_MPSK(1179648071, 45, 1, 0, 24319), | |
38 | PLL_RATE_MPSK(1083801600, 42, 1, 0, -20665), | |
39 | }; | |
40 | ||
41 | struct cmucal_pll_table pll_g3d_rate_table[] = { | |
42 | PLL_RATE_MPS(750000000, 375, 13, 0), | |
43 | PLL_RATE_MPS(1000000061, 500, 13, 0), | |
44 | PLL_RATE_MPS(1200000000, 600, 13, 0), | |
45 | PLL_RATE_MPS(300000000, 600, 13, 2), | |
46 | PLL_RATE_MPS(550000000, 550, 13, 1), | |
47 | }; | |
48 | ||
49 | struct cmucal_pll_table pll_mif_rate_table[] = { | |
50 | PLL_RATE_MPS(4264000000, 492, 3, 0), | |
51 | PLL_RATE_MPS(1399666626, 323, 3, 1), | |
52 | PLL_RATE_MPS(1332500000, 410, 4, 1), | |
53 | }; | |
54 | ||
55 | struct cmucal_pll_table pll_mif1_rate_table[] = { | |
56 | PLL_RATE_MPS(100000000, 0, 0, 0), | |
57 | }; | |
58 | ||
59 | /*====================The section of PLLs===================*/ | |
60 | unsigned int cmucal_pll_size = 9; | |
61 | ||
62 | struct cmucal_pll cmucal_pll_list[] = { | |
63 | CLK_PLL(PLL_1051X, PLL_SHARED0, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED0_ENABLE, PLL_CON0_PLL_SHARED0_STABLE, PLL_CON0_PLL_SHARED0_DIV_P, PLL_CON0_PLL_SHARED0_DIV_M, PLL_CON0_PLL_SHARED0_DIV_S, EMPTY_CAL_ID, pll_shared0_rate_table, 150, 0), | |
64 | CLK_PLL(PLL_1051X, PLL_SHARED1, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED1_ENABLE, PLL_CON0_PLL_SHARED1_STABLE, PLL_CON0_PLL_SHARED1_DIV_P, PLL_CON0_PLL_SHARED1_DIV_M, PLL_CON0_PLL_SHARED1_DIV_S, EMPTY_CAL_ID, pll_shared1_rate_table, 150, 0), | |
65 | CLK_PLL(PLL_1061X, PLL_MMC, OSCCLK_CMU, PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME, PLL_CON0_PLL_MMC_ENABLE, PLL_CON0_PLL_MMC_STABLE, PLL_CON0_PLL_MMC_DIV_P, PLL_CON0_PLL_MMC_DIV_M, PLL_CON0_PLL_MMC_DIV_S, PLL_CON3_PLL_MMC_DIV_K, pll_mmc_rate_table, 150, 1500), | |
66 | CLK_PLL(PLL_1051X, PLL_CPUCL0, OSCCLK_CPUCL0, PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, PLL_CON0_PLL_CPUCL0_ENABLE, PLL_CON0_PLL_CPUCL0_STABLE, PLL_CON0_PLL_CPUCL0_DIV_P, PLL_CON0_PLL_CPUCL0_DIV_M, PLL_CON0_PLL_CPUCL0_DIV_S, EMPTY_CAL_ID, pll_cpucl0_rate_table, 150, 0), | |
67 | CLK_PLL(PLL_1054X, PLL_CPUCL1, OSCCLK_CPUCL1, PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, PLL_CON0_PLL_CPUCL1_ENABLE, PLL_CON0_PLL_CPUCL1_STABLE, PLL_CON0_PLL_CPUCL1_DIV_P, PLL_CON0_PLL_CPUCL1_DIV_M, PLL_CON0_PLL_CPUCL1_DIV_S, EMPTY_CAL_ID, pll_cpucl1_rate_table, 0, 0), | |
68 | CLK_PLL(PLL_1061X, PLL_AUD, OSCCLK_DISPAUD, PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, PLL_CON0_PLL_AUD_ENABLE, PLL_CON0_PLL_AUD_STABLE, PLL_CON0_PLL_AUD_DIV_P, PLL_CON0_PLL_AUD_DIV_M, PLL_CON0_PLL_AUD_DIV_S, PLL_CON3_PLL_AUD_DIV_K, pll_aud_rate_table, 150, 1500), | |
69 | CLK_PLL(PLL_1052X, PLL_G3D, OSCCLK_G3D, PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, PLL_CON0_PLL_G3D_ENABLE, PLL_CON0_PLL_G3D_STABLE, PLL_CON0_PLL_G3D_DIV_P, PLL_CON0_PLL_G3D_DIV_M, PLL_CON0_PLL_G3D_DIV_S, EMPTY_CAL_ID, pll_g3d_rate_table, 150, 0), | |
70 | CLK_PLL(PLL_1050X, PLL_MIF, OSCCLK_MIF, PLL_LOCKTIME_PLL_MIF_PLL_LOCK_TIME, PLL_CON0_PLL_MIF_ENABLE, PLL_CON0_PLL_MIF_STABLE, PLL_CON0_PLL_MIF_DIV_P, PLL_CON0_PLL_MIF_DIV_M, PLL_CON0_PLL_MIF_DIV_S, EMPTY_CAL_ID, pll_mif_rate_table, 150, 0), | |
71 | CLK_PLL(PLL_1050X, PLL_MIF1, OSCCLK_MIF1, PLL_LOCKTIME_PLL_MIF1_PLL_LOCK_TIME, PLL_CON0_PLL_MIF1_ENABLE, PLL_CON0_PLL_MIF1_STABLE, PLL_CON0_PLL_MIF1_DIV_P, PLL_CON0_PLL_MIF1_DIV_M, PLL_CON0_PLL_MIF1_DIV_S, EMPTY_CAL_ID, pll_mif1_rate_table, 150, 0), | |
72 | }; | |
73 | ||
74 | /*====================The section of MUXs' parents===================*/ | |
75 | enum clk_id cmucal_mux_clk_apm_bus_parents[] = { | |
76 | MUX_CLKCMU_APM_BUS_USER, | |
77 | MUX_DLL_USER, | |
78 | }; | |
79 | enum clk_id cmucal_mux_clkcmu_shub_bus_parents[] = { | |
80 | MUX_CLKCMU_APM_BUS_USER, | |
81 | MUX_DLL_USER, | |
82 | }; | |
83 | enum clk_id cmucal_mux_clk_cmgp_usi01_parents[] = { | |
84 | OSCCLK_RCO_CMGP, | |
85 | CLKCMU_CMGP_BUS, | |
86 | }; | |
87 | enum clk_id cmucal_mux_clk_cmgp_i2c_parents[] = { | |
88 | OSCCLK_RCO_CMGP, | |
89 | CLKCMU_CMGP_BUS, | |
90 | }; | |
91 | enum clk_id cmucal_mux_clk_cmgp_usi00_parents[] = { | |
92 | OSCCLK_RCO_CMGP, | |
93 | CLKCMU_CMGP_BUS, | |
94 | }; | |
95 | enum clk_id cmucal_mux_clk_cmgp_usi04_parents[] = { | |
96 | OSCCLK_RCO_CMGP, | |
97 | CLKCMU_CMGP_BUS, | |
98 | }; | |
99 | enum clk_id cmucal_mux_clk_cmgp_usi02_parents[] = { | |
100 | OSCCLK_RCO_CMGP, | |
101 | CLKCMU_CMGP_BUS, | |
102 | }; | |
103 | enum clk_id cmucal_mux_clk_cmgp_usi03_parents[] = { | |
104 | OSCCLK_RCO_CMGP, | |
105 | CLKCMU_CMGP_BUS, | |
106 | }; | |
107 | enum clk_id cmucal_mux_clk_cmgp_adc_parents[] = { | |
108 | OSCCLK_CMGP, | |
109 | DIV_CLK_CMGP_ADC, | |
110 | }; | |
111 | enum clk_id cmucal_mux_clkcmu_g2d_mscl_parents[] = { | |
112 | PLL_SHARED0_DIV3, | |
113 | PLL_SHARED1_DIV3, | |
114 | PLL_SHARED0_DIV4, | |
115 | PLL_SHARED1_DIV4, | |
116 | }; | |
117 | enum clk_id cmucal_mux_clkcmu_dispaud_disp_parents[] = { | |
118 | PLL_SHARED0_DIV3, | |
119 | PLL_SHARED1_DIV3, | |
120 | PLL_SHARED0_DIV4, | |
121 | PLL_SHARED1_DIV4, | |
122 | }; | |
123 | enum clk_id cmucal_mux_clkcmu_fsys_bus_parents[] = { | |
124 | PLL_SHARED0_DIV2, | |
125 | PLL_SHARED1_DIV2, | |
126 | }; | |
127 | enum clk_id cmucal_mux_clkcmu_fsys_mmc_embd_parents[] = { | |
128 | OSCCLK_CMU, | |
129 | PLL_SHARED0_DIV2, | |
130 | PLL_SHARED1_DIV2, | |
131 | PLL_SHARED0_DIV3, | |
132 | PLL_SHARED1_DIV3, | |
133 | PLL_MMC, | |
134 | OSCCLK_CMU, | |
135 | OSCCLK_CMU, | |
136 | }; | |
137 | enum clk_id cmucal_mux_clkcmu_peri_bus_parents[] = { | |
138 | PLL_SHARED0_DIV4, | |
139 | PLL_SHARED1_DIV4, | |
140 | }; | |
141 | enum clk_id cmucal_mux_clkcmu_peri_ip_parents[] = { | |
142 | OSCCLK_CMU, | |
143 | PLL_SHARED0_DIV4, | |
144 | PLL_SHARED1_DIV4, | |
145 | OSCCLK_CMU, | |
146 | }; | |
147 | enum clk_id cmucal_mux_clkcmu_fsys_mmc_card_parents[] = { | |
148 | OSCCLK_CMU, | |
149 | PLL_SHARED0_DIV2, | |
150 | PLL_SHARED1_DIV2, | |
151 | PLL_SHARED0_DIV3, | |
152 | PLL_SHARED1_DIV3, | |
153 | PLL_MMC, | |
154 | OSCCLK_CMU, | |
155 | OSCCLK_CMU, | |
156 | }; | |
157 | enum clk_id cmucal_mux_clkcmu_cis_clk0_parents[] = { | |
158 | OSCCLK_CMU, | |
159 | PLL_SHARED0_DIV4, | |
160 | }; | |
161 | enum clk_id cmucal_mux_clkcmu_cis_clk1_parents[] = { | |
162 | OSCCLK_CMU, | |
163 | PLL_SHARED0_DIV4, | |
164 | }; | |
165 | enum clk_id cmucal_mux_clkcmu_cis_clk2_parents[] = { | |
166 | OSCCLK_CMU, | |
167 | PLL_SHARED0_DIV4, | |
168 | }; | |
169 | enum clk_id cmucal_mux_cmu_cmuref_parents[] = { | |
170 | OSCCLK_CMU, | |
171 | DIV_CLK_CMU_CMUREF, | |
172 | }; | |
173 | enum clk_id cmucal_mux_clk_cmu_cmuref_parents[] = { | |
174 | PLL_SHARED0_DIV4, | |
175 | PLL_SHARED1_DIV4, | |
176 | }; | |
177 | enum clk_id cmucal_mux_clkcmu_apm_bus_parents[] = { | |
178 | PLL_SHARED0_DIV4, | |
179 | PLL_SHARED1_DIV4, | |
180 | }; | |
181 | enum clk_id cmucal_mux_clkcmu_core_cci_parents[] = { | |
182 | PLL_SHARED0_DIV2, | |
183 | PLL_SHARED1_DIV2, | |
184 | PLL_SHARED0_DIV3, | |
185 | PLL_MMC_DIV2, | |
186 | }; | |
187 | enum clk_id cmucal_mux_clkcmu_core_g3d_parents[] = { | |
188 | PLL_SHARED0_DIV2, | |
189 | PLL_SHARED1_DIV2, | |
190 | PLL_SHARED0_DIV3, | |
191 | PLL_MMC_DIV2, | |
192 | }; | |
193 | enum clk_id cmucal_mux_clkcmu_core_bus_parents[] = { | |
194 | PLL_SHARED1_DIV2, | |
195 | PLL_SHARED0_DIV3, | |
196 | PLL_SHARED0_DIV4, | |
197 | PLL_MMC_DIV2, | |
198 | }; | |
199 | enum clk_id cmucal_mux_clkcmu_mif_busp_parents[] = { | |
200 | PLL_SHARED0_DIV4, | |
201 | PLL_SHARED1_DIV4, | |
202 | PLL_MMC_DIV2, | |
203 | OSCCLK_CMU, | |
204 | }; | |
205 | enum clk_id cmucal_mux_clkcmu_fsys_ufs_embd_parents[] = { | |
206 | OSCCLK_CMU, | |
207 | PLL_SHARED0_DIV4, | |
208 | PLL_SHARED1_DIV4, | |
209 | OSCCLK_CMU, | |
210 | }; | |
211 | enum clk_id cmucal_mux_clkcmu_cam_bus_parents[] = { | |
212 | PLL_SHARED1_DIV2, | |
213 | PLL_SHARED0_DIV3, | |
214 | PLL_SHARED1_DIV3, | |
215 | PLL_SHARED0_DIV4, | |
216 | }; | |
217 | enum clk_id cmucal_mux_clkcmu_vipx1_bus_parents[] = { | |
218 | PLL_SHARED1_DIV2, | |
219 | PLL_SHARED0_DIV3, | |
220 | PLL_SHARED1_DIV3, | |
221 | PLL_SHARED0_DIV4, | |
222 | }; | |
223 | enum clk_id cmucal_mux_clkcmu_isp_bus_parents[] = { | |
224 | PLL_SHARED1_DIV2, | |
225 | PLL_SHARED0_DIV3, | |
226 | PLL_SHARED1_DIV3, | |
227 | PLL_SHARED0_DIV4, | |
228 | }; | |
229 | enum clk_id cmucal_mux_clkcmu_isp_vra_parents[] = { | |
230 | PLL_SHARED0_DIV3, | |
231 | PLL_SHARED1_DIV3, | |
232 | PLL_SHARED0_DIV4, | |
233 | PLL_SHARED1_DIV4, | |
234 | }; | |
235 | enum clk_id cmucal_mux_clkcmu_isp_gdc_parents[] = { | |
236 | PLL_SHARED0_DIV3, | |
237 | PLL_SHARED1_DIV3, | |
238 | PLL_SHARED0_DIV4, | |
239 | PLL_SHARED1_DIV4, | |
240 | }; | |
241 | enum clk_id cmucal_mux_clkcmu_g2d_g2d_parents[] = { | |
242 | PLL_SHARED1_DIV2, | |
243 | PLL_SHARED0_DIV3, | |
244 | PLL_SHARED1_DIV3, | |
245 | PLL_SHARED0_DIV4, | |
246 | }; | |
247 | enum clk_id cmucal_mux_clkcmu_cpucl0_switch_parents[] = { | |
248 | PLL_SHARED0_DIV2, | |
249 | PLL_SHARED1_DIV2, | |
250 | PLL_SHARED0_DIV3, | |
251 | PLL_SHARED1_DIV3, | |
252 | }; | |
253 | enum clk_id cmucal_mux_clkcmu_cpucl1_switch_parents[] = { | |
254 | PLL_SHARED0_DIV2, | |
255 | PLL_SHARED1_DIV2, | |
256 | PLL_SHARED0_DIV3, | |
257 | PLL_SHARED1_DIV3, | |
258 | }; | |
259 | enum clk_id cmucal_mux_clkcmu_g3d_switch_parents[] = { | |
260 | PLL_SHARED0_DIV2, | |
261 | PLL_SHARED1_DIV2, | |
262 | PLL_SHARED0_DIV3, | |
263 | PLL_SHARED1_DIV3, | |
264 | }; | |
265 | enum clk_id cmucal_mux_clkcmu_dispaud_cpu_parents[] = { | |
266 | PLL_SHARED1, | |
267 | PLL_SHARED0_DIV2, | |
268 | PLL_SHARED1_DIV2, | |
269 | PLL_SHARED0_DIV3, | |
270 | PLL_SHARED1_DIV3, | |
271 | PLL_MMC, | |
272 | OSCCLK_CMU, | |
273 | OSCCLK_CMU, | |
274 | }; | |
275 | enum clk_id cmucal_mux_clkcmu_mif_switch_parents[] = { | |
276 | PLL_SHARED0, | |
277 | PLL_SHARED1, | |
278 | PLL_SHARED0_DIV2, | |
279 | PLL_MMC, | |
280 | PLL_SHARED0_DIV3, | |
281 | PLL_SHARED1_DIV3, | |
282 | PLL_SHARED0_DIV4, | |
283 | PLL_SHARED1_DIV4, | |
284 | }; | |
285 | enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_parents[] = { | |
286 | PLL_SHARED0_DIV4, | |
287 | PLL_SHARED1_DIV4, | |
288 | }; | |
289 | enum clk_id cmucal_mux_clkcmu_usb_bus_parents[] = { | |
290 | PLL_SHARED0_DIV3, | |
291 | PLL_SHARED1_DIV3, | |
292 | PLL_SHARED0_DIV4, | |
293 | PLL_SHARED1_DIV4, | |
294 | }; | |
295 | enum clk_id cmucal_mux_clkcmu_usb_usb30drd_parents[] = { | |
296 | OSCCLK_CMU, | |
297 | PLL_SHARED0_DIV4, | |
298 | PLL_SHARED1_DIV4, | |
299 | OSCCLK_CMU, | |
300 | }; | |
301 | enum clk_id cmucal_mux_clkcmu_usb_dpgtc_parents[] = { | |
302 | OSCCLK_CMU, | |
303 | PLL_SHARED0_DIV4, | |
304 | PLL_SHARED1_DIV4, | |
305 | OSCCLK_CMU, | |
306 | }; | |
307 | enum clk_id cmucal_mux_clkcmu_dispaud_aud_parents[] = { | |
308 | PLL_SHARED1_DIV2, | |
309 | PLL_SHARED0_DIV3, | |
310 | PLL_SHARED1_DIV3, | |
311 | PLL_SHARED0_DIV4, | |
312 | }; | |
313 | enum clk_id cmucal_mux_clkcmu_mfc_mfc_parents[] = { | |
314 | PLL_SHARED1_DIV2, | |
315 | PLL_SHARED0_DIV3, | |
316 | PLL_SHARED1_DIV3, | |
317 | PLL_SHARED0_DIV4, | |
318 | }; | |
319 | enum clk_id cmucal_mux_clkcmu_mfc_wfd_parents[] = { | |
320 | PLL_SHARED0_DIV3, | |
321 | PLL_SHARED1_DIV3, | |
322 | PLL_SHARED0_DIV4, | |
323 | PLL_SHARED1_DIV4, | |
324 | }; | |
325 | enum clk_id cmucal_mux_clkcmu_hpm_parents[] = { | |
326 | OSCCLK_CMU, | |
327 | PLL_SHARED0_DIV2, | |
328 | PLL_SHARED1_DIV2, | |
329 | PLL_SHARED0_DIV3, | |
330 | PLL_MMC_DIV2, | |
331 | OSCCLK_CMU, | |
332 | OSCCLK_CMU, | |
333 | OSCCLK_CMU, | |
334 | }; | |
335 | enum clk_id cmucal_mux_clkcmu_peri_uart_parents[] = { | |
336 | OSCCLK_CMU, | |
337 | PLL_SHARED0_DIV4, | |
338 | PLL_SHARED1_DIV4, | |
339 | OSCCLK_CMU, | |
340 | }; | |
341 | enum clk_id cmucal_mux_clkcmu_vipx2_bus_parents[] = { | |
342 | PLL_SHARED1_DIV2, | |
343 | PLL_SHARED0_DIV3, | |
344 | PLL_SHARED1_DIV3, | |
345 | PLL_SHARED0_DIV4, | |
346 | }; | |
347 | enum clk_id cmucal_mux_clkcmu_cis_clk3_parents[] = { | |
348 | OSCCLK_CMU, | |
349 | PLL_SHARED0_DIV4, | |
350 | }; | |
351 | enum clk_id cmucal_mux_clk_core_gic_parents[] = { | |
352 | DIV_CLK_CORE_BUSP, | |
353 | OSCCLK_CORE, | |
354 | }; | |
355 | enum clk_id cmucal_mux_clk_cpucl0_pll_parents[] = { | |
356 | PLL_CPUCL0, | |
357 | MUX_CLKCMU_CPUCL0_SWITCH_USER, | |
358 | }; | |
359 | enum clk_id cmucal_mux_clk_cpucl1_pll_parents[] = { | |
360 | PLL_CPUCL1, | |
361 | MUX_CLKCMU_CPUCL1_SWITCH_USER, | |
362 | }; | |
363 | enum clk_id cmucal_mux_clk_aud_cpu_parents[] = { | |
364 | DIV_CLK_AUD_CPU, | |
365 | MUX_CLKCMU_DISPAUD_CPU_USER, | |
366 | }; | |
367 | enum clk_id cmucal_mux_clk_aud_uaif0_parents[] = { | |
368 | DIV_CLK_AUD_UAIF0, | |
369 | IOCLK_AUDIOCDCLK0, | |
370 | }; | |
371 | enum clk_id cmucal_mux_clk_aud_uaif2_parents[] = { | |
372 | DIV_CLK_AUD_UAIF2, | |
373 | IOCLK_AUDIOCDCLK2, | |
374 | }; | |
375 | enum clk_id cmucal_mux_clk_aud_uaif1_parents[] = { | |
376 | DIV_CLK_AUD_UAIF1, | |
377 | IOCLK_AUDIOCDCLK1, | |
378 | }; | |
379 | enum clk_id cmucal_mux_clk_aud_cpu_hch_parents[] = { | |
380 | MUX_CLK_AUD_CPU, | |
381 | OSCCLK_DISPAUD, | |
382 | }; | |
383 | enum clk_id cmucal_mux_clk_aud_fm_parents[] = { | |
384 | OSCCLK_DISPAUD, | |
385 | DIV_CLK_AUD_FM_SPDY, | |
386 | }; | |
387 | enum clk_id cmucal_mux_clk_aud_bus_parents[] = { | |
388 | DIV_CLK_AUD_BUS, | |
389 | MUX_CLKCMU_DISPAUD_AUD_USER, | |
390 | }; | |
391 | enum clk_id cmucal_mux_clk_g3d_busd_parents[] = { | |
392 | PLL_G3D, | |
393 | MUX_CLKCMU_G3D_SWITCH_USER, | |
394 | }; | |
395 | enum clk_id cmucal_mux_clk_mif_ddrphy_clk2x_parents[] = { | |
396 | PLL_MIF, | |
397 | CLKCMU_MIF_SWITCH, | |
398 | }; | |
399 | enum clk_id cmucal_mux_mif_cmuref_parents[] = { | |
400 | OSCCLK_MIF, | |
401 | MUX_CLKCMU_MIF_BUSP_USER, | |
402 | }; | |
403 | enum clk_id cmucal_mux_clk_mif1_ddrphy_clk2x_parents[] = { | |
404 | PLL_MIF1, | |
405 | CLKCMU_MIF_SWITCH, | |
406 | }; | |
407 | enum clk_id cmucal_mux_mif1_cmuref_parents[] = { | |
408 | OSCCLK_MIF1, | |
409 | MUX_CLKCMU_MIF1_BUSP_USER, | |
410 | }; | |
411 | enum clk_id cmucal_mux_clk_shub_usi00_parents[] = { | |
412 | OSCCLK_RCO_SHUB__ALV, | |
413 | MUX_CLKCMU_SHUB_BUS_USER, | |
414 | }; | |
415 | enum clk_id cmucal_mux_clk_shub_usi01_parents[] = { | |
416 | OSCCLK_RCO_SHUB__ALV, | |
417 | MUX_CLKCMU_SHUB_BUS_USER, | |
418 | }; | |
419 | enum clk_id cmucal_mux_clk_shub_i2c_parents[] = { | |
420 | OSCCLK_RCO_SHUB__ALV, | |
421 | MUX_CLKCMU_SHUB_BUS_USER, | |
422 | }; | |
423 | enum clk_id cmucal_mux_clkcmu_apm_bus_user_parents[] = { | |
424 | OSCCLK_RCO_APM, | |
425 | CLKCMU_APM_BUS, | |
426 | }; | |
427 | enum clk_id cmucal_mux_dll_user_parents[] = { | |
428 | OSCCLK_RCO_APM, | |
429 | CLK_DLL_DCO, | |
430 | }; | |
431 | enum clk_id cmucal_mux_clkcmu_cam_bus_user_parents[] = { | |
432 | OSCCLK_CAM, | |
433 | CLKCMU_CAM_BUS, | |
434 | }; | |
435 | enum clk_id cmucal_mux_clkcmu_core_bus_user_parents[] = { | |
436 | OSCCLK_CORE, | |
437 | CLKCMU_CORE_BUS, | |
438 | }; | |
439 | enum clk_id cmucal_mux_clkcmu_core_cci_user_parents[] = { | |
440 | OSCCLK_CORE, | |
441 | CLKCMU_CORE_CCI, | |
442 | }; | |
443 | enum clk_id cmucal_mux_clkcmu_core_g3d_user_parents[] = { | |
444 | OSCCLK_CORE, | |
445 | CLKCMU_CORE_G3D, | |
446 | }; | |
447 | enum clk_id cmucal_mux_clkcmu_cpucl0_switch_user_parents[] = { | |
448 | OSCCLK_CPUCL0, | |
449 | CLKCMU_CPUCL0_SWITCH, | |
450 | }; | |
451 | enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_user_parents[] = { | |
452 | OSCCLK_CPUCL0, | |
453 | CLKCMU_CPUCL0_DBG, | |
454 | }; | |
455 | enum clk_id cmucal_mux_clkcmu_cpucl1_switch_user_parents[] = { | |
456 | OSCCLK_CPUCL1, | |
457 | CLKCMU_CPUCL1_SWITCH, | |
458 | }; | |
459 | enum clk_id cmucal_mux_clkcmu_dispaud_cpu_user_parents[] = { | |
460 | OSCCLK_DISPAUD, | |
461 | CLKCMU_DISPAUD_CPU, | |
462 | }; | |
463 | enum clk_id cmucal_mux_clkcmu_dispaud_disp_user_parents[] = { | |
464 | OSCCLK_DISPAUD, | |
465 | CLKCMU_DISPAUD_DISP, | |
466 | }; | |
467 | enum clk_id cmucal_mux_clkcmu_dispaud_aud_user_parents[] = { | |
468 | OSCCLK_DISPAUD, | |
469 | CLKCMU_DISPAUD_AUD, | |
470 | }; | |
471 | enum clk_id cmucal_mux_clkcmu_fsys_bus_user_parents[] = { | |
472 | OSCCLK_FSYS, | |
473 | CLKCMU_FSYS_BUS, | |
474 | }; | |
475 | enum clk_id cmucal_mux_clkcmu_fsys_mmc_card_user_parents[] = { | |
476 | OSCCLK_FSYS, | |
477 | CLKCMU_FSYS_MMC_CARD, | |
478 | }; | |
479 | enum clk_id cmucal_mux_clkcmu_fsys_mmc_embd_user_parents[] = { | |
480 | OSCCLK_FSYS, | |
481 | CLKCMU_FSYS_MMC_EMBD, | |
482 | }; | |
483 | enum clk_id cmucal_mux_clkcmu_fsys_ufs_embd_user_parents[] = { | |
484 | OSCCLK_FSYS, | |
485 | CLKCMU_FSYS_UFS_EMBD, | |
486 | }; | |
487 | enum clk_id cmucal_mux_clkcmu_g2d_mscl_user_parents[] = { | |
488 | OSCCLK_G2D, | |
489 | CLKCMU_G2D_MSCL, | |
490 | }; | |
491 | enum clk_id cmucal_mux_clkcmu_g2d_g2d_user_parents[] = { | |
492 | OSCCLK_G2D, | |
493 | CLKCMU_G2D_G2D, | |
494 | }; | |
495 | enum clk_id cmucal_mux_clkcmu_g3d_switch_user_parents[] = { | |
496 | OSCCLK_G3D, | |
497 | CLKCMU_G3D_SWITCH, | |
498 | }; | |
499 | enum clk_id cmucal_mux_clkcmu_isp_bus_user_parents[] = { | |
500 | OSCCLK_ISP, | |
501 | CLKCMU_ISP_BUS, | |
502 | }; | |
503 | enum clk_id cmucal_mux_clkcmu_isp_vra_user_parents[] = { | |
504 | OSCCLK_ISP, | |
505 | CLKCMU_ISP_VRA, | |
506 | }; | |
507 | enum clk_id cmucal_mux_clkcmu_isp_gdc_user_parents[] = { | |
508 | OSCCLK_ISP, | |
509 | CLKCMU_ISP_GDC, | |
510 | }; | |
511 | enum clk_id cmucal_mux_clkcmu_mfc_wfd_user_parents[] = { | |
512 | OSCCLK_MFC, | |
513 | CLKCMU_MFC_WFD, | |
514 | }; | |
515 | enum clk_id cmucal_mux_clkcmu_mfc_mfc_user_parents[] = { | |
516 | OSCCLK_MFC, | |
517 | CLKCMU_MFC_MFC, | |
518 | }; | |
519 | enum clk_id cmucal_mux_clkcmu_mif_busp_user_parents[] = { | |
520 | OSCCLK_MIF, | |
521 | CLKCMU_MIF_BUSP, | |
522 | }; | |
523 | enum clk_id cmucal_mux_clkcmu_mif1_busp_user_parents[] = { | |
524 | OSCCLK_MIF1, | |
525 | CLKCMU_MIF_BUSP, | |
526 | }; | |
527 | enum clk_id cmucal_mux_clkcmu_peri_bus_user_parents[] = { | |
528 | OSCCLK_PERI, | |
529 | CLKCMU_PERI_BUS, | |
530 | }; | |
531 | enum clk_id cmucal_mux_clkcmu_peri_ip_user_parents[] = { | |
532 | OSCCLK_PERI, | |
533 | CLKCMU_PERI_IP, | |
534 | }; | |
535 | enum clk_id cmucal_mux_clkcmu_peri_uart_user_parents[] = { | |
536 | OSCCLK_PERI, | |
537 | CLKCMU_PERI_UART, | |
538 | }; | |
539 | enum clk_id cmucal_mux_clkcmu_shub_bus_user_parents[] = { | |
540 | OSCCLK_RCO_SHUB__ALV, | |
541 | CLKCMU_SHUB_BUS, | |
542 | }; | |
543 | enum clk_id cmucal_mux_clkcmu_usb_bus_user_parents[] = { | |
544 | OSCCLK_USB, | |
545 | CLKCMU_USB_BUS, | |
546 | }; | |
547 | enum clk_id cmucal_mux_clkcmu_usb_usb30drd_user_parents[] = { | |
548 | OSCCLK_USB, | |
549 | CLKCMU_USB_USB30DRD, | |
550 | }; | |
551 | enum clk_id cmucal_mux_clkcmu_usb_dpgtc_user_parents[] = { | |
552 | OSCCLK_USB, | |
553 | CLKCMU_USB_DPGTC, | |
554 | }; | |
555 | enum clk_id cmucal_mux_clkcmu_vipx1_bus_user_parents[] = { | |
556 | OSCCLK_VIPX1, | |
557 | CLKCMU_VIPX1_BUS, | |
558 | }; | |
559 | enum clk_id cmucal_mux_clkcmu_vipx2_bus_user_parents[] = { | |
560 | OSCCLK_VIPX2, | |
561 | CLKCMU_VIPX2_BUS, | |
562 | }; | |
563 | ||
564 | ||
565 | /*====================The section of MUXs===================*/ | |
566 | unsigned int cmucal_mux_size = 124; | |
567 | ||
568 | ||
569 | struct cmucal_mux cmucal_mux_list[] = { | |
570 | CLK_MUX(MUX_CLK_APM_BUS, cmucal_mux_clk_apm_bus_parents, CLK_CON_MUX_MUX_CLK_APM_BUS_SELECT, CLK_CON_MUX_MUX_CLK_APM_BUS_BUSY, CLK_CON_MUX_MUX_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
571 | CLK_MUX(MUX_CLKCMU_SHUB_BUS, cmucal_mux_clkcmu_shub_bus_parents, CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
572 | CLK_MUX(MUX_CLK_CMGP_USI01, cmucal_mux_clk_cmgp_usi01_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI01_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI01_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI01_ENABLE_AUTOMATIC_CLKGATING), | |
573 | CLK_MUX(MUX_CLK_CMGP_I2C, cmucal_mux_clk_cmgp_i2c_parents, CLK_CON_MUX_MUX_CLK_CMGP_I2C_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I2C_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING), | |
574 | CLK_MUX(MUX_CLK_CMGP_USI00, cmucal_mux_clk_cmgp_usi00_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI00_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI00_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI00_ENABLE_AUTOMATIC_CLKGATING), | |
575 | CLK_MUX(MUX_CLK_CMGP_USI04, cmucal_mux_clk_cmgp_usi04_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI04_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI04_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI04_ENABLE_AUTOMATIC_CLKGATING), | |
576 | CLK_MUX(MUX_CLK_CMGP_USI02, cmucal_mux_clk_cmgp_usi02_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI02_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI02_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI02_ENABLE_AUTOMATIC_CLKGATING), | |
577 | CLK_MUX(MUX_CLK_CMGP_USI03, cmucal_mux_clk_cmgp_usi03_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI03_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI03_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI03_ENABLE_AUTOMATIC_CLKGATING), | |
578 | CLK_MUX(MUX_CLK_CMGP_ADC, cmucal_mux_clk_cmgp_adc_parents, CLK_CON_MUX_MUX_CLK_CMGP_ADC_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_ADC_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING), | |
579 | CLK_MUX(MUX_CLKCMU_G2D_MSCL, cmucal_mux_clkcmu_g2d_mscl_parents, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_SELECT, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING), | |
580 | CLK_MUX(MUX_CLKCMU_DISPAUD_DISP, cmucal_mux_clkcmu_dispaud_disp_parents, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP_SELECT, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP_BUSY, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING), | |
581 | CLK_MUX(MUX_CLKCMU_FSYS_BUS, cmucal_mux_clkcmu_fsys_bus_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
582 | CLK_MUX(MUX_CLKCMU_FSYS_MMC_EMBD, cmucal_mux_clkcmu_fsys_mmc_embd_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING), | |
583 | CLK_MUX(MUX_CLKCMU_PERI_BUS, cmucal_mux_clkcmu_peri_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
584 | CLK_MUX(MUX_CLKCMU_PERI_IP, cmucal_mux_clkcmu_peri_ip_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING), | |
585 | CLK_MUX(MUX_CLKCMU_FSYS_MMC_CARD, cmucal_mux_clkcmu_fsys_mmc_card_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING), | |
586 | CLK_MUX(MUX_CLKCMU_CIS_CLK0, cmucal_mux_clkcmu_cis_clk0_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING), | |
587 | CLK_MUX(MUX_CLKCMU_CIS_CLK1, cmucal_mux_clkcmu_cis_clk1_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING), | |
588 | CLK_MUX(MUX_CLKCMU_CIS_CLK2, cmucal_mux_clkcmu_cis_clk2_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING), | |
589 | CLK_MUX(MUX_CMU_CMUREF, cmucal_mux_cmu_cmuref_parents, CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING), | |
590 | CLK_MUX(MUX_CLK_CMU_CMUREF, cmucal_mux_clk_cmu_cmuref_parents, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING), | |
591 | CLK_MUX(MUX_CLKCMU_APM_BUS, cmucal_mux_clkcmu_apm_bus_parents, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
592 | CLK_MUX(MUX_CLKCMU_CORE_CCI, cmucal_mux_clkcmu_core_cci_parents, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI_ENABLE_AUTOMATIC_CLKGATING), | |
593 | CLK_MUX(MUX_CLKCMU_CORE_G3D, cmucal_mux_clkcmu_core_g3d_parents, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING), | |
594 | CLK_MUX(MUX_CLKCMU_CORE_BUS, cmucal_mux_clkcmu_core_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
595 | CLK_MUX(MUX_CLKCMU_MIF_BUSP, cmucal_mux_clkcmu_mif_busp_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING), | |
596 | CLK_MUX(MUX_CLKCMU_FSYS_UFS_EMBD, cmucal_mux_clkcmu_fsys_ufs_embd_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING), | |
597 | CLK_MUX(MUX_CLKCMU_CAM_BUS, cmucal_mux_clkcmu_cam_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
598 | CLK_MUX(MUX_CLKCMU_VIPX1_BUS, cmucal_mux_clkcmu_vipx1_bus_parents, CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
599 | CLK_MUX(MUX_CLKCMU_ISP_BUS, cmucal_mux_clkcmu_isp_bus_parents, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
600 | CLK_MUX(MUX_CLKCMU_ISP_VRA, cmucal_mux_clkcmu_isp_vra_parents, CLK_CON_MUX_MUX_CLKCMU_ISP_VRA_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISP_VRA_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING), | |
601 | CLK_MUX(MUX_CLKCMU_ISP_GDC, cmucal_mux_clkcmu_isp_gdc_parents, CLK_CON_MUX_MUX_CLKCMU_ISP_GDC_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISP_GDC_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING), | |
602 | CLK_MUX(MUX_CLKCMU_G2D_G2D, cmucal_mux_clkcmu_g2d_g2d_parents, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_SELECT, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING), | |
603 | CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH, cmucal_mux_clkcmu_cpucl0_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING), | |
604 | CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH, cmucal_mux_clkcmu_cpucl1_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING), | |
605 | CLK_MUX(MUX_CLKCMU_G3D_SWITCH, cmucal_mux_clkcmu_g3d_switch_parents, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING), | |
606 | CLK_MUX(MUX_CLKCMU_DISPAUD_CPU, cmucal_mux_clkcmu_dispaud_cpu_parents, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU_SELECT, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU_BUSY, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING), | |
607 | CLK_MUX(MUX_CLKCMU_MIF_SWITCH, cmucal_mux_clkcmu_mif_switch_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING), | |
608 | CLK_MUX(MUX_CLKCMU_CPUCL0_DBG, cmucal_mux_clkcmu_cpucl0_dbg_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING), | |
609 | CLK_MUX(MUX_CLKCMU_USB_BUS, cmucal_mux_clkcmu_usb_bus_parents, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
610 | CLK_MUX(MUX_CLKCMU_USB_USB30DRD, cmucal_mux_clkcmu_usb_usb30drd_parents, CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD_SELECT, CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD_BUSY, CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD_ENABLE_AUTOMATIC_CLKGATING), | |
611 | CLK_MUX(MUX_CLKCMU_USB_DPGTC, cmucal_mux_clkcmu_usb_dpgtc_parents, CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC_SELECT, CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC_BUSY, CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC_ENABLE_AUTOMATIC_CLKGATING), | |
612 | CLK_MUX(MUX_CLKCMU_DISPAUD_AUD, cmucal_mux_clkcmu_dispaud_aud_parents, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD_SELECT, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD_BUSY, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING), | |
613 | CLK_MUX(MUX_CLKCMU_MFC_MFC, cmucal_mux_clkcmu_mfc_mfc_parents, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING), | |
614 | CLK_MUX(MUX_CLKCMU_MFC_WFD, cmucal_mux_clkcmu_mfc_wfd_parents, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING), | |
615 | CLK_MUX(MUX_CLKCMU_HPM, cmucal_mux_clkcmu_hpm_parents, CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING), | |
616 | CLK_MUX(MUX_CLKCMU_PERI_UART, cmucal_mux_clkcmu_peri_uart_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_ENABLE_AUTOMATIC_CLKGATING), | |
617 | CLK_MUX(MUX_CLKCMU_VIPX2_BUS, cmucal_mux_clkcmu_vipx2_bus_parents, CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
618 | CLK_MUX(MUX_CLKCMU_CIS_CLK3, cmucal_mux_clkcmu_cis_clk3_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING), | |
619 | CLK_MUX(MUX_CLK_CORE_GIC, cmucal_mux_clk_core_gic_parents, CLK_CON_MUX_MUX_CLK_CORE_GIC_SELECT, CLK_CON_MUX_MUX_CLK_CORE_GIC_BUSY, CLK_CON_MUX_MUX_CLK_CORE_GIC_ENABLE_AUTOMATIC_CLKGATING), | |
620 | CLK_MUX(MUX_CLK_CPUCL0_PLL, cmucal_mux_clk_cpucl0_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING), | |
621 | CLK_MUX(MUX_CLK_CPUCL1_PLL, cmucal_mux_clk_cpucl1_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING), | |
622 | CLK_MUX(MUX_CLK_AUD_CPU, cmucal_mux_clk_aud_cpu_parents, CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING), | |
623 | CLK_MUX(MUX_CLK_AUD_UAIF0, cmucal_mux_clk_aud_uaif0_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING), | |
624 | CLK_MUX(MUX_CLK_AUD_UAIF2, cmucal_mux_clk_aud_uaif2_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING), | |
625 | CLK_MUX(MUX_CLK_AUD_UAIF1, cmucal_mux_clk_aud_uaif1_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING), | |
626 | CLK_MUX(MUX_CLK_AUD_CPU_HCH, cmucal_mux_clk_aud_cpu_hch_parents, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_ENABLE_AUTOMATIC_CLKGATING), | |
627 | CLK_MUX(MUX_CLK_AUD_FM, cmucal_mux_clk_aud_fm_parents, CLK_CON_MUX_MUX_CLK_AUD_FM_SELECT, CLK_CON_MUX_MUX_CLK_AUD_FM_BUSY, CLK_CON_MUX_MUX_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING), | |
628 | CLK_MUX(MUX_CLK_AUD_BUS, cmucal_mux_clk_aud_bus_parents, CLK_CON_MUX_MUX_CLK_AUD_BUS_SELECT, CLK_CON_MUX_MUX_CLK_AUD_BUS_BUSY, CLK_CON_MUX_MUX_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
629 | CLK_MUX(MUX_CLK_G3D_BUSD, cmucal_mux_clk_g3d_busd_parents, CLK_CON_MUX_MUX_CLK_G3D_BUSD_SELECT, CLK_CON_MUX_MUX_CLK_G3D_BUSD_BUSY, CLK_CON_MUX_MUX_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING), | |
630 | CLK_MUX(MUX_CLK_MIF_DDRPHY_CLK2X, cmucal_mux_clk_mif_ddrphy_clk2x_parents, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_SELECT, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_BUSY, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_ENABLE_AUTOMATIC_CLKGATING), | |
631 | CLK_MUX(MUX_MIF_CMUREF, cmucal_mux_mif_cmuref_parents, CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING), | |
632 | CLK_MUX(MUX_CLK_MIF1_DDRPHY_CLK2X, cmucal_mux_clk_mif1_ddrphy_clk2x_parents, CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X_SELECT, CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X_BUSY, CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X_ENABLE_AUTOMATIC_CLKGATING), | |
633 | CLK_MUX(MUX_MIF1_CMUREF, cmucal_mux_mif1_cmuref_parents, CLK_CON_MUX_MUX_MIF1_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF1_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF1_CMUREF_ENABLE_AUTOMATIC_CLKGATING), | |
634 | CLK_MUX(MUX_CLK_SHUB_USI00, cmucal_mux_clk_shub_usi00_parents, CLK_CON_MUX_MUX_CLK_SHUB_USI00_SELECT, CLK_CON_MUX_MUX_CLK_SHUB_USI00_BUSY, CLK_CON_MUX_MUX_CLK_SHUB_USI00_ENABLE_AUTOMATIC_CLKGATING), | |
635 | CLK_MUX(MUX_CLK_SHUB_USI01, cmucal_mux_clk_shub_usi01_parents, CLK_CON_MUX_MUX_CLK_SHUB_USI01_SELECT, CLK_CON_MUX_MUX_CLK_SHUB_USI01_BUSY, CLK_CON_MUX_MUX_CLK_SHUB_USI01_ENABLE_AUTOMATIC_CLKGATING), | |
636 | CLK_MUX(MUX_CLK_SHUB_I2C, cmucal_mux_clk_shub_i2c_parents, CLK_CON_MUX_MUX_CLK_SHUB_I2C_SELECT, CLK_CON_MUX_MUX_CLK_SHUB_I2C_BUSY, CLK_CON_MUX_MUX_CLK_SHUB_I2C_ENABLE_AUTOMATIC_CLKGATING), | |
36b28160 MB |
637 | CLK_MUX_NULL(APM_CMU_APM_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
638 | CLK_MUX_NULL(CAM_CMU_CAM_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
639 | CLK_MUX_NULL(CMGP_CMU_CMGP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
640 | CLK_MUX_NULL(CMU_CMU_TOP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
641 | CLK_MUX_NULL(CORE_CMU_CORE_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
642 | CLK_MUX_NULL(CPUCL0_CMU_CPUCL0_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
643 | CLK_MUX_NULL(CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
644 | CLK_MUX_NULL(CPUCL1_CMU_CPUCL1_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
645 | CLK_MUX_NULL(CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
646 | CLK_MUX_NULL(DISPAUD_CMU_DISPAUD_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
647 | CLK_MUX_NULL(FSYS_CMU_FSYS_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
648 | CLK_MUX_NULL(G2D_CMU_G2D_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
649 | CLK_MUX_NULL(G3D_CMU_G3D_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
650 | CLK_MUX_NULL(ISP_CMU_ISP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
651 | CLK_MUX_NULL(MFC_CMU_MFC_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
652 | CLK_MUX_NULL(MIF_CMU_MIF_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
653 | CLK_MUX_NULL(MIF1_CMU_MIF1_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
654 | CLK_MUX_NULL(PERI_CMU_PERI_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
655 | CLK_MUX_NULL(SHUB_CMU_SHUB_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
656 | CLK_MUX_NULL(USB_CMU_USB_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
657 | CLK_MUX_NULL(VIPX1_CMU_VIPX1_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
658 | CLK_MUX_NULL(VIPX2_CMU_VIPX2_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), | |
32760332 JJ |
659 | CLK_MUX(MUX_CLKCMU_APM_BUS_USER, cmucal_mux_clkcmu_apm_bus_user_parents, PLL_CON0_MUX_CLKCMU_APM_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_APM_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_APM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
660 | CLK_MUX(MUX_DLL_USER, cmucal_mux_dll_user_parents, PLL_CON0_MUX_DLL_USER_MUX_SEL, PLL_CON0_MUX_DLL_USER_BUSY, PLL_CON2_MUX_DLL_USER_ENABLE_AUTOMATIC_CLKGATING), | |
661 | CLK_MUX(MUX_CLKCMU_CAM_BUS_USER, cmucal_mux_clkcmu_cam_bus_user_parents, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_CAM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), | |
662 | CLK_MUX(MUX_CLKCMU_CORE_BUS_USER, cmucal_mux_clkcmu_core_bus_user_parents, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), | |
663 | CLK_MUX(MUX_CLKCMU_CORE_CCI_USER, cmucal_mux_clkcmu_core_cci_user_parents, PLL_CON0_MUX_CLKCMU_CORE_CCI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_CCI_USER_BUSY, PLL_CON2_MUX_CLKCMU_CORE_CCI_USER_ENABLE_AUTOMATIC_CLKGATING), | |
664 | CLK_MUX(MUX_CLKCMU_CORE_G3D_USER, cmucal_mux_clkcmu_core_g3d_user_parents, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_BUSY, PLL_CON2_MUX_CLKCMU_CORE_G3D_USER_ENABLE_AUTOMATIC_CLKGATING), | |
665 | CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH_USER, cmucal_mux_clkcmu_cpucl0_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), | |
666 | CLK_MUX(MUX_CLKCMU_CPUCL0_DBG_USER, cmucal_mux_clkcmu_cpucl0_dbg_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_USER_ENABLE_AUTOMATIC_CLKGATING), | |
667 | CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH_USER, cmucal_mux_clkcmu_cpucl1_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), | |
668 | CLK_MUX(MUX_CLKCMU_DISPAUD_CPU_USER, cmucal_mux_clkcmu_dispaud_cpu_user_parents, PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER_BUSY, PLL_CON2_MUX_CLKCMU_DISPAUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING), | |
669 | CLK_MUX(MUX_CLKCMU_DISPAUD_DISP_USER, cmucal_mux_clkcmu_dispaud_disp_user_parents, PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER_BUSY, PLL_CON2_MUX_CLKCMU_DISPAUD_DISP_USER_ENABLE_AUTOMATIC_CLKGATING), | |
670 | CLK_MUX(MUX_CLKCMU_DISPAUD_AUD_USER, cmucal_mux_clkcmu_dispaud_aud_user_parents, PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER_BUSY, PLL_CON2_MUX_CLKCMU_DISPAUD_AUD_USER_ENABLE_AUTOMATIC_CLKGATING), | |
671 | CLK_MUX(MUX_CLKCMU_FSYS_BUS_USER, cmucal_mux_clkcmu_fsys_bus_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), | |
672 | CLK_MUX(MUX_CLKCMU_FSYS_MMC_CARD_USER, cmucal_mux_clkcmu_fsys_mmc_card_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING), | |
673 | CLK_MUX(MUX_CLKCMU_FSYS_MMC_EMBD_USER, cmucal_mux_clkcmu_fsys_mmc_embd_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING), | |
674 | CLK_MUX(MUX_CLKCMU_FSYS_UFS_EMBD_USER, cmucal_mux_clkcmu_fsys_ufs_embd_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING), | |
675 | CLK_MUX(MUX_CLKCMU_G2D_MSCL_USER, cmucal_mux_clkcmu_g2d_mscl_user_parents, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_BUSY, PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING), | |
676 | CLK_MUX(MUX_CLKCMU_G2D_G2D_USER, cmucal_mux_clkcmu_g2d_g2d_user_parents, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_BUSY, PLL_CON2_MUX_CLKCMU_G2D_G2D_USER_ENABLE_AUTOMATIC_CLKGATING), | |
677 | CLK_MUX(MUX_CLKCMU_G3D_SWITCH_USER, cmucal_mux_clkcmu_g3d_switch_user_parents, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), | |
678 | CLK_MUX(MUX_CLKCMU_ISP_BUS_USER, cmucal_mux_clkcmu_isp_bus_user_parents, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_ISP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), | |
679 | CLK_MUX(MUX_CLKCMU_ISP_VRA_USER, cmucal_mux_clkcmu_isp_vra_user_parents, PLL_CON0_MUX_CLKCMU_ISP_VRA_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISP_VRA_USER_BUSY, PLL_CON2_MUX_CLKCMU_ISP_VRA_USER_ENABLE_AUTOMATIC_CLKGATING), | |
680 | CLK_MUX(MUX_CLKCMU_ISP_GDC_USER, cmucal_mux_clkcmu_isp_gdc_user_parents, PLL_CON0_MUX_CLKCMU_ISP_GDC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISP_GDC_USER_BUSY, PLL_CON2_MUX_CLKCMU_ISP_GDC_USER_ENABLE_AUTOMATIC_CLKGATING), | |
681 | CLK_MUX(MUX_CLKCMU_MFC_WFD_USER, cmucal_mux_clkcmu_mfc_wfd_user_parents, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_BUSY, PLL_CON2_MUX_CLKCMU_MFC_WFD_USER_ENABLE_AUTOMATIC_CLKGATING), | |
682 | CLK_MUX(MUX_CLKCMU_MFC_MFC_USER, cmucal_mux_clkcmu_mfc_mfc_user_parents, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_BUSY, PLL_CON2_MUX_CLKCMU_MFC_MFC_USER_ENABLE_AUTOMATIC_CLKGATING), | |
683 | CLK_MUX(MUX_CLKCMU_MIF_BUSP_USER, cmucal_mux_clkcmu_mif_busp_user_parents, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY, PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING), | |
684 | CLK_MUX(MUX_CLKCMU_MIF1_BUSP_USER, cmucal_mux_clkcmu_mif1_busp_user_parents, PLL_CON0_MUX_CLKCMU_MIF1_BUSP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MIF1_BUSP_USER_BUSY, PLL_CON2_MUX_CLKCMU_MIF1_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING), | |
685 | CLK_MUX(MUX_CLKCMU_PERI_BUS_USER, cmucal_mux_clkcmu_peri_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), | |
686 | CLK_MUX(MUX_CLKCMU_PERI_IP_USER, cmucal_mux_clkcmu_peri_ip_user_parents, PLL_CON0_MUX_CLKCMU_PERI_IP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_IP_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_IP_USER_ENABLE_AUTOMATIC_CLKGATING), | |
687 | CLK_MUX(MUX_CLKCMU_PERI_UART_USER, cmucal_mux_clkcmu_peri_uart_user_parents, PLL_CON0_MUX_CLKCMU_PERI_UART_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_UART_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_UART_USER_ENABLE_AUTOMATIC_CLKGATING), | |
688 | CLK_MUX(MUX_CLKCMU_SHUB_BUS_USER, cmucal_mux_clkcmu_shub_bus_user_parents, PLL_CON0_MUX_CLKCMU_SHUB_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_SHUB_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_SHUB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), | |
689 | CLK_MUX(MUX_CLKCMU_USB_BUS_USER, cmucal_mux_clkcmu_usb_bus_user_parents, PLL_CON0_MUX_CLKCMU_USB_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_USB_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_USB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), | |
690 | CLK_MUX(MUX_CLKCMU_USB_USB30DRD_USER, cmucal_mux_clkcmu_usb_usb30drd_user_parents, PLL_CON0_MUX_CLKCMU_USB_USB30DRD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_USB_USB30DRD_USER_BUSY, PLL_CON2_MUX_CLKCMU_USB_USB30DRD_USER_ENABLE_AUTOMATIC_CLKGATING), | |
691 | CLK_MUX(MUX_CLKCMU_USB_DPGTC_USER, cmucal_mux_clkcmu_usb_dpgtc_user_parents, PLL_CON0_MUX_CLKCMU_USB_DPGTC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_USB_DPGTC_USER_BUSY, PLL_CON2_MUX_CLKCMU_USB_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING), | |
692 | CLK_MUX(MUX_CLKCMU_VIPX1_BUS_USER, cmucal_mux_clkcmu_vipx1_bus_user_parents, PLL_CON0_MUX_CLKCMU_VIPX1_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VIPX1_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_VIPX1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), | |
693 | CLK_MUX(MUX_CLKCMU_VIPX2_BUS_USER, cmucal_mux_clkcmu_vipx2_bus_user_parents, PLL_CON0_MUX_CLKCMU_VIPX2_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VIPX2_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_VIPX2_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), | |
694 | }; | |
695 | ||
696 | /*====================The section of DIVs===================*/ | |
697 | unsigned int cmucal_div_size = 98; | |
698 | ||
699 | ||
700 | struct cmucal_div cmucal_div_list[] = { | |
701 | CLK_DIV(DIV_CLK_APM_BUS, MUX_CLK_APM_BUS, CLK_CON_DIV_DIV_CLK_APM_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_APM_BUS_BUSY, CLK_CON_DIV_DIV_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
702 | CLK_DIV(CLKCMU_SHUB_BUS, GATE_CLKCMU_SHUB_BUS, CLK_CON_DIV_CLKCMU_SHUB_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_SHUB_BUS_BUSY, CLK_CON_DIV_CLKCMU_SHUB_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
703 | CLK_DIV(DIV_CLK_CAM_BUSP, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_DIV_DIV_CLK_CAM_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CAM_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CAM_BUSP_ENABLE_AUTOMATIC_CLKGATING), | |
704 | CLK_DIV(DIV_CLK_CMGP_USI03, MUX_CLK_CMGP_USI03, CLK_CON_DIV_DIV_CLK_CMGP_USI03_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI03_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI03_ENABLE_AUTOMATIC_CLKGATING), | |
705 | CLK_DIV(DIV_CLK_CMGP_USI00, MUX_CLK_CMGP_USI00, CLK_CON_DIV_DIV_CLK_CMGP_USI00_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI00_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI00_ENABLE_AUTOMATIC_CLKGATING), | |
706 | CLK_DIV(DIV_CLK_CMGP_I2C, MUX_CLK_CMGP_I2C, CLK_CON_DIV_DIV_CLK_CMGP_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I2C_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING), | |
707 | CLK_DIV(DIV_CLK_CMGP_USI01, MUX_CLK_CMGP_USI01, CLK_CON_DIV_DIV_CLK_CMGP_USI01_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI01_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI01_ENABLE_AUTOMATIC_CLKGATING), | |
708 | CLK_DIV(DIV_CLK_CMGP_USI04, MUX_CLK_CMGP_USI04, CLK_CON_DIV_DIV_CLK_CMGP_USI04_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI04_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI04_ENABLE_AUTOMATIC_CLKGATING), | |
709 | CLK_DIV(DIV_CLK_CMGP_USI02, MUX_CLK_CMGP_USI02, CLK_CON_DIV_DIV_CLK_CMGP_USI02_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI02_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI02_ENABLE_AUTOMATIC_CLKGATING), | |
710 | CLK_DIV(DIV_CLK_CMGP_ADC, CLKCMU_CMGP_BUS, CLK_CON_DIV_DIV_CLK_CMGP_ADC_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_ADC_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING), | |
711 | CLK_DIV(CLKCMU_DISPAUD_DISP, GATE_CLKCMU_DISPAUD_DISP, CLK_CON_DIV_CLKCMU_DISPAUD_DISP_DIVRATIO, CLK_CON_DIV_CLKCMU_DISPAUD_DISP_BUSY, CLK_CON_DIV_CLKCMU_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING), | |
712 | CLK_DIV(CLKCMU_FSYS_BUS, GATE_CLKCMU_FSYS_BUS, CLK_CON_DIV_CLKCMU_FSYS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS_BUS_BUSY, CLK_CON_DIV_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
713 | CLK_DIV(CLKCMU_G2D_MSCL, GATE_CLKCMU_G2D_MSCL, CLK_CON_DIV_CLKCMU_G2D_MSCL_DIVRATIO, CLK_CON_DIV_CLKCMU_G2D_MSCL_BUSY, CLK_CON_DIV_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING), | |
714 | CLK_DIV(AP2CP_SHARED0_PLL_CLK, GATE_CLKCMU_MODEM_SHARED0, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_DIVRATIO, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_BUSY, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
715 | CLK_DIV(CLKCMU_PERI_BUS, GATE_CLKCMU_PERI_BUS, CLK_CON_DIV_CLKCMU_PERI_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
716 | CLK_DIV(CLKCMU_PERI_IP, GATE_CLKCMU_PERI_IP, CLK_CON_DIV_CLKCMU_PERI_IP_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_IP_BUSY, CLK_CON_DIV_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING), | |
717 | CLK_DIV(CLKCMU_APM_BUS, GATE_CLKCMU_APM_BUS, CLK_CON_DIV_CLKCMU_APM_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_APM_BUS_BUSY, CLK_CON_DIV_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
718 | CLK_DIV(CLKCMU_FSYS_MMC_CARD, GATE_CLKCMU_FSYS_MMC_CARD, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_BUSY, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING), | |
719 | CLK_DIV(CLKCMU_CIS_CLK0, GATE_CLKCMU_CIS_CLK0, CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING), | |
720 | CLK_DIV(CLKCMU_CIS_CLK1, GATE_CLKCMU_CIS_CLK1, CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING), | |
721 | CLK_DIV(CLKCMU_CIS_CLK2, GATE_CLKCMU_CIS_CLK2, CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING), | |
722 | CLK_DIV(CLKCMU_FSYS_MMC_EMBD, GATE_CLKCMU_FSYS_MMC_EMBD, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_BUSY, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING), | |
723 | CLK_DIV(AP2CP_SHARED1_PLL_CLK, GATE_CLKCMU_MODEM_SHARED1, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_DIVRATIO, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_BUSY, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
724 | CLK_DIV(DIV_CLK_CMU_CMUREF, MUX_CLK_CMU_CMUREF, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING), | |
725 | CLK_DIV(CLKCMU_CORE_BUS, GATE_CLKCMU_CORE_BUS, CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
726 | CLK_DIV(PLL_SHARED0_DIV3, PLL_SHARED0, CLK_CON_DIV_PLL_SHARED0_DIV3_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV3_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV3_ENABLE_AUTOMATIC_CLKGATING), | |
727 | CLK_DIV(CLKCMU_CPUCL0_DBG, GATE_CLKCMU_CPUCL0_DBG, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING), | |
728 | CLK_DIV(PLL_SHARED0_DIV2, PLL_SHARED0, CLK_CON_DIV_PLL_SHARED0_DIV2_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV2_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING), | |
729 | CLK_DIV(PLL_SHARED0_DIV4, PLL_SHARED0_DIV2, CLK_CON_DIV_PLL_SHARED0_DIV4_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV4_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING), | |
730 | CLK_DIV(PLL_SHARED1_DIV2, PLL_SHARED1, CLK_CON_DIV_PLL_SHARED1_DIV2_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV2_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING), | |
731 | CLK_DIV(PLL_SHARED1_DIV4, PLL_SHARED1_DIV2, CLK_CON_DIV_PLL_SHARED1_DIV4_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV4_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING), | |
732 | CLK_DIV(CLKCMU_CORE_CCI, GATE_CLKCMU_CORE_CCI, CLK_CON_DIV_CLKCMU_CORE_CCI_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_CCI_BUSY, CLK_CON_DIV_CLKCMU_CORE_CCI_ENABLE_AUTOMATIC_CLKGATING), | |
733 | CLK_DIV(CLKCMU_CORE_G3D, GATE_CLKCMU_CORE_G3D, CLK_CON_DIV_CLKCMU_CORE_G3D_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_G3D_BUSY, CLK_CON_DIV_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING), | |
734 | CLK_DIV(CLKCMU_MIF_BUSP, GATE_CLKCMU_MIF_BUSP, CLK_CON_DIV_CLKCMU_MIF_BUSP_DIVRATIO, CLK_CON_DIV_CLKCMU_MIF_BUSP_BUSY, CLK_CON_DIV_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING), | |
735 | CLK_DIV(PLL_SHARED1_DIV3, PLL_SHARED1, CLK_CON_DIV_PLL_SHARED1_DIV3_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV3_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV3_ENABLE_AUTOMATIC_CLKGATING), | |
736 | CLK_DIV(CLKCMU_FSYS_UFS_EMBD, GATE_CLKCMU_FSYS_UFS_EMBD, CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD_BUSY, CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING), | |
737 | CLK_DIV(CLKCMU_CAM_BUS, GATE_CLKCMU_CAM_BUS, CLK_CON_DIV_CLKCMU_CAM_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CAM_BUS_BUSY, CLK_CON_DIV_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
738 | CLK_DIV(CLKCMU_VIPX1_BUS, GATE_CLKCMU_VIPX1_BUS, CLK_CON_DIV_CLKCMU_VIPX1_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_VIPX1_BUS_BUSY, CLK_CON_DIV_CLKCMU_VIPX1_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
739 | CLK_DIV(CLKCMU_ISP_BUS, GATE_CLKCMU_ISP_BUS, CLK_CON_DIV_CLKCMU_ISP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ISP_BUS_BUSY, CLK_CON_DIV_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
740 | CLK_DIV(CLKCMU_ISP_VRA, GATE_CLKCMU_ISP_VRA, CLK_CON_DIV_CLKCMU_ISP_VRA_DIVRATIO, CLK_CON_DIV_CLKCMU_ISP_VRA_BUSY, CLK_CON_DIV_CLKCMU_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING), | |
741 | CLK_DIV(CLKCMU_ISP_GDC, GATE_CLKCMU_ISP_GDC, CLK_CON_DIV_CLKCMU_ISP_GDC_DIVRATIO, CLK_CON_DIV_CLKCMU_ISP_GDC_BUSY, CLK_CON_DIV_CLKCMU_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING), | |
742 | CLK_DIV(CLKCMU_G2D_G2D, GATE_CLKCMU_G2D_G2D, CLK_CON_DIV_CLKCMU_G2D_G2D_DIVRATIO, CLK_CON_DIV_CLKCMU_G2D_G2D_BUSY, CLK_CON_DIV_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING), | |
743 | CLK_DIV(CLKCMU_CPUCL0_SWITCH, GATE_CLKCMU_CPUCL0_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING), | |
744 | CLK_DIV(CLKCMU_CPUCL1_SWITCH, GATE_CLKCMU_CPUCL1_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING), | |
745 | CLK_DIV(CLKCMU_G3D_SWITCH, GATE_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING), | |
746 | CLK_DIV(CLKCMU_DISPAUD_CPU, GATE_CLKCMU_DISPAUD_CPU, CLK_CON_DIV_CLKCMU_DISPAUD_CPU_DIVRATIO, CLK_CON_DIV_CLKCMU_DISPAUD_CPU_BUSY, CLK_CON_DIV_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING), | |
747 | CLK_DIV(CLKCMU_USB_BUS, GATE_CLKCMU_USB_BUS, CLK_CON_DIV_CLKCMU_USB_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_USB_BUS_BUSY, CLK_CON_DIV_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
748 | CLK_DIV(CLKCMU_USB_USB30DRD, GATE_CLKCMU_USB_USB30DRD, CLK_CON_DIV_CLKCMU_USB_USB30DRD_DIVRATIO, CLK_CON_DIV_CLKCMU_USB_USB30DRD_BUSY, CLK_CON_DIV_CLKCMU_USB_USB30DRD_ENABLE_AUTOMATIC_CLKGATING), | |
749 | CLK_DIV(CLKCMU_USB_DPGTC, GATE_CLKCMU_USB_DPGTC, CLK_CON_DIV_CLKCMU_USB_DPGTC_DIVRATIO, CLK_CON_DIV_CLKCMU_USB_DPGTC_BUSY, CLK_CON_DIV_CLKCMU_USB_DPGTC_ENABLE_AUTOMATIC_CLKGATING), | |
750 | CLK_DIV(CLKCMU_DISPAUD_AUD, GATE_CLKCMU_DISPAUD_AUD, CLK_CON_DIV_CLKCMU_DISPAUD_AUD_DIVRATIO, CLK_CON_DIV_CLKCMU_DISPAUD_AUD_BUSY, CLK_CON_DIV_CLKCMU_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING), | |
751 | CLK_DIV(CLKCMU_MFC_MFC, GATE_CLKCMU_MFC_MFC, CLK_CON_DIV_CLKCMU_MFC_MFC_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC_MFC_BUSY, CLK_CON_DIV_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING), | |
752 | CLK_DIV(CLKCMU_MFC_WFD, GATE_CLKCMU_MFC_WFD, CLK_CON_DIV_CLKCMU_MFC_WFD_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC_WFD_BUSY, CLK_CON_DIV_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING), | |
753 | CLK_DIV(CLKCMU_HPM, GATE_CLKCMU_HPM, CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, CLK_CON_DIV_CLKCMU_HPM_BUSY, CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING), | |
754 | CLK_DIV(CLKCMU_PERI_UART, GATE_CLKCMU_PERI_UART, CLK_CON_DIV_CLKCMU_PERI_UART_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_UART_BUSY, CLK_CON_DIV_CLKCMU_PERI_UART_ENABLE_AUTOMATIC_CLKGATING), | |
755 | CLK_DIV(CLKCMU_VIPX2_BUS, GATE_CLKCMU_VIPX2_BUS, CLK_CON_DIV_CLKCMU_VIPX2_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_VIPX2_BUS_BUSY, CLK_CON_DIV_CLKCMU_VIPX2_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
756 | CLK_DIV(CLKCMU_CIS_CLK3, GATE_CLKCMU_CIS_CLK3, CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING), | |
757 | CLK_DIV(PLL_MMC_DIV2, PLL_MMC, CLK_CON_DIV_PLL_MMC_DIV2_DIVRATIO, CLK_CON_DIV_PLL_MMC_DIV2_BUSY, CLK_CON_DIV_PLL_MMC_DIV2_ENABLE_AUTOMATIC_CLKGATING), | |
758 | CLK_DIV(DIV_CLK_CORE_BUSP, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING), | |
759 | CLK_DIV(DIV_CLK_CPUCL0_PCLK, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
760 | CLK_DIV(DIV_CLK_CPUCL0_CMUREF, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING), | |
761 | CLK_DIV(DIV_CLK_CLUSTER0_ACLK, GATE_CLK_CLUSTER0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
762 | CLK_DIV(DIV_CLK_CLUSTER0_PCLKDBG, GATE_CLK_CLUSTER0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), | |
763 | CLK_DIV(DIV_CLK_CLUSTER0_CNTCLK, GATE_CLK_CLUSTER0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK_ENABLE_AUTOMATIC_CLKGATING), | |
764 | CLK_DIV(DIV_CLK_CPUCL0_CPU, MUX_CLK_CPUCL0_PLL, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING), | |
765 | CLK_DIV(DIV_CLK_CPUCL1_PCLK, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
766 | CLK_DIV(DIV_CLK_CPUCL1_CMUREF, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING), | |
767 | CLK_DIV(DIV_CLK_CLUSTER1_ACLK, GATE_CLK_CLUSTER1_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
768 | CLK_DIV(DIV_CLK_CPUCL1_CPU, MUX_CLK_CPUCL1_PLL, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING), | |
769 | CLK_DIV(DIV_CLK_CLUSTER1_CNTCLK, GATE_CLK_CLUSTER1_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_ENABLE_AUTOMATIC_CLKGATING), | |
770 | CLK_DIV(DIV_CLK_CPUCL1_PCLKDBG, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), | |
771 | CLK_DIV(DIV_CLK_AUD_CPU, PLL_AUD, CLK_CON_DIV_DIV_CLK_AUD_CPU_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING), | |
772 | CLK_DIV(DIV_CLK_AUD_CPU_PCLKDBG, MUX_CLK_AUD_CPU_HCH, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), | |
773 | CLK_DIV(DIV_CLK_AUD_CPU_ACLK, MUX_CLK_AUD_CPU_HCH, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
774 | CLK_DIV(DIV_CLK_AUD_UAIF0, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING), | |
775 | CLK_DIV(DIV_CLK_AUD_AUDIF, PLL_AUD, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING), | |
776 | CLK_DIV(DIV_CLK_AUD_UAIF2, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING), | |
777 | CLK_DIV(DIV_CLK_AUD_UAIF1, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING), | |
778 | CLK_DIV(DIV_CLK_DISPAUD_BUSP, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_ENABLE_AUTOMATIC_CLKGATING), | |
779 | CLK_DIV(DIV_CLK_AUD_DSIF, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING), | |
780 | CLK_DIV(DIV_CLK_AUD_FM_SPDY, TICK_USB, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_BUSY, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_ENABLE_AUTOMATIC_CLKGATING), | |
781 | CLK_DIV(DIV_CLK_AUD_FM, MUX_CLK_AUD_FM, CLK_CON_DIV_DIV_CLK_AUD_FM_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_FM_BUSY, CLK_CON_DIV_DIV_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING), | |
782 | CLK_DIV(DIV_CLK_AUD_BUS, PLL_AUD, CLK_CON_DIV_DIV_CLK_AUD_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_BUS_BUSY, CLK_CON_DIV_DIV_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
783 | CLK_DIV(DIV_CLK_G2D_BUSP, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_DIV_DIV_CLK_G2D_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G2D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G2D_BUSP_ENABLE_AUTOMATIC_CLKGATING), | |
784 | CLK_DIV(DIV_CLK_G3D_BUSP, MUX_CLK_G3D_BUSD, CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING), | |
785 | CLK_DIV(DIV_CLK_G3D_BUSD, MUX_CLK_G3D_BUSD, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_G3D_BUSD_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING), | |
786 | CLK_DIV(DIV_CLK_ISP_BUSP, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_DIV_DIV_CLK_ISP_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_ISP_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ISP_BUSP_ENABLE_AUTOMATIC_CLKGATING), | |
787 | CLK_DIV(DIV_CLK_MFC_BUSP, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_DIV_DIV_CLK_MFC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MFC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MFC_BUSP_ENABLE_AUTOMATIC_CLKGATING), | |
788 | CLK_DIV(DIV_CLK_PERI_I2C, GATE_CLK_PERI_I2C, CLK_CON_DIV_DIV_CLK_PERI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERI_I2C_ENABLE_AUTOMATIC_CLKGATING), | |
789 | CLK_DIV(DIV_CLK_PERI_SPI0, GATE_CLK_PERI_SPI0, CLK_CON_DIV_DIV_CLK_PERI_SPI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_SPI0_BUSY, CLK_CON_DIV_DIV_CLK_PERI_SPI0_ENABLE_AUTOMATIC_CLKGATING), | |
790 | CLK_DIV(DIV_CLK_PERI_SPI1, GATE_CLK_PERI_SPI1, CLK_CON_DIV_DIV_CLK_PERI_SPI1_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_SPI1_BUSY, CLK_CON_DIV_DIV_CLK_PERI_SPI1_ENABLE_AUTOMATIC_CLKGATING), | |
791 | CLK_DIV(DIV_CLK_PERI_USI_I2C, GATE_CLK_PERI_USI_I2C, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_ENABLE_AUTOMATIC_CLKGATING), | |
792 | CLK_DIV(DIV_CLK_PERI_USI_USI, GATE_CLK_PERI_USI_USI, CLK_CON_DIV_DIV_CLK_PERI_USI_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI_USI_ENABLE_AUTOMATIC_CLKGATING), | |
793 | CLK_DIV(DIV_CLK_PERI_SPI2, GATE_CLK_PERI_SPI2, CLK_CON_DIV_DIV_CLK_PERI_SPI2_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_SPI2_BUSY, CLK_CON_DIV_DIV_CLK_PERI_SPI2_ENABLE_AUTOMATIC_CLKGATING), | |
794 | CLK_DIV(DIV_CLK_SHUB_USI01, MUX_CLK_SHUB_USI01, CLK_CON_DIV_DIV_CLK_SHUB_USI01_DIVRATIO, CLK_CON_DIV_DIV_CLK_SHUB_USI01_BUSY, CLK_CON_DIV_DIV_CLK_SHUB_USI01_ENABLE_AUTOMATIC_CLKGATING), | |
795 | CLK_DIV(DIV_CLK_SHUB_I2C, MUX_CLK_SHUB_I2C, CLK_CON_DIV_DIV_CLK_SHUB_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_SHUB_I2C_BUSY, CLK_CON_DIV_DIV_CLK_SHUB_I2C_ENABLE_AUTOMATIC_CLKGATING), | |
796 | CLK_DIV(DIV_CLK_SHUB_USI00, MUX_CLK_SHUB_USI00, CLK_CON_DIV_DIV_CLK_SHUB_USI00_DIVRATIO, CLK_CON_DIV_DIV_CLK_SHUB_USI00_BUSY, CLK_CON_DIV_DIV_CLK_SHUB_USI00_ENABLE_AUTOMATIC_CLKGATING), | |
797 | CLK_DIV(DIV_CLK_VIPX1_BUSP, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_DIV_DIV_CLK_VIPX1_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_VIPX1_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_VIPX1_BUSP_ENABLE_AUTOMATIC_CLKGATING), | |
798 | CLK_DIV(DIV_CLK_VIPX2_BUSP, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_DIV_DIV_CLK_VIPX2_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_VIPX2_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_VIPX2_BUSP_ENABLE_AUTOMATIC_CLKGATING), | |
799 | }; | |
800 | ||
801 | /*====================The section of GATEs===================*/ | |
802 | unsigned int cmucal_gate_size = 647; | |
803 | ||
804 | ||
805 | struct cmucal_gate cmucal_gate_list[] = { | |
806 | CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
807 | CLK_GATE(GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
808 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
809 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
810 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
811 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
812 | CLK_GATE(GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
813 | CLK_GATE(GOUT_BLK_APM_UID_RSTnSYNC_CLK_APM_BUS_IPCLKPORT_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
814 | CLK_GATE(GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
815 | CLK_GATE(GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
816 | CLK_GATE(CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
817 | CLK_GATE(GATE_CLKCMU_SHUB_BUS, MUX_CLKCMU_SHUB_BUS, CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
818 | CLK_GATE(CLKCMU_CMGP_BUS, DIV_CLK_APM_BUS, CLK_CON_GAT_CLKCMU_CMGP_BUS_CG_VAL, CLK_CON_GAT_CLKCMU_CMGP_BUS_MANUAL, CLK_CON_GAT_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
819 | CLK_GATE(GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
820 | CLK_GATE(GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
821 | CLK_GATE(GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
822 | CLK_GATE(GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
823 | CLK_GATE(GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
824 | CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
825 | CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
826 | CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
827 | CLK_GATE(GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
828 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
829 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
830 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
831 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
832 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
833 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
834 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
835 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
836 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
837 | CLK_GATE(GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
838 | CLK_GATE(GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
839 | CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
840 | CLK_GATE(GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
841 | CLK_GATE(GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
842 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
843 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
844 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
845 | CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
846 | CLK_GATE(GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
847 | CLK_GATE(GOUT_BLK_APM_UID_RSTnSYNC_CLK_APM_GREBE_IPCLKPORT_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
848 | CLK_GATE(GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING), | |
849 | CLK_GATE(CLK_BLK_APM_UID_RSTnSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK, OSCCLK_APM, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
850 | CLK_GATE(CLK_BLK_APM_UID_RSTnSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_APM, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
851 | CLK_GATE(CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
852 | CLK_GATE(GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
853 | CLK_GATE(GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
854 | CLK_GATE(GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
855 | CLK_GATE(GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
856 | CLK_GATE(GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
857 | CLK_GATE(CLK_BLK_CAM_UID_RSTnSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK, OSCCLK_CAM, CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
858 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_XIU_D_CAM, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM_ENABLE_AUTOMATIC_CLKGATING), | |
859 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_PCLK_PPMU_CAM, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM_ENABLE_AUTOMATIC_CLKGATING), | |
860 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_PPMU_CAM, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM_ENABLE_AUTOMATIC_CLKGATING), | |
861 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_SMMU_CAM, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM_ENABLE_AUTOMATIC_CLKGATING), | |
862 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_3AA, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA_ENABLE_AUTOMATIC_CLKGATING), | |
863 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_CSIS0, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING), | |
864 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_CSIS1, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING), | |
865 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_CSIS2, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING), | |
866 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_CSIS3, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING), | |
867 | CLK_GATE(GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD_ENABLE_AUTOMATIC_CLKGATING), | |
868 | CLK_GATE(GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
869 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0_ENABLE_AUTOMATIC_CLKGATING), | |
870 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_DMA, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING), | |
871 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE_ENABLE_AUTOMATIC_CLKGATING), | |
872 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_RDMA, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA_ENABLE_AUTOMATIC_CLKGATING), | |
873 | CLK_GATE(GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
874 | CLK_GATE(GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
875 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0_ENABLE_AUTOMATIC_CLKGATING), | |
876 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1_ENABLE_AUTOMATIC_CLKGATING), | |
877 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2_ENABLE_AUTOMATIC_CLKGATING), | |
878 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3_ENABLE_AUTOMATIC_CLKGATING), | |
879 | CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1_ENABLE_AUTOMATIC_CLKGATING), | |
880 | CLK_GATE(CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
881 | CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
882 | CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
883 | CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
884 | CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
885 | CLK_GATE(GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
886 | CLK_GATE(GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING), | |
887 | CLK_GATE(GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING), | |
888 | CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
889 | CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
890 | CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
891 | CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
892 | CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
893 | CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
894 | CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
895 | CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
896 | CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
897 | CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
898 | CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
899 | CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK, DIV_CLK_CMGP_USI00, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
900 | CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
901 | CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
902 | CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK, DIV_CLK_CMGP_USI01, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
903 | CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK, DIV_CLK_CMGP_USI02, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
904 | CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK, DIV_CLK_CMGP_USI03, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
905 | CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK, DIV_CLK_CMGP_USI04, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
906 | CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
907 | CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
908 | CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
909 | CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
910 | CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
911 | CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI00, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
912 | CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI01, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
913 | CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI02, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
914 | CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI03, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
915 | CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI04, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
916 | CLK_GATE(CLK_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_CMGP, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
917 | CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
918 | CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
919 | CLK_GATE(GATE_CLKCMU_G2D_MSCL, MUX_CLKCMU_G2D_MSCL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING), | |
920 | CLK_GATE(GATE_CLKCMU_DISPAUD_DISP, MUX_CLKCMU_DISPAUD_DISP, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING), | |
921 | CLK_GATE(GATE_CLKCMU_FSYS_MMC_EMBD, MUX_CLKCMU_FSYS_MMC_EMBD, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING), | |
922 | CLK_GATE(GATE_CLKCMU_FSYS_BUS, MUX_CLKCMU_FSYS_BUS, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
923 | CLK_GATE(GATE_CLKCMU_MODEM_SHARED0, PLL_SHARED0_DIV2, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING), | |
924 | CLK_GATE(GATE_CLKCMU_PERI_BUS, MUX_CLKCMU_PERI_BUS, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
925 | CLK_GATE(GATE_CLKCMU_PERI_IP, MUX_CLKCMU_PERI_IP, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING), | |
926 | CLK_GATE(GATE_CLKCMU_APM_BUS, MUX_CLKCMU_APM_BUS, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
927 | CLK_GATE(GATE_CLKCMU_FSYS_MMC_CARD, MUX_CLKCMU_FSYS_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING), | |
928 | CLK_GATE(GATE_CLKCMU_CIS_CLK0, MUX_CLKCMU_CIS_CLK0, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING), | |
929 | CLK_GATE(GATE_CLKCMU_CIS_CLK1, MUX_CLKCMU_CIS_CLK1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING), | |
930 | CLK_GATE(GATE_CLKCMU_CIS_CLK2, MUX_CLKCMU_CIS_CLK2, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING), | |
931 | CLK_GATE(GATE_CLKCMU_MODEM_SHARED1, PLL_SHARED1_DIV2, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING), | |
932 | CLK_GATE(GATE_CLKCMU_CORE_BUS, MUX_CLKCMU_CORE_BUS, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
933 | CLK_GATE(GATE_CLKCMU_CPUCL0_DBG, MUX_CLKCMU_CPUCL0_DBG, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING), | |
934 | CLK_GATE(GATE_CLKCMU_CORE_CCI, MUX_CLKCMU_CORE_CCI, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI_ENABLE_AUTOMATIC_CLKGATING), | |
935 | CLK_GATE(GATE_CLKCMU_CORE_G3D, MUX_CLKCMU_CORE_G3D, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING), | |
936 | CLK_GATE(GATE_CLKCMU_MIF_BUSP, MUX_CLKCMU_MIF_BUSP, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING), | |
937 | CLK_GATE(GATE_CLKCMU_FSYS_UFS_EMBD, MUX_CLKCMU_FSYS_UFS_EMBD, CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING), | |
938 | CLK_GATE(GATE_CLKCMU_CAM_BUS, MUX_CLKCMU_CAM_BUS, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
939 | CLK_GATE(GATE_CLKCMU_VIPX1_BUS, MUX_CLKCMU_VIPX1_BUS, CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
940 | CLK_GATE(GATE_CLKCMU_ISP_BUS, MUX_CLKCMU_ISP_BUS, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
941 | CLK_GATE(GATE_CLKCMU_ISP_VRA, MUX_CLKCMU_ISP_VRA, CLK_CON_GAT_GATE_CLKCMU_ISP_VRA_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISP_VRA_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING), | |
942 | CLK_GATE(GATE_CLKCMU_ISP_GDC, MUX_CLKCMU_ISP_GDC, CLK_CON_GAT_GATE_CLKCMU_ISP_GDC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISP_GDC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING), | |
943 | CLK_GATE(GATE_CLKCMU_G2D_G2D, MUX_CLKCMU_G2D_G2D, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING), | |
944 | CLK_GATE(GATE_CLKCMU_CPUCL0_SWITCH, MUX_CLKCMU_CPUCL0_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING), | |
945 | CLK_GATE(GATE_CLKCMU_CPUCL1_SWITCH, MUX_CLKCMU_CPUCL1_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING), | |
946 | CLK_GATE(GATE_CLKCMU_G3D_SWITCH, MUX_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING), | |
947 | CLK_GATE(GATE_CLKCMU_DISPAUD_CPU, MUX_CLKCMU_DISPAUD_CPU, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING), | |
948 | CLK_GATE(CLKCMU_MIF_SWITCH, MUX_CLKCMU_MIF_SWITCH, CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING), | |
949 | CLK_GATE(GATE_CLKCMU_USB_BUS, MUX_CLKCMU_USB_BUS, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
950 | CLK_GATE(GATE_CLKCMU_USB_USB30DRD, MUX_CLKCMU_USB_USB30DRD, CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD_ENABLE_AUTOMATIC_CLKGATING), | |
951 | CLK_GATE(GATE_CLKCMU_USB_DPGTC, MUX_CLKCMU_USB_DPGTC, CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC_ENABLE_AUTOMATIC_CLKGATING), | |
952 | CLK_GATE(GATE_CLKCMU_DISPAUD_AUD, MUX_CLKCMU_DISPAUD_AUD, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING), | |
953 | CLK_GATE(GATE_CLKCMU_MFC_MFC, MUX_CLKCMU_MFC_MFC, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING), | |
954 | CLK_GATE(GATE_CLKCMU_MFC_WFD, MUX_CLKCMU_MFC_WFD, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING), | |
955 | CLK_GATE(GATE_CLKCMU_HPM, MUX_CLKCMU_HPM, CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING), | |
956 | CLK_GATE(GATE_CLKCMU_PERI_UART, MUX_CLKCMU_PERI_UART, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_ENABLE_AUTOMATIC_CLKGATING), | |
957 | CLK_GATE(CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK, CLKCMU_OTP, CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
958 | CLK_GATE(GATE_CLKCMU_VIPX2_BUS, MUX_CLKCMU_VIPX2_BUS, CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS_ENABLE_AUTOMATIC_CLKGATING), | |
959 | CLK_GATE(GATE_CLKCMU_CIS_CLK3, MUX_CLKCMU_CIS_CLK3, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING), | |
960 | CLK_GATE(GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM, MUX_CLK_CORE_GIC, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), | |
961 | CLK_GATE(GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK, MUX_CLK_CORE_GIC, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
962 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
963 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
964 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
965 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
966 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
967 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
968 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
969 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
970 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
971 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
972 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
973 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
974 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
975 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
976 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
977 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
978 | CLK_GATE(GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
979 | CLK_GATE(GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
980 | CLK_GATE(GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
981 | CLK_GATE(GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
982 | CLK_GATE(GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
983 | CLK_GATE(GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
984 | CLK_GATE(GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
985 | CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_pclk, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
986 | CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
987 | CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
988 | CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
989 | CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), | |
990 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
991 | CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK, MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
992 | CLK_GATE(GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
993 | CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
994 | CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_CCI_IPCLKPORT_CLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
995 | CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_G3D_IPCLKPORT_CLK, MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
996 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
997 | CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_GIC_IPCLKPORT_CLK, MUX_CLK_CORE_GIC, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
998 | CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK, OSCCLK_CORE, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
999 | CLK_GATE(CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1000 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1001 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1002 | CLK_GATE(GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1003 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1004 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1005 | CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1006 | CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1007 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1008 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1009 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1010 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1011 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1012 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1013 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1014 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1015 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1016 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1017 | CLK_GATE(GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_ENABLE_AUTOMATIC_CLKGATING), | |
1018 | CLK_GATE(GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_ENABLE_AUTOMATIC_CLKGATING), | |
1019 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1020 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1021 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1022 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1023 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1024 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1025 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1026 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1027 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1028 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1029 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1030 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1031 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1032 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1033 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1034 | CLK_GATE(GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1035 | CLK_GATE(GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_pclk, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1036 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1037 | CLK_GATE(GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1038 | CLK_GATE(GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1039 | CLK_GATE(GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1040 | CLK_GATE(GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1041 | CLK_GATE(GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1042 | CLK_GATE(GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1043 | CLK_GATE(GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1044 | CLK_GATE(GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_i_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1045 | CLK_GATE(GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_i_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1046 | CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1047 | CLK_GATE(GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING), | |
1048 | CLK_GATE(GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1049 | CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_pclk, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1050 | CLK_GATE(GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1051 | CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1052 | CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1053 | CLK_GATE(GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1054 | CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1055 | CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK, MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1056 | CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1057 | CLK_GATE(GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING), | |
1058 | CLK_GATE(GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING), | |
1059 | CLK_GATE(GOUT_BLK_CORE_UID_DIT_IPCLKPORT_iClkL2A, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING), | |
1060 | CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1061 | CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1062 | CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1063 | CLK_GATE(GOUT_BLK_CORE_UID_AXI_US_A40_64to128_DIT_IPCLKPORT_aclk, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1064 | CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1065 | CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1066 | CLK_GATE(GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1067 | CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1068 | CLK_GATE(GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1069 | CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1070 | CLK_GATE(CLK_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK, OSCCLK_CPUCL0, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1071 | CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1072 | CLK_GATE(CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1073 | CLK_GATE(GATE_CLK_CLUSTER0_CPU, DIV_CLK_CPUCL0_CPU, CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU_CG_VAL, CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU_MANUAL, CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU_ENABLE_AUTOMATIC_CLKGATING), | |
1074 | CLK_GATE(GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1075 | CLK_GATE(GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING), | |
1076 | CLK_GATE(GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), | |
1077 | CLK_GATE(GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), | |
1078 | CLK_GATE(GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1079 | CLK_GATE(GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1080 | CLK_GATE(GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1081 | CLK_GATE(GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1082 | CLK_GATE(GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1083 | CLK_GATE(GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1084 | CLK_GATE(CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), | |
1085 | CLK_GATE(GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), | |
1086 | CLK_GATE(GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1087 | CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1088 | CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1089 | CLK_GATE(CLK_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK, OSCCLK_CPUCL1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1090 | CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER1_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1091 | CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1092 | CLK_GATE(GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM, DIV_CLK_CPUCL1_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1093 | CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_CPUCL1_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1094 | CLK_GATE(GATE_CLK_CLUSTER1_CPU, DIV_CLK_CPUCL1_CPU, CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU_CG_VAL, CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU_MANUAL, CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU_ENABLE_AUTOMATIC_CLKGATING), | |
1095 | CLK_GATE(CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), | |
1096 | CLK_GATE(GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1097 | CLK_GATE(GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1098 | CLK_GATE(GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1099 | CLK_GATE(GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER1_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1100 | CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB, DIV_CLK_AUD_CPU_ACLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING), | |
1101 | CLK_GATE(GOUT_BLK_DISPAUD_UID_AXI_US_32to128_IPCLKPORT_aclk, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1102 | CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK, MUX_CLK_AUD_CPU_HCH, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1103 | CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1104 | CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1105 | CLK_GATE(GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1106 | CLK_GATE(GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1107 | CLK_GATE(GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1108 | CLK_GATE(CLK_BLK_DISPAUD_UID_RSTnSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK, OSCCLK_DISPAUD, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1109 | CLK_GATE(GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK, DIV_CLK_AUD_AUDIF, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1110 | CLK_GATE(GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1111 | CLK_GATE(GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1112 | CLK_GATE(GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1113 | CLK_GATE(GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1114 | CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1115 | CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1116 | CLK_GATE(GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1117 | CLK_GATE(GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1118 | CLK_GATE(GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1119 | CLK_GATE(GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1120 | CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_ACLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1121 | CLK_GATE(CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1122 | CLK_GATE(GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1123 | CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY, DIV_CLK_AUD_FM, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_ENABLE_AUTOMATIC_CLKGATING), | |
1124 | CLK_GATE(GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1125 | CLK_GATE(GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING), | |
1126 | CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG_ENABLE_AUTOMATIC_CLKGATING), | |
1127 | CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK, DIV_CLK_AUD_DSIF, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1128 | CLK_GATE(GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING), | |
1129 | CLK_GATE(GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING), | |
1130 | CLK_GATE(GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING), | |
1131 | CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1132 | CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF, DIV_CLK_AUD_DSIF, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING), | |
1133 | CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY, MUX_CLK_AUD_FM, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY_ENABLE_AUTOMATIC_CLKGATING), | |
1134 | CLK_GATE(CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, MUX_CLK_AUD_UAIF0, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING), | |
1135 | CLK_GATE(CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1, MUX_CLK_AUD_UAIF1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING), | |
1136 | CLK_GATE(CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, MUX_CLK_AUD_UAIF2, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING), | |
1137 | CLK_GATE(CLK_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK, MUX_CLK_AUD_UAIF0, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1138 | CLK_GATE(CLK_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK, MUX_CLK_AUD_UAIF1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1139 | CLK_GATE(CLK_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK, MUX_CLK_AUD_UAIF2, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1140 | CLK_GATE(GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1141 | CLK_GATE(GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1142 | CLK_GATE(GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1143 | CLK_GATE(GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1144 | CLK_GATE(GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING), | |
1145 | CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7, MUX_CLK_AUD_CPU_HCH, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_ENABLE_AUTOMATIC_CLKGATING), | |
1146 | CLK_GATE(GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1147 | CLK_GATE(GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1148 | CLK_GATE(GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1149 | CLK_GATE(GOUT_BLK_FSYS_UID_RSTnSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1150 | CLK_GATE(GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1151 | CLK_GATE(GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1152 | CLK_GATE(GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1153 | CLK_GATE(GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1154 | CLK_GATE(GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1155 | CLK_GATE(GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1156 | CLK_GATE(CLK_BLK_FSYS_UID_RSTnSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK, OSCCLK_FSYS, CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1157 | CLK_GATE(GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1158 | CLK_GATE(GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1159 | CLK_GATE(CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1160 | CLK_GATE(GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1161 | CLK_GATE(GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1162 | CLK_GATE(GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1163 | CLK_GATE(GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1164 | CLK_GATE(GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1165 | CLK_GATE(GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1166 | CLK_GATE(GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1167 | CLK_GATE(GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1168 | CLK_GATE(GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1169 | CLK_GATE(GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN, MUX_CLKCMU_FSYS_MMC_CARD_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING), | |
1170 | CLK_GATE(GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN, MUX_CLKCMU_FSYS_MMC_EMBD_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING), | |
1171 | CLK_GATE(GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, MUX_CLKCMU_FSYS_UFS_EMBD_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING), | |
1172 | CLK_GATE(GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1173 | CLK_GATE(GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1174 | CLK_GATE(GOUT_BLK_G2D_UID_RSTnSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1175 | CLK_GATE(CLK_BLK_G2D_UID_RSTnSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK, OSCCLK_G2D, CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1176 | CLK_GATE(GOUT_BLK_G2D_UID_RSTnSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1177 | CLK_GATE(CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1178 | CLK_GATE(GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1179 | CLK_GATE(GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1180 | CLK_GATE(GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1181 | CLK_GATE(GOUT_BLK_G2D_UID_RSTnSYNC_CLK_G2D_G2D_IPCLKPORT_CLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1182 | CLK_GATE(GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1183 | CLK_GATE(GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING), | |
1184 | CLK_GATE(GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING), | |
1185 | CLK_GATE(GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1186 | CLK_GATE(GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1187 | CLK_GATE(GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1188 | CLK_GATE(GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1189 | CLK_GATE(GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1190 | CLK_GATE(GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1191 | CLK_GATE(GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1192 | CLK_GATE(GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING), | |
1193 | CLK_GATE(GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING), | |
1194 | CLK_GATE(GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1195 | CLK_GATE(GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1196 | CLK_GATE(GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1197 | CLK_GATE(GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1198 | CLK_GATE(GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1199 | CLK_GATE(GOUT_BLK_G3D_UID_RSTnSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1200 | CLK_GATE(CLK_BLK_G3D_UID_RSTnSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK, OSCCLK_G3D, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1201 | CLK_GATE(GOUT_BLK_G3D_UID_RSTnSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1202 | CLK_GATE(GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1203 | CLK_GATE(CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1204 | CLK_GATE(GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1205 | CLK_GATE(GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1206 | CLK_GATE(CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), | |
1207 | CLK_GATE(GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1208 | CLK_GATE(GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1209 | CLK_GATE(GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1210 | CLK_GATE(CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1211 | CLK_GATE(GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1212 | CLK_GATE(CLK_BLK_ISP_UID_RSTnSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK, OSCCLK_ISP, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1213 | CLK_GATE(CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1214 | CLK_GATE(GOUT_BLK_ISP_UID_RSTnSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1215 | CLK_GATE(GOUT_BLK_ISP_UID_RSTnSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1216 | CLK_GATE(GOUT_BLK_ISP_UID_RSTnSYNC_CLK_ISP_GDC_IPCLKPORT_CLK, MUX_CLKCMU_ISP_GDC_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1217 | CLK_GATE(GOUT_BLK_ISP_UID_RSTnSYNC_CLK_ISP_VRA_IPCLKPORT_CLK, MUX_CLKCMU_ISP_VRA_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1218 | CLK_GATE(GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1219 | CLK_GATE(GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1220 | CLK_GATE(GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1221 | CLK_GATE(GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1222 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_PCLK_PPMU_ISP1, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1_ENABLE_AUTOMATIC_CLKGATING), | |
1223 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_ENABLE_AUTOMATIC_CLKGATING), | |
1224 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA, MUX_CLKCMU_ISP_VRA_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_ENABLE_AUTOMATIC_CLKGATING), | |
1225 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC, MUX_CLKCMU_ISP_GDC_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC_ENABLE_AUTOMATIC_CLKGATING), | |
1226 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC_ENABLE_AUTOMATIC_CLKGATING), | |
1227 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_PPMU_ISP0, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0_ENABLE_AUTOMATIC_CLKGATING), | |
1228 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_PCLK_PPMU_ISP0, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0_ENABLE_AUTOMATIC_CLKGATING), | |
1229 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_SMMU_ISP0, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0_ENABLE_AUTOMATIC_CLKGATING), | |
1230 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_GDC, MUX_CLKCMU_ISP_GDC_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC_ENABLE_AUTOMATIC_CLKGATING), | |
1231 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_ISP, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP_ENABLE_AUTOMATIC_CLKGATING), | |
1232 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_VRA, MUX_CLKCMU_ISP_VRA_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA_ENABLE_AUTOMATIC_CLKGATING), | |
1233 | CLK_GATE(GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1234 | CLK_GATE(GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD_ENABLE_AUTOMATIC_CLKGATING), | |
1235 | CLK_GATE(GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC, MUX_CLKCMU_ISP_GDC_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING), | |
1236 | CLK_GATE(GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA, MUX_CLKCMU_ISP_VRA_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING), | |
1237 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_PPMU_ISP1, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1_ENABLE_AUTOMATIC_CLKGATING), | |
1238 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_SMMU_ISP1, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1_ENABLE_AUTOMATIC_CLKGATING), | |
1239 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_D_ISP, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP_ENABLE_AUTOMATIC_CLKGATING), | |
1240 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_MCSC, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC_ENABLE_AUTOMATIC_CLKGATING), | |
1241 | CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1242 | CLK_GATE(GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1243 | CLK_GATE(GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1244 | CLK_GATE(GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1245 | CLK_GATE(GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1246 | CLK_GATE(CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1247 | CLK_GATE(GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING), | |
1248 | CLK_GATE(GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), | |
1249 | CLK_GATE(GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI_ENABLE_AUTOMATIC_CLKGATING), | |
1250 | CLK_GATE(GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI_ENABLE_AUTOMATIC_CLKGATING), | |
1251 | CLK_GATE(GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1252 | CLK_GATE(GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1253 | CLK_GATE(GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1254 | CLK_GATE(GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1255 | CLK_GATE(GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1256 | CLK_GATE(GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1257 | CLK_GATE(GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1258 | CLK_GATE(GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1259 | CLK_GATE(GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1260 | CLK_GATE(GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1261 | CLK_GATE(GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1262 | CLK_GATE(GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING), | |
1263 | CLK_GATE(GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING), | |
1264 | CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_MFC_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1265 | CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_WFD_IPCLKPORT_CLK, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1266 | CLK_GATE(CLK_BLK_MFC_UID_RSTnSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK, OSCCLK_MFC, CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1267 | CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1268 | CLK_GATE(GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1269 | CLK_GATE(GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1270 | CLK_GATE(GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1271 | CLK_GATE(GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1272 | CLK_GATE(GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1273 | CLK_GATE(GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1274 | CLK_GATE(GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1275 | CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1276 | CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1277 | CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1278 | CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1279 | CLK_GATE(CLK_BLK_MIF_UID_RSTnSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, OSCCLK_MIF, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1280 | CLK_GATE(GOUT_BLK_MIF_UID_RSTnSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, CLK_MIF_BUSD, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1281 | CLK_GATE(GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK, CLK_MIF_BUSD, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1282 | CLK_GATE(GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1283 | CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_ENABLE_AUTOMATIC_CLKGATING), | |
1284 | CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1285 | CLK_GATE(GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1286 | CLK_GATE(GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1287 | CLK_GATE(GOUT_BLK_MIF_UID_RSTnSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1288 | CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1289 | CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1290 | CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1291 | CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1292 | CLK_GATE(GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1293 | CLK_GATE(CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1294 | CLK_GATE(CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1295 | CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1296 | CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_ENABLE_AUTOMATIC_CLKGATING), | |
1297 | CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING), | |
1298 | CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1299 | CLK_GATE(CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), | |
1300 | CLK_GATE(GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1301 | CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK, CLK_MIF_BUSD, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1302 | CLK_GATE(CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1303 | CLK_GATE(CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1304 | CLK_GATE(CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1305 | CLK_GATE(CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1306 | CLK_GATE(CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1307 | CLK_GATE(GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK, CLK_MIF1_BUSD, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1308 | CLK_GATE(GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), | |
1309 | CLK_GATE(GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1310 | CLK_GATE(GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1311 | CLK_GATE(GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF_ENABLE_AUTOMATIC_CLKGATING), | |
1312 | CLK_GATE(GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU_ENABLE_AUTOMATIC_CLKGATING), | |
1313 | CLK_GATE(GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING), | |
1314 | CLK_GATE(GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1315 | CLK_GATE(GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1316 | CLK_GATE(GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1317 | CLK_GATE(GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1318 | CLK_GATE(CLK_BLK_PERI_UID_RSTnSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK, OSCCLK_PERI, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1319 | CLK_GATE(GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_aclk, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1320 | CLK_GATE(GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1321 | CLK_GATE(GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1322 | CLK_GATE(GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1323 | CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_BUS_IPCLKPORT_CLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1324 | CLK_GATE(GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1325 | CLK_GATE(GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1326 | CLK_GATE(GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1327 | CLK_GATE(GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1328 | CLK_GATE(GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING), | |
1329 | CLK_GATE(GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1330 | CLK_GATE(GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1331 | CLK_GATE(GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1332 | CLK_GATE(GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1333 | CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1334 | CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1335 | CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1336 | CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1337 | CLK_GATE(GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1338 | CLK_GATE(GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1339 | CLK_GATE(GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1340 | CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_UART_IPCLKPORT_CLK, MUX_CLKCMU_PERI_UART_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1341 | CLK_GATE(GATE_CLK_PERI_I2C, MUX_CLKCMU_PERI_IP_USER, CLK_CON_GAT_GATE_CLK_PERI_I2C_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_I2C_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_I2C_ENABLE_AUTOMATIC_CLKGATING), | |
1342 | CLK_GATE(GATE_CLK_PERI_SPI0, MUX_CLKCMU_PERI_IP_USER, CLK_CON_GAT_GATE_CLK_PERI_SPI0_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_SPI0_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_SPI0_ENABLE_AUTOMATIC_CLKGATING), | |
1343 | CLK_GATE(GATE_CLK_PERI_SPI1, MUX_CLKCMU_PERI_IP_USER, CLK_CON_GAT_GATE_CLK_PERI_SPI1_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_SPI1_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_SPI1_ENABLE_AUTOMATIC_CLKGATING), | |
1344 | CLK_GATE(GATE_CLK_PERI_USI_USI, MUX_CLKCMU_PERI_IP_USER, CLK_CON_GAT_GATE_CLK_PERI_USI_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_USI_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_USI_USI_ENABLE_AUTOMATIC_CLKGATING), | |
1345 | CLK_GATE(GATE_CLK_PERI_USI_I2C, MUX_CLKCMU_PERI_IP_USER, CLK_CON_GAT_GATE_CLK_PERI_USI_I2C_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_USI_I2C_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_USI_I2C_ENABLE_AUTOMATIC_CLKGATING), | |
1346 | CLK_GATE(GATE_CLK_PERI_SPI2, MUX_CLKCMU_PERI_IP_USER, CLK_CON_GAT_GATE_CLK_PERI_SPI2_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_SPI2_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_SPI2_ENABLE_AUTOMATIC_CLKGATING), | |
1347 | CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_I2C_IPCLKPORT_CLK, DIV_CLK_PERI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1348 | CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK, DIV_CLK_PERI_SPI0, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1349 | CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK, DIV_CLK_PERI_SPI1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1350 | CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK, DIV_CLK_PERI_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1351 | CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK, DIV_CLK_PERI_USI_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1352 | CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK, DIV_CLK_PERI_SPI2, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1353 | CLK_GATE(CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1354 | CLK_GATE(GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK, MUX_CLKCMU_PERI_UART_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1355 | CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK, DIV_CLK_PERI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1356 | CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK, DIV_CLK_PERI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1357 | CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK, DIV_CLK_PERI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1358 | CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK, DIV_CLK_PERI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1359 | CLK_GATE(GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1360 | CLK_GATE(GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1361 | CLK_GATE(GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1362 | CLK_GATE(GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1363 | CLK_GATE(GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1364 | CLK_GATE(GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1365 | CLK_GATE(GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1366 | CLK_GATE(GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK, DIV_CLK_PERI_SPI0, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1367 | CLK_GATE(GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK, DIV_CLK_PERI_SPI1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1368 | CLK_GATE(GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK, DIV_CLK_PERI_SPI2, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1369 | CLK_GATE(GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1370 | CLK_GATE(GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1371 | CLK_GATE(CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1372 | CLK_GATE(GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1373 | CLK_GATE(GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1374 | CLK_GATE(GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1375 | CLK_GATE(GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1376 | CLK_GATE(GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1377 | CLK_GATE(GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1378 | CLK_GATE(GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1379 | CLK_GATE(GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1380 | CLK_GATE(GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_i_PCLK_S0, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING), | |
1381 | CLK_GATE(GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1382 | CLK_GATE(GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1383 | CLK_GATE(GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1384 | CLK_GATE(GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1385 | CLK_GATE(GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1386 | CLK_GATE(GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1387 | CLK_GATE(GOUT_BLK_SHUB_UID_RSTnSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1388 | CLK_GATE(GOUT_BLK_SHUB_UID_RSTnSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK, DIV_CLK_SHUB_I2C, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1389 | CLK_GATE(CLK_BLK_SHUB_UID_RSTnSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK, OSCCLK_RCO_SHUB__ALV, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1390 | CLK_GATE(CLK_BLK_SHUB_UID_RSTnSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK, RTCCLK_SHUB__ALV, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1391 | CLK_GATE(GOUT_BLK_SHUB_UID_RSTnSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK, DIV_CLK_SHUB_USI00, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1392 | CLK_GATE(GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1393 | CLK_GATE(GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK, DIV_CLK_SHUB_I2C, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1394 | CLK_GATE(GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1395 | CLK_GATE(GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK, DIV_CLK_SHUB_USI00, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1396 | CLK_GATE(GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1397 | CLK_GATE(CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1398 | CLK_GATE(GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1399 | CLK_GATE(GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1400 | CLK_GATE(GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1401 | CLK_GATE(GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1402 | CLK_GATE(GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_bus_clk_early, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING), | |
1403 | CLK_GATE(GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK, MUX_CLKCMU_USB_DPGTC_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1404 | CLK_GATE(GOUT_BLK_USB_UID_RSTnSYNC_CLK_USB_BUS_IPCLKPORT_CLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1405 | CLK_GATE(CLK_BLK_USB_UID_RSTnSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK, OSCCLK_USB, CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1406 | CLK_GATE(GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20_ENABLE_AUTOMATIC_CLKGATING), | |
1407 | CLK_GATE(GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1408 | CLK_GATE(GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1_ENABLE_AUTOMATIC_CLKGATING), | |
1409 | CLK_GATE(GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1410 | CLK_GATE(GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1411 | CLK_GATE(GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_aclk, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1412 | CLK_GATE(GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1413 | CLK_GATE(GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0_ENABLE_AUTOMATIC_CLKGATING), | |
1414 | CLK_GATE(GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_ref_clk, MUX_CLKCMU_USB_USB30DRD_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1415 | CLK_GATE(GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1416 | CLK_GATE(GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1417 | CLK_GATE(GOUT_BLK_VIPX1_UID_RSTnSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1418 | CLK_GATE(GOUT_BLK_VIPX1_UID_RSTnSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1419 | CLK_GATE(CLK_BLK_VIPX1_UID_RSTnSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK, OSCCLK_VIPX1, CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1420 | CLK_GATE(GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1421 | CLK_GATE(CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1422 | CLK_GATE(GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1423 | CLK_GATE(GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD_ENABLE_AUTOMATIC_CLKGATING), | |
1424 | CLK_GATE(GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1425 | CLK_GATE(GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1426 | CLK_GATE(GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1427 | CLK_GATE(GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1428 | CLK_GATE(GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1429 | CLK_GATE(GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1430 | CLK_GATE(GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1431 | CLK_GATE(GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1432 | CLK_GATE(GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1433 | CLK_GATE(GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1434 | CLK_GATE(GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1435 | CLK_GATE(CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1436 | CLK_GATE(GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1437 | CLK_GATE(GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1438 | CLK_GATE(GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1439 | CLK_GATE(GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1440 | CLK_GATE(GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1441 | CLK_GATE(GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1442 | CLK_GATE(GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1443 | CLK_GATE(GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1444 | CLK_GATE(GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), | |
1445 | CLK_GATE(GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1446 | CLK_GATE(GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1447 | CLK_GATE(GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), | |
1448 | CLK_GATE(GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD_ENABLE_AUTOMATIC_CLKGATING), | |
1449 | CLK_GATE(GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1450 | CLK_GATE(GOUT_BLK_VIPX2_UID_RSTnSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1451 | CLK_GATE(GOUT_BLK_VIPX2_UID_RSTnSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1452 | CLK_GATE(CLK_BLK_VIPX2_UID_RSTnSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK, OSCCLK_VIPX2, CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), | |
1453 | }; | |
1454 | ||
1455 | /*====================The section of FIXED RATEs===================*/ | |
1456 | unsigned int cmucal_fixed_rate_size = 41; | |
1457 | ||
1458 | ||
1459 | struct cmucal_clk_fixed_rate cmucal_fixed_rate_list[] = { | |
1460 | FIXEDRATE(OSCCLK_RCO_APM, 26000000, EMPTY_CAL_ID), | |
417ef672 | 1461 | FIXEDRATE(CLK_DLL_DCO, 360000000, EMPTY_CAL_ID), |
32760332 JJ |
1462 | FIXEDRATE(OSCCLK_APM, 26000000, EMPTY_CAL_ID), |
1463 | FIXEDRATE(OSCCLK_CAM, 26000000, EMPTY_CAL_ID), | |
1464 | FIXEDRATE(OSCCLK_RCO_CMGP, 30000000, EMPTY_CAL_ID), | |
1465 | FIXEDRATE(OSCCLK_CMGP, 26000000, EMPTY_CAL_ID), | |
1466 | FIXEDRATE(OSCCLK_CMU, 26000000, EMPTY_CAL_ID), | |
1467 | FIXEDRATE(OSCCLK_CORE, 26000000, EMPTY_CAL_ID), | |
1468 | FIXEDRATE(OSCCLK_CPUCL0, 26000000, EMPTY_CAL_ID), | |
1469 | FIXEDRATE(OSCCLK_EMBEDDED_CPUCL0, 26000000, EMPTY_CAL_ID), | |
1470 | FIXEDRATE(CLK_CLUSTER0_DIV_ACLK, 100000000, EMPTY_CAL_ID), | |
1471 | FIXEDRATE(CLK_CLUSTER0_DIV_PCLKDBG, 100000000, EMPTY_CAL_ID), | |
1472 | FIXEDRATE(CLK_CLUSTER0_DIV_CNTCLK, 100000000, EMPTY_CAL_ID), | |
1473 | FIXEDRATE(OSCCLK_CPUCL1, 26000000, EMPTY_CAL_ID), | |
1474 | FIXEDRATE(OSCCLK_EMBEDDED_CPUCL1, 26000000, EMPTY_CAL_ID), | |
1475 | FIXEDRATE(OSCCLK_DISPAUD, 26000000, EMPTY_CAL_ID), | |
1476 | FIXEDRATE(IOCLK_AUDIOCDCLK0, 10000000, EMPTY_CAL_ID), | |
1477 | FIXEDRATE(IOCLK_AUDIOCDCLK2, 10000000, EMPTY_CAL_ID), | |
1478 | FIXEDRATE(IOCLK_AUDIOCDCLK1, 100000000, EMPTY_CAL_ID), | |
1479 | FIXEDRATE(CLK_DEBUG_DECON, 100000000, EMPTY_CAL_ID), | |
1480 | FIXEDRATE(TICK_USB, 60000000, EMPTY_CAL_ID), | |
1481 | FIXEDRATE(OSCCLK_FSYS, 26000000, EMPTY_CAL_ID), | |
1482 | FIXEDRATE(OSCCLK_G2D, 26000000, EMPTY_CAL_ID), | |
1483 | FIXEDRATE(OSCCLK_G3D, 26000000, EMPTY_CAL_ID), | |
1484 | FIXEDRATE(OSCCLK_ISP, 26000000, EMPTY_CAL_ID), | |
1485 | FIXEDRATE(OSCCLK_MFC, 26000000, EMPTY_CAL_ID), | |
1486 | FIXEDRATE(CLKCMU_MIF_SWITCH_CLKOUT, 1600000000, EMPTY_CAL_ID), | |
1487 | FIXEDRATE(OSCCLK_MIF, 26000000, EMPTY_CAL_ID), | |
1488 | FIXEDRATE(OSCCLK_MIF1, 100000000, EMPTY_CAL_ID), | |
1489 | FIXEDRATE(OSCCLK_PERI, 26000000, EMPTY_CAL_ID), | |
1490 | FIXEDRATE(OSCCLK_RCO_SHUB__ALV, 26000000, EMPTY_CAL_ID), | |
1491 | FIXEDRATE(RTCCLK_SHUB__ALV, 26000000, EMPTY_CAL_ID), | |
1492 | FIXEDRATE(OSCCLK_USB, 26000000, EMPTY_CAL_ID), | |
1493 | FIXEDRATE(RTC_CLK_USB__ALV, 26000000, EMPTY_CAL_ID), | |
1494 | FIXEDRATE(O_USB20_PHY_CLOCK, 60000000, EMPTY_CAL_ID), | |
1495 | FIXEDRATE(O_USB30_PHY_RX0CLK_0, 250000000, EMPTY_CAL_ID), | |
1496 | FIXEDRATE(O_USB30_PHY_RX0CLK_1, 250000000, EMPTY_CAL_ID), | |
1497 | FIXEDRATE(O_USB30_PIPE_PCLK_0, 125000000, EMPTY_CAL_ID), | |
1498 | FIXEDRATE(O_USB30_PIPE_PCLK_1, 125000000, EMPTY_CAL_ID), | |
1499 | FIXEDRATE(OSCCLK_VIPX1, 26000000, EMPTY_CAL_ID), | |
1500 | FIXEDRATE(OSCCLK_VIPX2, 26000000, EMPTY_CAL_ID), | |
1501 | }; | |
1502 | ||
1503 | /*====================The section of FIXED FACTORs===================*/ | |
1504 | unsigned int cmucal_fixed_factor_size = 3; | |
1505 | ||
1506 | ||
1507 | struct cmucal_clk_fixed_factor cmucal_fixed_factor_list[] = { | |
1508 | FIXEDFACTOR(CLKCMU_OTP, OSCCLK_CMU, 7, CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING), | |
1509 | FIXEDFACTOR(CLK_MIF_BUSD, MUX_CLK_MIF_DDRPHY_CLK2X, 7, CLK_CON_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING), | |
1510 | FIXEDFACTOR(CLK_MIF1_BUSD, MUX_CLK_MIF1_DDRPHY_CLK2X, 7, CLK_CON_DIV_CLK_MIF1_BUSD_ENABLE_AUTOMATIC_CLKGATING), | |
1511 | }; |