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a7e79840 RK |
1 | /* |
2 | * Page table support for the Hexagon architecture | |
3 | * | |
e1858b2a | 4 | * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved. |
a7e79840 RK |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 and | |
8 | * only version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
18 | * 02110-1301, USA. | |
19 | */ | |
20 | ||
21 | #ifndef _ASM_PGTABLE_H | |
22 | #define _ASM_PGTABLE_H | |
23 | ||
24 | /* | |
25 | * Page table definitions for Qualcomm Hexagon processor. | |
26 | */ | |
27 | #include <linux/swap.h> | |
28 | #include <asm/page.h> | |
9849a569 | 29 | #define __ARCH_USE_5LEVEL_HACK |
a7e79840 RK |
30 | #include <asm-generic/pgtable-nopmd.h> |
31 | ||
32 | /* A handy thing to have if one has the RAM. Declared in head.S */ | |
33 | extern unsigned long empty_zero_page; | |
34 | extern unsigned long zero_page_mask; | |
35 | ||
36 | /* | |
37 | * The PTE model described here is that of the Hexagon Virtual Machine, | |
38 | * which autonomously walks 2-level page tables. At a lower level, we | |
39 | * also describe the RISCish software-loaded TLB entry structure of | |
40 | * the underlying Hexagon processor. A kernel built to run on the | |
41 | * virtual machine has no need to know about the underlying hardware. | |
42 | */ | |
43 | #include <asm/vm_mmu.h> | |
44 | ||
45 | /* | |
46 | * To maximize the comfort level for the PTE manipulation macros, | |
47 | * define the "well known" architecture-specific bits. | |
48 | */ | |
49 | #define _PAGE_READ __HVM_PTE_R | |
50 | #define _PAGE_WRITE __HVM_PTE_W | |
51 | #define _PAGE_EXECUTE __HVM_PTE_X | |
52 | #define _PAGE_USER __HVM_PTE_U | |
53 | ||
54 | /* | |
55 | * We have a total of 4 "soft" bits available in the abstract PTE. | |
56 | * The two mandatory software bits are Dirty and Accessed. | |
57 | * To make nonlinear swap work according to the more recent | |
58 | * model, we want a low order "Present" bit to indicate whether | |
59 | * the PTE describes MMU programming or swap space. | |
60 | */ | |
61 | #define _PAGE_PRESENT (1<<0) | |
62 | #define _PAGE_DIRTY (1<<1) | |
63 | #define _PAGE_ACCESSED (1<<2) | |
64 | ||
a7e79840 RK |
65 | /* |
66 | * For now, let's say that Valid and Present are the same thing. | |
67 | * Alternatively, we could say that it's the "or" of R, W, and X | |
68 | * permissions. | |
69 | */ | |
70 | #define _PAGE_VALID _PAGE_PRESENT | |
71 | ||
72 | /* | |
73 | * We're not defining _PAGE_GLOBAL here, since there's no concept | |
74 | * of global pages or ASIDs exposed to the Hexagon Virtual Machine, | |
75 | * and we want to use the same page table structures and macros in | |
76 | * the native kernel as we do in the virtual machine kernel. | |
77 | * So we'll put up with a bit of inefficiency for now... | |
78 | */ | |
79 | ||
80 | /* | |
81 | * Top "FOURTH" level (pgd), which for the Hexagon VM is really | |
82 | * only the second from the bottom, pgd and pud both being collapsed. | |
83 | * Each entry represents 4MB of virtual address space, 4K of table | |
84 | * thus maps the full 4GB. | |
85 | */ | |
86 | #define PGDIR_SHIFT 22 | |
87 | #define PTRS_PER_PGD 1024 | |
88 | ||
89 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
90 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
91 | ||
92 | #ifdef CONFIG_PAGE_SIZE_4KB | |
93 | #define PTRS_PER_PTE 1024 | |
94 | #endif | |
95 | ||
96 | #ifdef CONFIG_PAGE_SIZE_16KB | |
97 | #define PTRS_PER_PTE 256 | |
98 | #endif | |
99 | ||
100 | #ifdef CONFIG_PAGE_SIZE_64KB | |
101 | #define PTRS_PER_PTE 64 | |
102 | #endif | |
103 | ||
104 | #ifdef CONFIG_PAGE_SIZE_256KB | |
105 | #define PTRS_PER_PTE 16 | |
106 | #endif | |
107 | ||
108 | #ifdef CONFIG_PAGE_SIZE_1MB | |
109 | #define PTRS_PER_PTE 4 | |
110 | #endif | |
111 | ||
112 | /* Any bigger and the PTE disappears. */ | |
113 | #define pgd_ERROR(e) \ | |
114 | printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__,\ | |
115 | pgd_val(e)) | |
116 | ||
117 | /* | |
118 | * Page Protection Constants. Includes (in this variant) cache attributes. | |
119 | */ | |
120 | extern unsigned long _dflt_cache_att; | |
121 | ||
122 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER | \ | |
123 | _dflt_cache_att) | |
124 | #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | \ | |
125 | _PAGE_READ | _PAGE_EXECUTE | _dflt_cache_att) | |
126 | #define PAGE_COPY PAGE_READONLY | |
127 | #define PAGE_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \ | |
128 | _PAGE_READ | _PAGE_EXECUTE | _dflt_cache_att) | |
129 | #define PAGE_COPY_EXEC PAGE_EXEC | |
130 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | \ | |
131 | _PAGE_EXECUTE | _PAGE_WRITE | _dflt_cache_att) | |
132 | #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | \ | |
133 | _PAGE_WRITE | _PAGE_EXECUTE | _dflt_cache_att) | |
134 | ||
135 | ||
136 | /* | |
137 | * Aliases for mapping mmap() protection bits to page protections. | |
138 | * These get used for static initialization, so using the _dflt_cache_att | |
139 | * variable for the default cache attribute isn't workable. If the | |
140 | * default gets changed at boot time, the boot option code has to | |
141 | * update data structures like the protaction_map[] array. | |
142 | */ | |
143 | #define CACHEDEF (CACHE_DEFAULT << 6) | |
144 | ||
145 | /* Private (copy-on-write) page protections. */ | |
146 | #define __P000 __pgprot(_PAGE_PRESENT | _PAGE_USER | CACHEDEF) | |
147 | #define __P001 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | CACHEDEF) | |
148 | #define __P010 __P000 /* Write-only copy-on-write */ | |
149 | #define __P011 __P001 /* Read/Write copy-on-write */ | |
150 | #define __P100 __pgprot(_PAGE_PRESENT | _PAGE_USER | \ | |
151 | _PAGE_EXECUTE | CACHEDEF) | |
152 | #define __P101 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_EXECUTE | \ | |
153 | _PAGE_READ | CACHEDEF) | |
154 | #define __P110 __P100 /* Write/execute copy-on-write */ | |
155 | #define __P111 __P101 /* Read/Write/Execute, copy-on-write */ | |
156 | ||
157 | /* Shared page protections. */ | |
158 | #define __S000 __P000 | |
159 | #define __S001 __P001 | |
160 | #define __S010 __pgprot(_PAGE_PRESENT | _PAGE_USER | \ | |
161 | _PAGE_WRITE | CACHEDEF) | |
162 | #define __S011 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | \ | |
163 | _PAGE_WRITE | CACHEDEF) | |
164 | #define __S100 __pgprot(_PAGE_PRESENT | _PAGE_USER | \ | |
165 | _PAGE_EXECUTE | CACHEDEF) | |
166 | #define __S101 __P101 | |
167 | #define __S110 __pgprot(_PAGE_PRESENT | _PAGE_USER | \ | |
168 | _PAGE_EXECUTE | _PAGE_WRITE | CACHEDEF) | |
169 | #define __S111 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | \ | |
170 | _PAGE_EXECUTE | _PAGE_WRITE | CACHEDEF) | |
171 | ||
172 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* located in head.S */ | |
173 | ||
174 | /* Seems to be zero even in architectures where the zero page is firewalled? */ | |
d016bf7e | 175 | #define FIRST_USER_ADDRESS 0UL |
a7e79840 RK |
176 | #define pte_special(pte) 0 |
177 | #define pte_mkspecial(pte) (pte) | |
178 | ||
179 | /* HUGETLB not working currently */ | |
180 | #ifdef CONFIG_HUGETLB_PAGE | |
181 | #define pte_mkhuge(pte) __pte((pte_val(pte) & ~0x3) | HVM_HUGEPAGE_SIZE) | |
182 | #endif | |
183 | ||
184 | /* | |
185 | * For now, assume that higher-level code will do TLB/MMU invalidations | |
186 | * and don't insert that overhead into this low-level function. | |
187 | */ | |
188 | extern void sync_icache_dcache(pte_t pte); | |
189 | ||
190 | #define pte_present_exec_user(pte) \ | |
191 | ((pte_val(pte) & (_PAGE_EXECUTE | _PAGE_USER)) == \ | |
192 | (_PAGE_EXECUTE | _PAGE_USER)) | |
193 | ||
194 | static inline void set_pte(pte_t *ptep, pte_t pteval) | |
195 | { | |
196 | /* should really be using pte_exec, if it weren't declared later. */ | |
197 | if (pte_present_exec_user(pteval)) | |
198 | sync_icache_dcache(pteval); | |
199 | ||
200 | *ptep = pteval; | |
201 | } | |
202 | ||
203 | /* | |
204 | * For the Hexagon Virtual Machine MMU (or its emulation), a null/invalid | |
205 | * L1 PTE (PMD/PGD) has 7 in the least significant bits. For the L2 PTE | |
206 | * (Linux PTE), the key is to have bits 11..9 all zero. We'd use 0x7 | |
207 | * as a universal null entry, but some of those least significant bits | |
208 | * are interpreted by software. | |
209 | */ | |
210 | #define _NULL_PMD 0x7 | |
211 | #define _NULL_PTE 0x0 | |
212 | ||
213 | static inline void pmd_clear(pmd_t *pmd_entry_ptr) | |
214 | { | |
215 | pmd_val(*pmd_entry_ptr) = _NULL_PMD; | |
216 | } | |
217 | ||
218 | /* | |
219 | * Conveniently, a null PTE value is invalid. | |
220 | */ | |
221 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, | |
222 | pte_t *ptep) | |
223 | { | |
224 | pte_val(*ptep) = _NULL_PTE; | |
225 | } | |
226 | ||
227 | #ifdef NEED_PMD_INDEX_DESPITE_BEING_2_LEVEL | |
228 | /** | |
229 | * pmd_index - returns the index of the entry in the PMD page | |
230 | * which would control the given virtual address | |
231 | */ | |
232 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
233 | ||
234 | #endif | |
235 | ||
236 | /** | |
237 | * pgd_index - returns the index of the entry in the PGD page | |
238 | * which would control the given virtual address | |
239 | * | |
240 | * This returns the *index* for the address in the pgd_t | |
241 | */ | |
242 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) | |
243 | ||
244 | /* | |
245 | * pgd_offset - find an offset in a page-table-directory | |
246 | */ | |
247 | #define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) | |
248 | ||
249 | /* | |
250 | * pgd_offset_k - get kernel (init_mm) pgd entry pointer for addr | |
251 | */ | |
252 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
253 | ||
254 | /** | |
255 | * pmd_none - check if pmd_entry is mapped | |
256 | * @pmd_entry: pmd entry | |
257 | * | |
258 | * MIPS checks it against that "invalid pte table" thing. | |
259 | */ | |
260 | static inline int pmd_none(pmd_t pmd) | |
261 | { | |
262 | return pmd_val(pmd) == _NULL_PMD; | |
263 | } | |
264 | ||
265 | /** | |
266 | * pmd_present - is there a page table behind this? | |
267 | * Essentially the inverse of pmd_none. We maybe | |
268 | * save an inline instruction by defining it this | |
269 | * way, instead of simply "!pmd_none". | |
270 | */ | |
271 | static inline int pmd_present(pmd_t pmd) | |
272 | { | |
273 | return pmd_val(pmd) != (unsigned long)_NULL_PMD; | |
274 | } | |
275 | ||
276 | /** | |
277 | * pmd_bad - check if a PMD entry is "bad". That might mean swapped out. | |
278 | * As we have no known cause of badness, it's null, as it is for many | |
279 | * architectures. | |
280 | */ | |
281 | static inline int pmd_bad(pmd_t pmd) | |
282 | { | |
283 | return 0; | |
284 | } | |
285 | ||
286 | /* | |
287 | * pmd_page - converts a PMD entry to a page pointer | |
288 | */ | |
289 | #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) | |
290 | #define pmd_pgtable(pmd) pmd_page(pmd) | |
291 | ||
292 | /** | |
293 | * pte_none - check if pte is mapped | |
294 | * @pte: pte_t entry | |
295 | */ | |
296 | static inline int pte_none(pte_t pte) | |
297 | { | |
298 | return pte_val(pte) == _NULL_PTE; | |
299 | }; | |
300 | ||
301 | /* | |
302 | * pte_present - check if page is present | |
303 | */ | |
304 | static inline int pte_present(pte_t pte) | |
305 | { | |
306 | return pte_val(pte) & _PAGE_PRESENT; | |
307 | } | |
308 | ||
309 | /* mk_pte - make a PTE out of a page pointer and protection bits */ | |
310 | #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) | |
311 | ||
312 | /* pte_page - returns a page (frame pointer/descriptor?) based on a PTE */ | |
313 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
314 | ||
315 | /* pte_mkold - mark PTE as not recently accessed */ | |
316 | static inline pte_t pte_mkold(pte_t pte) | |
317 | { | |
318 | pte_val(pte) &= ~_PAGE_ACCESSED; | |
319 | return pte; | |
320 | } | |
321 | ||
322 | /* pte_mkyoung - mark PTE as recently accessed */ | |
323 | static inline pte_t pte_mkyoung(pte_t pte) | |
324 | { | |
325 | pte_val(pte) |= _PAGE_ACCESSED; | |
326 | return pte; | |
327 | } | |
328 | ||
329 | /* pte_mkclean - mark page as in sync with backing store */ | |
330 | static inline pte_t pte_mkclean(pte_t pte) | |
331 | { | |
332 | pte_val(pte) &= ~_PAGE_DIRTY; | |
333 | return pte; | |
334 | } | |
335 | ||
336 | /* pte_mkdirty - mark page as modified */ | |
337 | static inline pte_t pte_mkdirty(pte_t pte) | |
338 | { | |
339 | pte_val(pte) |= _PAGE_DIRTY; | |
340 | return pte; | |
341 | } | |
342 | ||
343 | /* pte_young - "is PTE marked as accessed"? */ | |
344 | static inline int pte_young(pte_t pte) | |
345 | { | |
346 | return pte_val(pte) & _PAGE_ACCESSED; | |
347 | } | |
348 | ||
349 | /* pte_dirty - "is PTE dirty?" */ | |
350 | static inline int pte_dirty(pte_t pte) | |
351 | { | |
352 | return pte_val(pte) & _PAGE_DIRTY; | |
353 | } | |
354 | ||
355 | /* pte_modify - set protection bits on PTE */ | |
356 | static inline pte_t pte_modify(pte_t pte, pgprot_t prot) | |
357 | { | |
358 | pte_val(pte) &= PAGE_MASK; | |
359 | pte_val(pte) |= pgprot_val(prot); | |
360 | return pte; | |
361 | } | |
362 | ||
363 | /* pte_wrprotect - mark page as not writable */ | |
364 | static inline pte_t pte_wrprotect(pte_t pte) | |
365 | { | |
366 | pte_val(pte) &= ~_PAGE_WRITE; | |
367 | return pte; | |
368 | } | |
369 | ||
370 | /* pte_mkwrite - mark page as writable */ | |
371 | static inline pte_t pte_mkwrite(pte_t pte) | |
372 | { | |
373 | pte_val(pte) |= _PAGE_WRITE; | |
374 | return pte; | |
375 | } | |
376 | ||
377 | /* pte_mkexec - mark PTE as executable */ | |
378 | static inline pte_t pte_mkexec(pte_t pte) | |
379 | { | |
380 | pte_val(pte) |= _PAGE_EXECUTE; | |
381 | return pte; | |
382 | } | |
383 | ||
384 | /* pte_read - "is PTE marked as readable?" */ | |
385 | static inline int pte_read(pte_t pte) | |
386 | { | |
387 | return pte_val(pte) & _PAGE_READ; | |
388 | } | |
389 | ||
390 | /* pte_write - "is PTE marked as writable?" */ | |
391 | static inline int pte_write(pte_t pte) | |
392 | { | |
393 | return pte_val(pte) & _PAGE_WRITE; | |
394 | } | |
395 | ||
396 | ||
397 | /* pte_exec - "is PTE marked as executable?" */ | |
398 | static inline int pte_exec(pte_t pte) | |
399 | { | |
400 | return pte_val(pte) & _PAGE_EXECUTE; | |
401 | } | |
402 | ||
403 | /* __pte_to_swp_entry - extract swap entry from PTE */ | |
404 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
405 | ||
406 | /* __swp_entry_to_pte - extract PTE from swap entry */ | |
407 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
408 | ||
409 | /* pfn_pte - convert page number and protection value to page table entry */ | |
410 | #define pfn_pte(pfn, pgprot) __pte((pfn << PAGE_SHIFT) | pgprot_val(pgprot)) | |
411 | ||
412 | /* pte_pfn - convert pte to page frame number */ | |
413 | #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) | |
414 | #define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval)) | |
415 | ||
416 | /* | |
417 | * set_pte_at - update page table and do whatever magic may be | |
418 | * necessary to make the underlying hardware/firmware take note. | |
419 | * | |
420 | * VM may require a virtual instruction to alert the MMU. | |
421 | */ | |
422 | #define set_pte_at(mm, addr, ptep, pte) set_pte(ptep, pte) | |
423 | ||
424 | /* | |
425 | * May need to invoke the virtual machine as well... | |
426 | */ | |
427 | #define pte_unmap(pte) do { } while (0) | |
428 | #define pte_unmap_nested(pte) do { } while (0) | |
429 | ||
430 | /* | |
431 | * pte_offset_map - returns the linear address of the page table entry | |
432 | * corresponding to an address | |
433 | */ | |
434 | #define pte_offset_map(dir, address) \ | |
435 | ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) | |
436 | ||
437 | #define pte_offset_map_nested(pmd, addr) pte_offset_map(pmd, addr) | |
438 | ||
439 | /* pte_offset_kernel - kernel version of pte_offset */ | |
440 | #define pte_offset_kernel(dir, address) \ | |
441 | ((pte_t *) (unsigned long) __va(pmd_val(*dir) & PAGE_MASK) \ | |
442 | + __pte_offset(address)) | |
443 | ||
444 | /* ZERO_PAGE - returns the globally shared zero page */ | |
445 | #define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page)) | |
446 | ||
447 | #define __pte_offset(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | |
448 | ||
a7e79840 RK |
449 | /* I think this is in case we have page table caches; needed by init/main.c */ |
450 | #define pgtable_cache_init() do { } while (0) | |
451 | ||
452 | /* | |
d99f95e6 KS |
453 | * Swap/file PTE definitions. If _PAGE_PRESENT is zero, the rest of the PTE is |
454 | * interpreted as swap information. The remaining free bits are interpreted as | |
455 | * swap type/offset tuple. Rather than have the TLB fill handler test | |
456 | * _PAGE_PRESENT, we're going to reserve the permissions bits and set them to | |
457 | * all zeros for swap entries, which speeds up the miss handler at the cost of | |
458 | * 3 bits of offset. That trade-off can be revisited if necessary, but Hexagon | |
459 | * processor architecture and target applications suggest a lot of TLB misses | |
460 | * and not much swap space. | |
a7e79840 RK |
461 | * |
462 | * Format of swap PTE: | |
463 | * bit 0: Present (zero) | |
d99f95e6 KS |
464 | * bits 1-5: swap type (arch independent layer uses 5 bits max) |
465 | * bits 6-9: bits 3:0 of offset | |
466 | * bits 10-12: effectively _PAGE_PROTNONE (all zero) | |
467 | * bits 13-31: bits 22:4 of swap offset | |
a7e79840 RK |
468 | * |
469 | * The split offset makes some of the following macros a little gnarly, | |
470 | * but there's plenty of precedent for this sort of thing. | |
471 | */ | |
a7e79840 RK |
472 | |
473 | /* Used for swap PTEs */ | |
d99f95e6 | 474 | #define __swp_type(swp_pte) (((swp_pte).val >> 1) & 0x1f) |
a7e79840 RK |
475 | |
476 | #define __swp_offset(swp_pte) \ | |
d99f95e6 | 477 | ((((swp_pte).val >> 6) & 0xf) | (((swp_pte).val >> 9) & 0x7ffff0)) |
a7e79840 RK |
478 | |
479 | #define __swp_entry(type, offset) \ | |
480 | ((swp_entry_t) { \ | |
d99f95e6 KS |
481 | ((type << 1) | \ |
482 | ((offset & 0x7ffff0) << 9) | ((offset & 0xf) << 6)) }) | |
a7e79840 RK |
483 | |
484 | /* Oh boy. There are a lot of possible arch overrides found in this file. */ | |
485 | #include <asm-generic/pgtable.h> | |
486 | ||
487 | #endif |