Commit | Line | Data |
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51f89798 JY |
1 | /* |
2 | * platform.c | |
3 | * | |
4 | * clock source setting and resource config | |
5 | * | |
6 | * Created on: Dec 4, 2013 | |
7 | * Author: amlogic | |
8 | */ | |
9 | ||
10 | #include <linux/platform_device.h> | |
11 | #include <linux/version.h> | |
12 | #include <linux/pm.h> | |
13 | #include <linux/of.h> | |
14 | #include <linux/module.h> /* kernel module definitions */ | |
15 | #include <linux/ioport.h> /* request_mem_region */ | |
16 | #include <linux/slab.h> | |
17 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29)) | |
18 | #include <mach/register.h> | |
19 | #include <mach/irqs.h> | |
20 | #include <mach/io.h> | |
21 | #endif | |
22 | #include <asm/io.h> | |
d3697437 | 23 | #if defined(CONFIG_GPU_THERMAL) |
51f89798 JY |
24 | #include <linux/gpu_cooling.h> |
25 | #include <linux/gpucore_cooling.h> | |
26 | #include <linux/amlogic/aml_thermal_hw.h> | |
27 | #endif | |
d3697437 HB |
28 | #if defined(CONFIG_AMLOGIC_GPU_THERMAL) |
29 | #include <linux/amlogic/gpu_cooling.h> | |
30 | #include <linux/amlogic/gpucore_cooling.h> | |
31 | #include <linux/amlogic/aml_thermal_hw.h> | |
32 | #endif | |
51f89798 JY |
33 | |
34 | #include "mali_scaling.h" | |
35 | #include "mali_clock.h" | |
36 | #include "meson_main2.h" | |
37 | ||
38 | /* | |
39 | * For Meson 8 M2. | |
40 | * | |
41 | */ | |
42 | static void mali_plat_preheat(void); | |
43 | static mali_plat_info_t mali_plat_data = { | |
44 | .bst_gpu = 210, /* threshold for boosting gpu. */ | |
45 | .bst_pp = 160, /* threshold for boosting PP. */ | |
46 | .have_switch = 1, | |
47 | .limit_on = 1, | |
48 | .plat_preheat = mali_plat_preheat, | |
49 | }; | |
50 | ||
51 | static void mali_plat_preheat(void) | |
52 | { | |
53 | #ifndef CONFIG_MALI_DVFS | |
54 | u32 pre_fs; | |
55 | u32 clk, pp; | |
56 | ||
57 | if (get_mali_schel_mode() != MALI_PP_FS_SCALING) | |
58 | return; | |
59 | ||
60 | get_mali_rt_clkpp(&clk, &pp); | |
61 | pre_fs = mali_plat_data.def_clock + 1; | |
62 | if (clk < pre_fs) | |
63 | clk = pre_fs; | |
64 | if (pp < mali_plat_data.sc_mpp) | |
65 | pp = mali_plat_data.sc_mpp; | |
66 | set_mali_rt_clkpp(clk, pp, 1); | |
67 | #endif | |
68 | } | |
69 | ||
70 | mali_plat_info_t* get_mali_plat_data(void) { | |
71 | return &mali_plat_data; | |
72 | } | |
73 | ||
74 | int get_mali_freq_level(int freq) | |
75 | { | |
76 | int i = 0, level = -1; | |
77 | int mali_freq_num; | |
78 | ||
79 | if (freq < 0) | |
80 | return level; | |
81 | ||
82 | mali_freq_num = mali_plat_data.dvfs_table_size - 1; | |
902adbb7 | 83 | if (freq < mali_plat_data.clk_sample[0]) |
51f89798 | 84 | level = mali_freq_num-1; |
902adbb7 | 85 | else if (freq >= mali_plat_data.clk_sample[mali_freq_num - 1]) |
51f89798 | 86 | level = 0; |
902adbb7 | 87 | else { |
88 | for (i=0; i<mali_freq_num - 1 ;i++) { | |
89 | if (freq >= mali_plat_data.clk_sample[i] && freq < mali_plat_data.clk_sample[i + 1]) { | |
90 | level = i; | |
91 | level = mali_freq_num-level - 1; | |
92 | break; | |
93 | } | |
51f89798 JY |
94 | } |
95 | } | |
96 | return level; | |
97 | } | |
98 | ||
99 | unsigned int get_mali_max_level(void) | |
100 | { | |
101 | return mali_plat_data.dvfs_table_size - 1; | |
102 | } | |
103 | ||
104 | int get_gpu_max_clk_level(void) | |
105 | { | |
106 | return mali_plat_data.cfg_clock; | |
107 | } | |
108 | ||
d3697437 | 109 | #if defined(CONFIG_AMLOGIC_GPU_THERMAL) || defined(CONFIG_GPU_THERMAL) |
51f89798 JY |
110 | static void set_limit_mali_freq(u32 idx) |
111 | { | |
112 | if (mali_plat_data.limit_on == 0) | |
113 | return; | |
114 | if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk) | |
115 | return; | |
116 | if (idx > mali_plat_data.maxclk_sysfs) { | |
117 | printk("idx > max freq\n"); | |
118 | return; | |
119 | } | |
120 | mali_plat_data.scale_info.maxclk= idx; | |
121 | revise_mali_rt(); | |
122 | } | |
123 | ||
124 | static u32 get_limit_mali_freq(void) | |
125 | { | |
126 | return mali_plat_data.scale_info.maxclk; | |
127 | } | |
128 | ||
e145e8e1 | 129 | #ifdef CONFIG_DEVFREQ_THERMAL |
51f89798 JY |
130 | static u32 get_mali_utilization(void) |
131 | { | |
132 | #ifndef MESON_DRV_BRING | |
133 | return 55; | |
134 | #else | |
135 | return (_mali_ukk_utilization_pp() * 100) / 256; | |
136 | #endif | |
137 | } | |
138 | #endif | |
e145e8e1 | 139 | #endif |
51f89798 | 140 | |
d3697437 | 141 | #if defined(CONFIG_AMLOGIC_GPU_THERMAL) || defined(CONFIG_GPU_THERMAL) |
51f89798 JY |
142 | static u32 set_limit_pp_num(u32 num) |
143 | { | |
144 | u32 ret = -1; | |
145 | if (mali_plat_data.limit_on == 0) | |
146 | goto quit; | |
147 | if (num > mali_plat_data.cfg_pp || | |
148 | num < mali_plat_data.scale_info.minpp) | |
149 | goto quit; | |
150 | ||
151 | if (num > mali_plat_data.maxpp_sysfs) { | |
152 | printk("pp > sysfs set pp\n"); | |
153 | goto quit; | |
154 | } | |
155 | ||
156 | mali_plat_data.scale_info.maxpp = num; | |
157 | revise_mali_rt(); | |
158 | ret = 0; | |
159 | quit: | |
160 | return ret; | |
161 | } | |
e145e8e1 | 162 | #ifdef CONFIG_DEVFREQ_THERMAL |
51f89798 JY |
163 | static u32 mali_get_online_pp(void) |
164 | { | |
165 | unsigned int val; | |
166 | mali_plat_info_t* pmali_plat = get_mali_plat_data(); | |
167 | ||
168 | val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff; | |
169 | if (val == 0x07) /* No pp is working */ | |
170 | return 0; | |
171 | ||
172 | #ifndef MESON_DRV_BRING | |
173 | return 2; | |
174 | #else | |
175 | return mali_executor_get_num_cores_enabled(); | |
176 | #endif | |
177 | } | |
178 | #endif | |
e145e8e1 | 179 | #endif |
51f89798 JY |
180 | |
181 | int mali_meson_init_start(struct platform_device* ptr_plt_dev) | |
182 | { | |
183 | //dev_set_drvdata(&ptr_plt_dev->dev, &mali_plat_data); | |
184 | mali_dt_info(ptr_plt_dev, &mali_plat_data); | |
185 | mali_clock_init_clk_tree(ptr_plt_dev); | |
186 | return 0; | |
187 | } | |
188 | ||
189 | int mali_meson_init_finish(struct platform_device* ptr_plt_dev) | |
190 | { | |
191 | if (mali_core_scaling_init(&mali_plat_data) < 0) | |
192 | return -1; | |
193 | return 0; | |
194 | } | |
195 | ||
196 | int mali_meson_uninit(struct platform_device* ptr_plt_dev) | |
197 | { | |
198 | mali_core_scaling_term(); | |
199 | return 0; | |
200 | } | |
201 | ||
202 | void mali_post_init(void) | |
203 | { | |
d3697437 | 204 | #if defined(CONFIG_AMLOGIC_GPU_THERMAL) || defined(CONFIG_GPU_THERMAL) |
51f89798 JY |
205 | int err; |
206 | struct gpufreq_cooling_device *gcdev = NULL; | |
207 | struct gpucore_cooling_device *gccdev = NULL; | |
208 | ||
209 | gcdev = gpufreq_cooling_alloc(); | |
210 | register_gpu_freq_info(get_current_frequency); | |
211 | if (IS_ERR(gcdev)) | |
212 | printk("malloc gpu cooling buffer error!!\n"); | |
213 | else if (!gcdev) | |
214 | printk("system does not enable thermal driver\n"); | |
215 | else { | |
216 | gcdev->get_gpu_freq_level = get_mali_freq_level; | |
217 | gcdev->get_gpu_max_level = get_mali_max_level; | |
218 | gcdev->set_gpu_freq_idx = set_limit_mali_freq; | |
219 | gcdev->get_gpu_current_max_level = get_limit_mali_freq; | |
e145e8e1 | 220 | #ifdef CONFIG_DEVFREQ_THERMAL |
51f89798 JY |
221 | gcdev->get_gpu_freq = get_mali_freq; |
222 | gcdev->get_gpu_loading = get_mali_utilization; | |
223 | gcdev->get_online_pp = mali_get_online_pp; | |
e145e8e1 | 224 | #endif |
51f89798 | 225 | err = gpufreq_cooling_register(gcdev); |
e145e8e1 | 226 | #ifdef CONFIG_DEVFREQ_THERMAL |
51f89798 | 227 | aml_thermal_min_update(gcdev->cool_dev); |
e145e8e1 | 228 | #endif |
51f89798 JY |
229 | if (err < 0) |
230 | printk("register GPU cooling error\n"); | |
231 | printk("gpu cooling register okay with err=%d\n",err); | |
232 | } | |
233 | ||
234 | gccdev = gpucore_cooling_alloc(); | |
235 | if (IS_ERR(gccdev)) | |
236 | printk("malloc gpu core cooling buffer error!!\n"); | |
237 | else if (!gccdev) | |
238 | printk("system does not enable thermal driver\n"); | |
239 | else { | |
240 | gccdev->max_gpu_core_num=mali_plat_data.cfg_pp; | |
241 | gccdev->set_max_pp_num=set_limit_pp_num; | |
242 | err = (int)gpucore_cooling_register(gccdev); | |
e145e8e1 | 243 | #ifdef CONFIG_DEVFREQ_THERMAL |
51f89798 | 244 | aml_thermal_min_update(gccdev->cool_dev); |
e145e8e1 | 245 | #endif |
51f89798 JY |
246 | if (err < 0) |
247 | printk("register GPU cooling error\n"); | |
248 | printk("gpu core cooling register okay with err=%d\n",err); | |
249 | } | |
250 | #endif | |
251 | } |