projects / GitHub / LineageOS / G12 / android_hardware_amlogic_kernel-modules_dhd-driver.git / blame
projects / GitHub / LineageOS / G12 / android_hardware_amlogic_kernel-modules_dhd-driver.git / blame
| Commit | Line | Data |
|---|---|---|
| 84813812 LJ |
1 | /* |
| 2 | * Broadcom SiliconBackplane ARM definitions | |
| 3 | * | |
| 4 | * Copyright (C) 1999-2019, Broadcom. | |
| 5 | * | |
| 6 | * Unless you and Broadcom execute a separate written software license | |
| 7 | * agreement governing use of this software, this software is licensed to you | |
| 8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | |
| 9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | |
| 10 | * following added to such license: | |
| 11 | * | |
| 12 | * As a special exception, the copyright holders of this software give you | |
| 13 | * permission to link this software with independent modules, and to copy and | |
| 14 | * distribute the resulting executable under terms of your choice, provided that | |
| 15 | * you also meet, for each linked independent module, the terms and conditions of | |
| 16 | * the license of that module. An independent module is a module which is not | |
| 17 | * derived from this software. The special exception does not apply to any | |
| 18 | * modifications of the software. | |
| 19 | * | |
| 20 | * Notwithstanding the above, under no circumstances may you combine this | |
| 21 | * software in any way with any other Broadcom software provided under a license | |
| 22 | * other than the GPL, without Broadcom's express prior written consent. | |
| 23 | * | |
| 24 | * | |
| 25 | * <<Broadcom-WL-IPTag/Open:>> | |
| 26 | * | |
| 27 | * $Id: sbhndarm.h 799498 2019-01-16 06:02:27Z $ | |
| 28 | */ | |
| 29 | ||
| 30 | #ifndef _sbhndarm_h_ | |
| 31 | #define _sbhndarm_h_ | |
| 32 | ||
| 33 | #ifndef _LANGUAGE_ASSEMBLY | |
| 34 | ||
| 35 | /* cpp contortions to concatenate w/arg prescan */ | |
| 36 | #ifndef PAD | |
| 37 | #define _PADLINE(line) pad ## line | |
| 38 | #define _XSTR(line) _PADLINE(line) | |
| 39 | #define PAD _XSTR(__LINE__) | |
| 40 | #endif /* PAD */ | |
| 41 | ||
| 42 | /* cortex-m3 */ | |
| 43 | typedef volatile struct { | |
| 44 | uint32 corecontrol; /* 0x0 */ | |
| 45 | uint32 corestatus; /* 0x4 */ | |
| 46 | uint32 PAD[1]; | |
| 47 | uint32 biststatus; /* 0xc */ | |
| 48 | uint32 nmiisrst; /* 0x10 */ | |
| 49 | uint32 nmimask; /* 0x14 */ | |
| 50 | uint32 isrmask; /* 0x18 */ | |
| 51 | uint32 PAD[1]; | |
| 52 | uint32 resetlog; /* 0x20 */ | |
| 53 | uint32 gpioselect; /* 0x24 */ | |
| 54 | uint32 gpioenable; /* 0x28 */ | |
| 55 | uint32 PAD[1]; | |
| 56 | uint32 bpaddrlo; /* 0x30 */ | |
| 57 | uint32 bpaddrhi; /* 0x34 */ | |
| 58 | uint32 bpdata; /* 0x38 */ | |
| 59 | uint32 bpindaccess; /* 0x3c */ | |
| 60 | uint32 ovlidx; /* 0x40 */ | |
| 61 | uint32 ovlmatch; /* 0x44 */ | |
| 62 | uint32 ovladdr; /* 0x48 */ | |
| 63 | uint32 PAD[13]; | |
| 64 | uint32 bwalloc; /* 0x80 */ | |
| 65 | uint32 PAD[3]; | |
| 66 | uint32 cyclecnt; /* 0x90 */ | |
| 67 | uint32 inttimer; /* 0x94 */ | |
| 68 | uint32 intmask; /* 0x98 */ | |
| 69 | uint32 intstatus; /* 0x9c */ | |
| 70 | uint32 PAD[80]; | |
| 71 | uint32 clk_ctl_st; /* 0x1e0 */ | |
| 72 | uint32 PAD[1]; | |
| 73 | uint32 powerctl; /* 0x1e8 */ | |
| 74 | } cm3regs_t; | |
| 75 | #define ARM_CM3_REG(regs, reg) (&((cm3regs_t *)regs)->reg) | |
| 76 | ||
| 77 | /* cortex-R4 */ | |
| 78 | typedef volatile struct { | |
| 79 | uint32 corecontrol; /* 0x0 */ | |
| 80 | uint32 corecapabilities; /* 0x4 */ | |
| 81 | uint32 corestatus; /* 0x8 */ | |
| 82 | uint32 biststatus; /* 0xc */ | |
| 83 | uint32 nmiisrst; /* 0x10 */ | |
| 84 | uint32 nmimask; /* 0x14 */ | |
| 85 | uint32 isrmask; /* 0x18 */ | |
| 86 | uint32 swintreg; /* 0x1C */ | |
| 87 | uint32 intstatus; /* 0x20 */ | |
| 88 | uint32 intmask; /* 0x24 */ | |
| 89 | uint32 cyclecnt; /* 0x28 */ | |
| 90 | uint32 inttimer; /* 0x2c */ | |
| 91 | uint32 gpioselect; /* 0x30 */ | |
| 92 | uint32 gpioenable; /* 0x34 */ | |
| 93 | uint32 PAD[2]; | |
| 94 | uint32 bankidx; /* 0x40 */ | |
| 95 | uint32 bankinfo; /* 0x44 */ | |
| 96 | uint32 bankstbyctl; /* 0x48 */ | |
| 97 | uint32 bankpda; /* 0x4c */ | |
| 98 | uint32 PAD[6]; | |
| 99 | uint32 tcampatchctrl; /* 0x68 */ | |
| 100 | uint32 tcampatchtblbaseaddr; /* 0x6c */ | |
| 101 | uint32 tcamcmdreg; /* 0x70 */ | |
| 102 | uint32 tcamdatareg; /* 0x74 */ | |
| 103 | uint32 tcambankxmaskreg; /* 0x78 */ | |
| 104 | uint32 PAD[89]; | |
| 105 | uint32 clk_ctl_st; /* 0x1e0 */ | |
| 106 | uint32 PAD[1]; | |
| 107 | uint32 powerctl; /* 0x1e8 */ | |
| 108 | } cr4regs_t; | |
| 109 | #define ARM_CR4_REG(regs, reg) (&((cr4regs_t *)regs)->reg) | |
| 110 | ||
| 111 | /* cortex-A7 */ | |
| 112 | typedef volatile struct { | |
| 113 | uint32 corecontrol; /* 0x0 */ | |
| 114 | uint32 corecapabilities; /* 0x4 */ | |
| 115 | uint32 corestatus; /* 0x8 */ | |
| 116 | uint32 tracecontrol; /* 0xc */ | |
| 117 | uint32 PAD[8]; | |
| 118 | uint32 gpioselect; /* 0x30 */ | |
| 119 | uint32 gpioenable; /* 0x34 */ | |
| 120 | uint32 PAD[106]; | |
| 121 | uint32 clk_ctl_st; /* 0x1e0 */ | |
| 122 | uint32 PAD[1]; | |
| 123 | uint32 powerctl; /* 0x1e8 */ | |
| 124 | } ca7regs_t; | |
| 125 | #define ARM_CA7_REG(regs, reg) (&((ca7regs_t *)regs)->reg) | |
| 126 | ||
| 127 | #if defined(__ARM_ARCH_7M__) | |
| 128 | #define ARMREG(regs, reg) ARM_CM3_REG(regs, reg) | |
| 129 | #endif /* __ARM_ARCH_7M__ */ | |
| 130 | ||
| 131 | #if defined(__ARM_ARCH_7R__) | |
| 132 | #define ARMREG(regs, reg) ARM_CR4_REG(regs, reg) | |
| 133 | #endif /* __ARM_ARCH_7R__ */ | |
| 134 | ||
| 135 | #if defined(__ARM_ARCH_7A__) | |
| 136 | #define ARMREG(regs, reg) ARM_CA7_REG(regs, reg) | |
| 137 | #endif /* __ARM_ARCH_7A__ */ | |
| 138 | ||
| 139 | #endif /* _LANGUAGE_ASSEMBLY */ | |
| 140 | ||
| 141 | #endif /* _sbhndarm_h_ */ |