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[GitHub/LineageOS/G12/android_hardware_amlogic_kernel-modules_dhd-driver.git] / bcmdhd.1.579.77.41.1.cn / dhd_pcie.h
CommitLineData
010c3a89
RC		 1/*
2 * Linux DHD Bus Module for PCIE
3 *
4 * Copyright (C) 1999-2017, Broadcom Corporation
5 *
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
11 *
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
19 *
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
23 *
24 *
25 * <<Broadcom-WL-IPTag/Open:>>
26 *
27 * $Id: dhd_pcie.h 707536 2017-06-28 04:23:48Z $
28 */
29
30
31#ifndef dhd_pcie_h
32#define dhd_pcie_h
33
34#include <bcmpcie.h>
35#include <hnd_cons.h>
36#ifdef SUPPORT_LINKDOWN_RECOVERY
37#ifdef CONFIG_ARCH_MSM
38#ifdef CONFIG_PCI_MSM
39#include <linux/msm_pcie.h>
40#else
41#include <mach/msm_pcie.h>
42#endif /* CONFIG_PCI_MSM */
43#endif /* CONFIG_ARCH_MSM */
44#ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
45#if defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895)
46#include <linux/exynos-pci-noti.h>
47extern int exynos_pcie_register_event(struct exynos_pcie_register_event *reg);
48extern int exynos_pcie_deregister_event(struct exynos_pcie_register_event *reg);
49#endif /* CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895 */
50#endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
51#endif /* SUPPORT_LINKDOWN_RECOVERY */
52
53#ifdef DHD_PCIE_RUNTIMEPM
54#include <linux/mutex.h>
55#include <linux/wait.h>
56
57#define DEFAULT_DHD_RUNTIME_MS 100
58#ifndef CUSTOM_DHD_RUNTIME_MS
59#define CUSTOM_DHD_RUNTIME_MS DEFAULT_DHD_RUNTIME_MS
60#endif /* CUSTOM_DHD_RUNTIME_MS */
61
62
63#ifndef MAX_IDLE_COUNT
64#define MAX_IDLE_COUNT 16
65#endif /* MAX_IDLE_COUNT */
66
67#ifndef MAX_RESUME_WAIT
68#define MAX_RESUME_WAIT 100
69#endif /* MAX_RESUME_WAIT */
70#endif /* DHD_PCIE_RUNTIMEPM */
71
72/* defines */
73
74#define PCMSGBUF_HDRLEN 0
75#define DONGLE_REG_MAP_SIZE (32 * 1024)
76#define DONGLE_TCM_MAP_SIZE (4096 * 1024)
77#define DONGLE_MIN_MEMSIZE (128 *1024)
78#ifdef DHD_DEBUG
79#define DHD_PCIE_SUCCESS 0
80#define DHD_PCIE_FAILURE 1
81#endif /* DHD_DEBUG */
82#define REMAP_ENAB(bus) ((bus)->remap)
83#define REMAP_ISADDR(bus, a) (((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
84
85#ifdef SUPPORT_LINKDOWN_RECOVERY
86#ifdef CONFIG_ARCH_MSM
87#define struct_pcie_notify struct msm_pcie_notify
88#define struct_pcie_register_event struct msm_pcie_register_event
89#endif /* CONFIG_ARCH_MSM */
90#ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
91#if defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895)
92#define struct_pcie_notify struct exynos_pcie_notify
93#define struct_pcie_register_event struct exynos_pcie_register_event
94#endif /* CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895 */
95#endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
96#endif /* SUPPORT_LINKDOWN_RECOVERY */
97
98#define MAX_DHD_TX_FLOWS 320
99
100/* user defined data structures */
101/* Device console log buffer state */
102#define CONSOLE_LINE_MAX 192
103#define CONSOLE_BUFFER_MAX (8 * 1024)
104
105#ifdef IDLE_TX_FLOW_MGMT
106#define IDLE_FLOW_LIST_TIMEOUT 5000
107#define IDLE_FLOW_RING_TIMEOUT 5000
108#endif /* IDLE_TX_FLOW_MGMT */
109
110#ifdef DEVICE_TX_STUCK_DETECT
111#define DEVICE_TX_STUCK_CKECK_TIMEOUT 1000 /* 1 sec */
112#define DEVICE_TX_STUCK_TIMEOUT 10000 /* 10 secs */
113#define DEVICE_TX_STUCK_WARN_DURATION (DEVICE_TX_STUCK_TIMEOUT / DEVICE_TX_STUCK_CKECK_TIMEOUT)
114#define DEVICE_TX_STUCK_DURATION (DEVICE_TX_STUCK_WARN_DURATION * 2)
115#endif /* DEVICE_TX_STUCK_DETECT */
116
117/* implicit DMA for h2d wr and d2h rd indice from Host memory to TCM */
118#define IDMA_ENAB(dhd) ((dhd)->idma_enable)
119#define IDMA_ACTIVE(dhd) (((dhd)->idma_enable) && ((dhd)->idma_inited))
120
121#define IDMA_DS_ENAB(dhd) ((dhd)->idma_retention_ds)
122#define IDMA_DS_ACTIVE(dhd) ((dhd)->bus->dongle_in_ds)
123
124/* IFRM (Implicit Flow Ring Manager enable and inited */
125#define IFRM_ENAB(dhd) ((dhd)->ifrm_enable)
126#define IFRM_ACTIVE(dhd) (((dhd)->ifrm_enable) && ((dhd)->ifrm_inited))
127
128/* PCIE CTO Prevention and Recovery */
129#define PCIECTO_ENAB(dhd) ((dhd)->cto_enable)
130
131/* Implicit DMA index usage :
132 * Index 0 for h2d write index transfer
133 * Index 1 for d2h read index transfer
134 */
135#define IDMA_IDX0 0
136#define IDMA_IDX1 1
137#define IDMA_IDX2 2
138#define IDMA_IDX3 3
139
140#define DHDPCIE_CONFIG_HDR_SIZE 16
141#define DHDPCIE_CONFIG_CHECK_DELAY_MS 10 /* 10ms */
142#define DHDPCIE_CONFIG_CHECK_RETRY_COUNT 20
143#define DHDPCIE_DONGLE_PWR_TOGGLE_DELAY 1000 /* 1ms in units of us */
144#define DHDPCIE_PM_D3_DELAY 200000 /* 200ms in units of us */
145#define DHDPCIE_PM_D2_DELAY 200 /* 200us */
146
147typedef struct dhd_console {
148 uint count; /* Poll interval msec counter */
149 uint log_addr; /* Log struct address (fixed) */
150 hnd_log_t log; /* Log struct (host copy) */
151 uint bufsize; /* Size of log buffer */
152 uint8 *buf; /* Log buffer (host copy) */
153 uint last; /* Last buffer read index */
154} dhd_console_t;
155
156typedef struct ring_sh_info {
157 uint32 ring_mem_addr;
158 uint32 ring_state_w;
159 uint32 ring_state_r;
160} ring_sh_info_t;
161
162
163#define DEVICE_WAKE_NONE 0
164#define DEVICE_WAKE_OOB 1
165#define DEVICE_WAKE_INB 2
166
167#define INBAND_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_INB)
168#define OOB_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_OOB)
169#define NO_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_NONE)
170
171struct dhd_bus;
172
173struct dhd_pcie_rev {
174 uint8 fw_rev;
175 void (*handle_mb_data)(struct dhd_bus *);
176};
177
178typedef struct dhdpcie_config_save
179{
180 uint32 header[DHDPCIE_CONFIG_HDR_SIZE];
181 /* pmcsr save */
182 uint32 pmcsr;
183 /* express save */
184 uint32 exp_dev_ctrl_stat;
185 uint32 exp_link_ctrl_stat;
186 uint32 exp_dev_ctrl_stat2;
187 uint32 exp_link_ctrl_stat2;
188 /* msi save */
189 uint32 msi_cap;
190 uint32 msi_addr0;
191 uint32 msi_addr1;
192 uint32 msi_data;
193 /* l1pm save */
194 uint32 l1pm0;
195 uint32 l1pm1;
196 /* ltr save */
197 uint32 ltr;
198 /* aer save */
199 uint32 aer_caps_ctrl; /* 0x18 */
200 uint32 aer_severity; /* 0x0C */
201 uint32 aer_umask; /* 0x08 */
202 uint32 aer_cmask; /* 0x14 */
203 uint32 aer_root_cmd; /* 0x2c */
204 /* BAR0 and BAR1 windows */
205 uint32 bar0_win;
206 uint32 bar1_win;
207} dhdpcie_config_save_t;
208
209typedef struct dhd_bus {
210 dhd_pub_t *dhd;
211 struct pci_dev *rc_dev; /* pci RC device handle */
212 struct pci_dev *dev; /* pci device handle */
213#ifdef DHD_EFI
214 void *pcie_dev;
215#endif
216
217 dll_t flowring_active_list; /* constructed list of tx flowring queues */
218#ifdef IDLE_TX_FLOW_MGMT
219 uint64 active_list_last_process_ts;
220 /* stores the timestamp of active list processing */
221#endif /* IDLE_TX_FLOW_MGMT */
222
223#ifdef DEVICE_TX_STUCK_DETECT
224 /* Flag to enable/disable device tx stuck monitor by DHD IOVAR dev_tx_stuck_monitor */
225 uint32 dev_tx_stuck_monitor;
226 /* Stores the timestamp (msec) of the last device Tx stuck check */
227 uint32 device_tx_stuck_check;
228#endif /* DEVICE_TX_STUCK_DETECT */
229
230 si_t *sih; /* Handle for SI calls */
231 char *vars; /* Variables (from CIS and/or other) */
232 uint varsz; /* Size of variables buffer */
233 uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
234 sbpcieregs_t *reg; /* Registers for PCIE core */
235
236 uint armrev; /* CPU core revision */
237 uint ramrev; /* SOCRAM core revision */
238 uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
239 uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
240 bool ramsize_adjusted; /* flag to note adjustment, so that
241 * adjustment routine and file io
242 * are avoided on D3 cold -> D0
243 */
244 uint32 srmemsize; /* Size of SRMEM */
245
246 uint32 bus; /* gSPI or SDIO bus */
247 uint32 intstatus; /* Intstatus bits (events) pending */
248 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
249 bool fcstate; /* State of dongle flow-control */
250
251 uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
252 char *fw_path; /* module_param: path to firmware image */
253 char *nv_path; /* module_param: path to nvram vars file */
254#ifdef CACHE_FW_IMAGES
255 int processed_nvram_params_len; /* Modified len of NVRAM info */
256#endif
257
258
259 struct pktq txq; /* Queue length used for flow-control */
260
261 bool intr; /* Use interrupts */
91a2c117 262 bool poll; /* Use polling */
010c3a89
RC		 263 bool ipend; /* Device interrupt is pending */
264 bool intdis; /* Interrupts disabled by isr */
265 uint intrcount; /* Count of device interrupt callbacks */
266 uint lastintrs; /* Count as of last watchdog timer */
267
268 dhd_console_t console; /* Console output polling support */
269 uint console_addr; /* Console address from shared struct */
270
271 bool alp_only; /* Don't use HT clock (ALP only) */
272
273 bool remap; /* Contiguous 1MB RAM: 512K socram + 512K devram
274 * Available with socram rev 16
275 * Remap region not DMA-able
276 */
277 uint32 resetinstr;
278 uint32 dongle_ram_base;
279
280 ulong shared_addr;
281 pciedev_shared_t *pcie_sh;
282 bool bus_flowctrl;
283 uint32 dma_rxoffset;
284 volatile char *regs; /* pci device memory va */
285 volatile char *tcm; /* pci device memory va */
286 osl_t *osh;
287 uint32 nvram_csm; /* Nvram checksum */
288 uint16 pollrate;
289 uint16 polltick;
290
291 volatile uint32 *pcie_mb_intr_addr;
292 volatile uint32 *pcie_mb_intr_2_addr;
293 void *pcie_mb_intr_osh;
294 bool sleep_allowed;
295
296 wake_counts_t wake_counts;
297
298 /* version 3 shared struct related info start */
299 ring_sh_info_t ring_sh[BCMPCIE_COMMON_MSGRINGS + MAX_DHD_TX_FLOWS];
300
301 uint8 h2d_ring_count;
302 uint8 d2h_ring_count;
303 uint32 ringmem_ptr;
304 uint32 ring_state_ptr;
305
306 uint32 d2h_dma_scratch_buffer_mem_addr;
307
308 uint32 h2d_mb_data_ptr_addr;
309 uint32 d2h_mb_data_ptr_addr;
310 /* version 3 shared struct related info end */
311
312 uint32 def_intmask;
313 bool ltrsleep_on_unload;
314 uint wait_for_d3_ack;
315 uint16 max_tx_flowrings;
316 uint16 max_submission_rings;
317 uint16 max_completion_rings;
318 uint16 max_cmn_rings;
319 uint32 rw_index_sz;
320 bool db1_for_mb;
321
322 dhd_timeout_t doorbell_timer;
323 bool device_wake_state;
324#ifdef PCIE_OOB
325 bool oob_enabled;
326#endif /* PCIE_OOB */
327 bool irq_registered;
328#ifdef SUPPORT_LINKDOWN_RECOVERY
329#if defined(CONFIG_ARCH_MSM) || (defined(EXYNOS_PCIE_LINKDOWN_RECOVERY) && \
330 defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895))
331#ifdef CONFIG_ARCH_MSM
332 uint8 no_cfg_restore;
333#endif /* CONFIG_ARCH_MSM */
334 struct_pcie_register_event pcie_event;
335#endif /* CONFIG_ARCH_MSM || (EXYNOS_PCIE_LINKDOWN_RECOVERY &&
336 * (CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895))
337 */
338 bool read_shm_fail;
339#endif /* SUPPORT_LINKDOWN_RECOVERY */
340 int32 idletime; /* Control for activity timeout */
341#ifdef DHD_PCIE_RUNTIMEPM
342 int32 idlecount; /* Activity timeout counter */
343 int32 bus_wake; /* For wake up the bus */
344 bool runtime_resume_done; /* For check runtime suspend end */
345 struct mutex pm_lock; /* Synchronize for system PM & runtime PM */
346 wait_queue_head_t rpm_queue; /* wait-queue for bus wake up */
347#endif /* DHD_PCIE_RUNTIMEPM */
348 uint32 d3_inform_cnt;
349 uint32 d0_inform_cnt;
350 uint32 d0_inform_in_use_cnt;
351 uint8 force_suspend;
352 uint8 is_linkdown;
353#ifdef IDLE_TX_FLOW_MGMT
354 bool enable_idle_flowring_mgmt;
355#endif /* IDLE_TX_FLOW_MGMT */
356 struct dhd_pcie_rev api;
357 bool use_mailbox;
358 bool d3_suspend_pending;
359 bool use_d0_inform;
360 uint32 hostready_count; /* Number of hostready issued */
361#if defined(PCIE_OOB) || defined(BCMPCIE_OOB_HOST_WAKE)
362 bool oob_presuspend;
363#endif /* PCIE_OOB || BCMPCIE_OOB_HOST_WAKE */
364 bool dongle_in_ds;
365 uint8 dw_option;
366#ifdef PCIE_INB_DW
367 bool inb_enabled;
368 uint32 ds_exit_timeout;
369 uint32 host_sleep_exit_timeout;
370 uint wait_for_ds_exit;
371 uint32 inband_dw_assert_cnt; /* # of inband device_wake assert */
372 uint32 inband_dw_deassert_cnt; /* # of inband device_wake deassert */
373 uint32 inband_ds_exit_host_cnt; /* # of DS-EXIT , host initiated */
374 uint32 inband_ds_exit_device_cnt; /* # of DS-EXIT , device initiated */
375 uint32 inband_ds_exit_to_cnt; /* # of DS-EXIT timeout */
376 uint32 inband_host_sleep_exit_to_cnt; /* # of Host_Sleep exit timeout */
377 void *inb_lock; /* Lock to serialize in band device wake activity */
378 /* # of contexts in the host which currently want a FW transaction */
379 uint32 host_active_cnt;
380#endif /* PCIE_INB_DW */
381 dhdpcie_config_save_t saved_config;
382 ulong resume_intr_enable_count;
383 ulong dpc_intr_enable_count;
384 ulong isr_intr_disable_count;
385 ulong suspend_intr_disable_count;
386 ulong dpc_return_busdown_count;
387 bool idma_enabled;
388 bool ifrm_enabled;
389#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
390 bool ds_enabled;
391#endif
392#ifdef DHD_PCIE_RUNTIMEPM
393 bool chk_pm; /* To avoid counting of wake up from Runtime PM */
394#endif /* DHD_PCIE_RUNTIMEPM */
395} dhd_bus_t;
396
397/* function declarations */
398
399extern uint32* dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size);
400extern int dhdpcie_bus_register(void);
401extern void dhdpcie_bus_unregister(void);
402extern bool dhdpcie_chipmatch(uint16 vendor, uint16 device);
403
404extern struct dhd_bus* dhdpcie_bus_attach(osl_t *osh,
405 volatile char *regs, volatile char *tcm, void *pci_dev);
406extern uint32 dhdpcie_bus_cfg_read_dword(struct dhd_bus *bus, uint32 addr, uint32 size);
407extern void dhdpcie_bus_cfg_write_dword(struct dhd_bus *bus, uint32 addr, uint32 size, uint32 data);
408extern void dhdpcie_bus_intr_enable(struct dhd_bus *bus);
409extern void dhdpcie_bus_intr_disable(struct dhd_bus *bus);
410extern int dhpcie_bus_mask_interrupt(dhd_bus_t *bus);
411extern void dhdpcie_bus_release(struct dhd_bus *bus);
412extern int32 dhdpcie_bus_isr(struct dhd_bus *bus);
413extern void dhdpcie_free_irq(dhd_bus_t *bus);
414extern void dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value);
415extern void dhdpcie_bus_ringbell_2_fast(struct dhd_bus *bus, uint32 value, bool devwake);
416extern int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state);
417extern int dhdpcie_pci_suspend_resume(struct dhd_bus *bus, bool state);
418extern uint32 dhdpcie_force_alp(struct dhd_bus *bus, bool enable);
419extern uint32 dhdpcie_set_l1_entry_time(struct dhd_bus *bus, int force_l1_entry_time);
420extern bool dhdpcie_tcm_valid(dhd_bus_t *bus);
421extern void dhdpcie_pme_active(osl_t *osh, bool enable);
422extern bool dhdpcie_pme_cap(osl_t *osh);
423extern uint32 dhdpcie_lcreg(osl_t *osh, uint32 mask, uint32 val);
424extern void dhdpcie_set_pmu_min_res_mask(struct dhd_bus *bus, uint min_res_mask);
425extern uint8 dhdpcie_clkreq(osl_t *osh, uint32 mask, uint32 val);
426extern int dhdpcie_disable_irq(dhd_bus_t *bus);
427extern int dhdpcie_disable_irq_nosync(dhd_bus_t *bus);
428extern int dhdpcie_enable_irq(dhd_bus_t *bus);
429extern uint32 dhdpcie_rc_config_read(dhd_bus_t *bus, uint offset);
430extern uint32 dhdpcie_rc_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext,
431 bool is_write, uint32 writeval);
432extern uint32 dhd_debug_get_rc_linkcap(dhd_bus_t *bus);
433extern int dhdpcie_start_host_pcieclock(dhd_bus_t *bus);
434extern int dhdpcie_stop_host_pcieclock(dhd_bus_t *bus);
435extern int dhdpcie_disable_device(dhd_bus_t *bus);
436extern int dhdpcie_alloc_resource(dhd_bus_t *bus);
437extern void dhdpcie_free_resource(dhd_bus_t *bus);
438extern int dhdpcie_bus_request_irq(struct dhd_bus *bus);
439extern int dhdpcie_enable_device(dhd_bus_t *bus);
440#ifdef BCMPCIE_OOB_HOST_WAKE
441extern int dhdpcie_oob_intr_register(dhd_bus_t *bus);
442extern void dhdpcie_oob_intr_unregister(dhd_bus_t *bus);
443extern void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable);
444#endif /* BCMPCIE_OOB_HOST_WAKE */
445#ifdef PCIE_OOB
446extern void dhd_oob_set_bt_reg_on(struct dhd_bus *bus, bool val);
447extern int dhd_oob_get_bt_reg_on(struct dhd_bus *bus);
448extern void dhdpcie_oob_init(dhd_bus_t *bus);
449extern void dhd_bus_doorbell_timeout_reset(struct dhd_bus *bus);
450extern int dhd_os_oob_set_device_wake(struct dhd_bus *bus, bool val);
451extern void dhd_os_ib_set_device_wake(struct dhd_bus *bus, bool val);
452#endif /* PCIE_OOB */
453
454#if defined(CONFIG_ARCH_EXYNOS)
455#define SAMSUNG_PCIE_VENDOR_ID 0x144d
456#if defined(CONFIG_MACH_UNIVERSAL5433)
457#define SAMSUNG_PCIE_DEVICE_ID 0xa5e3
458#define SAMSUNG_PCIE_CH_NUM
459#elif defined(CONFIG_MACH_UNIVERSAL7420)
460#define SAMSUNG_PCIE_DEVICE_ID 0xa575
461#define SAMSUNG_PCIE_CH_NUM 1
462#elif defined(CONFIG_SOC_EXYNOS8890)
463#define SAMSUNG_PCIE_DEVICE_ID 0xa544
464#define SAMSUNG_PCIE_CH_NUM 0
465#elif defined(CONFIG_SOC_EXYNOS7420)
466#define SAMSUNG_PCIE_DEVICE_ID 0xa575
467#define SAMSUNG_PCIE_CH_NUM 1
468#elif defined(CONFIG_SOC_EXYNOS8895)
469#define SAMSUNG_PCIE_DEVICE_ID 0xecec
470#define SAMSUNG_PCIE_CH_NUM 0
471#else
472#error "Not supported platform"
473#endif /* CONFIG_SOC_EXYNOSXXXX & CONFIG_MACH_UNIVERSALXXXX */
474#endif /* CONFIG_ARCH_EXYNOS */
475
476#if defined(CONFIG_ARCH_MSM)
477#define MSM_PCIE_VENDOR_ID 0x17cb
478#if defined(CONFIG_ARCH_APQ8084)
479#define MSM_PCIE_DEVICE_ID 0x0101
480#elif defined(CONFIG_ARCH_MSM8994)
481#define MSM_PCIE_DEVICE_ID 0x0300
482#elif defined(CONFIG_ARCH_MSM8996)
483#define MSM_PCIE_DEVICE_ID 0x0104
484#elif defined(CONFIG_ARCH_MSM8998)
485#define MSM_PCIE_DEVICE_ID 0x0105
486#else
487#error "Not supported platform"
488#endif
489#endif /* CONFIG_ARCH_MSM */
490
491#if defined(CONFIG_X86)
492#define X86_PCIE_VENDOR_ID 0x8086
493#define X86_PCIE_DEVICE_ID 0x9c1a
494#endif /* CONFIG_X86 */
495
496#if defined(CONFIG_ARCH_TEGRA)
497#define TEGRA_PCIE_VENDOR_ID 0x14e4
498#define TEGRA_PCIE_DEVICE_ID 0x4347
499#endif /* CONFIG_ARCH_TEGRA */
500
501#if defined(CONFIG_ARCH_EXYNOS)
502#define PCIE_RC_VENDOR_ID SAMSUNG_PCIE_VENDOR_ID
503#define PCIE_RC_DEVICE_ID SAMSUNG_PCIE_DEVICE_ID
504#elif defined(CONFIG_ARCH_MSM)
505#define PCIE_RC_VENDOR_ID MSM_PCIE_VENDOR_ID
506#define PCIE_RC_DEVICE_ID MSM_PCIE_DEVICE_ID
507#elif defined(CONFIG_X86)
508#define PCIE_RC_VENDOR_ID X86_PCIE_VENDOR_ID
509#define PCIE_RC_DEVICE_ID X86_PCIE_DEVICE_ID
510#elif defined(CONFIG_ARCH_TEGRA)
511#define PCIE_RC_VENDOR_ID TEGRA_PCIE_VENDOR_ID
512#define PCIE_RC_DEVICE_ID TEGRA_PCIE_DEVICE_ID
010c3a89
RC		 513#endif /* CONFIG_ARCH_EXYNOS */
514
515#ifdef USE_EXYNOS_PCIE_RC_PMPATCH
516#ifdef CONFIG_MACH_UNIVERSAL5433
517extern int exynos_pcie_pm_suspend(void);
518extern int exynos_pcie_pm_resume(void);
519#else
520extern int exynos_pcie_pm_suspend(int ch_num);
521extern int exynos_pcie_pm_resume(int ch_num);
522#endif /* CONFIG_MACH_UNIVERSAL5433 */
523#endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
524
525#ifdef CONFIG_ARCH_TEGRA
526extern int tegra_pcie_pm_suspend(void);
527extern int tegra_pcie_pm_resume(void);
528#endif /* CONFIG_ARCH_TEGRA */
529
530extern int dhd_buzzz_dump_dngl(dhd_bus_t *bus);
531#ifdef IDLE_TX_FLOW_MGMT
532extern int dhd_bus_flow_ring_resume_request(struct dhd_bus *bus, void *arg);
533extern void dhd_bus_flow_ring_resume_response(struct dhd_bus *bus, uint16 flowid, int32 status);
534extern int dhd_bus_flow_ring_suspend_request(struct dhd_bus *bus, void *arg);
535extern void dhd_bus_flow_ring_suspend_response(struct dhd_bus *bus, uint16 flowid, uint32 status);
536extern void dhd_flow_ring_move_to_active_list_head(struct dhd_bus *bus,
537 flow_ring_node_t *flow_ring_node);
538extern void dhd_flow_ring_add_to_active_list(struct dhd_bus *bus,
539 flow_ring_node_t *flow_ring_node);
540extern void dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
541 flow_ring_node_t *flow_ring_node);
542extern void __dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
543 flow_ring_node_t *flow_ring_node);
544#endif /* IDLE_TX_FLOW_MGMT */
545
546extern int dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data);
547
548#ifdef DHD_WAKE_STATUS
549int bcmpcie_get_total_wake(struct dhd_bus *bus);
550int bcmpcie_set_get_wake(struct dhd_bus *bus, int flag);
551#endif /* DHD_WAKE_STATUS */
552extern bool dhdpcie_bus_get_pcie_hostready_supported(dhd_bus_t *bus);
553extern void dhd_bus_hostready(struct dhd_bus *bus);
554#ifdef PCIE_OOB
555extern bool dhdpcie_bus_get_pcie_oob_dw_supported(dhd_bus_t *bus);
556#endif /* PCIE_OOB */
557#ifdef PCIE_INB_DW
558extern bool dhdpcie_bus_get_pcie_inband_dw_supported(dhd_bus_t *bus);
559extern void dhdpcie_bus_set_pcie_inband_dw_state(dhd_bus_t *bus,
560 enum dhd_bus_ds_state state);
561extern enum dhd_bus_ds_state dhdpcie_bus_get_pcie_inband_dw_state(dhd_bus_t *bus);
562extern const char * dhd_convert_inb_state_names(enum dhd_bus_ds_state inbstate);
563extern const char * dhd_convert_dsval(uint32 val, bool d2h);
564extern int dhd_bus_inb_set_device_wake(struct dhd_bus *bus, bool val);
565extern void dhd_bus_inb_ack_pending_ds_req(dhd_bus_t *bus);
566#endif /* PCIE_INB_DW */
567extern void dhdpcie_bus_enab_pcie_dw(dhd_bus_t *bus, uint8 dw_option);
568extern bool dhdpcie_irq_enabled(struct dhd_bus *bus);
569extern bool dhdpcie_bus_get_pcie_idma_supported(dhd_bus_t *bus);
570extern bool dhdpcie_bus_get_pcie_ifrm_supported(dhd_bus_t *bus);
571
572static INLINE uint32
573dhd_pcie_config_read(osl_t *osh, uint offset, uint size)
574{
575 OSL_DELAY(100);
576 return OSL_PCI_READ_CONFIG(osh, offset, size);
577}
578
579static INLINE uint32
580dhd_pcie_corereg_read(si_t *sih, uint val)
581{
582 OSL_DELAY(100);
583 si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, val);
584 return si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), 0, 0);
585}
586
587#ifdef DHD_SSSR_DUMP
588extern int dhdpcie_sssr_dump(dhd_pub_t *dhd);
589#endif /* DHD_SSSR_DUMP */
590
591#ifdef DHD_EFI
592extern int dhd_os_wifi_platform_set_power(uint32 value);
593int dhd_control_signal(dhd_bus_t *bus, char *arg, int set);
594extern int dhd_wifi_properties(struct dhd_bus *bus, char *arg);
595extern bool dhdpcie_is_arm_halted(struct dhd_bus *bus);
596extern void dhdpcie_dongle_pwr_toggle(dhd_bus_t *bus);
597extern int dhd_otp_dump(dhd_bus_t *bus, char *arg);
598#else
599static INLINE int dhd_os_wifi_platform_set_power(uint32 value) {return BCME_OK; }
600static INLINE bool dhdpcie_is_arm_halted(struct dhd_bus *bus) {return TRUE;}
601#endif /* DHD_EFI */
602int dhdpcie_config_check(dhd_bus_t *bus);
603int dhdpcie_config_restore(dhd_bus_t *bus, bool restore_pmcsr);
604int dhdpcie_config_save(dhd_bus_t *bus);
605int dhdpcie_set_pwr_state(dhd_bus_t *bus, uint state);
606
607#endif /* dhd_pcie_h */