GitHub/LineageOS/android_kernel_motorola_exynos9610.git
Author Commit
2017-04-19 Alexey Firagoclk: vc5: Add support for IDT VersaClock 5P49V5935
2017-04-19 Alexey Firagoclk: vc5: Add bindings for IDT VersaClock 5P49V5935
2017-04-19 Alexey Firagoclk: vc5: Add structure to describe particular chip...
2017-04-19 Stephen BoydMerge tag 'sunxi-clk-for-4.12' of https://git./linux...
2017-04-17 Stephen BoydMerge branch 'clk-fixes' into clk-next
2017-04-17 Stephen BoydMerge tag 'sunxi-clk-fixes-for-4.11-2-bis' of https...
2017-04-13 Chen-Yu Tsaiclk: sunxi-ng: a33: gate then ungate PLL CPU clk after...
2017-04-13 Chen-Yu Tsaiclk: sunxi-ng: Add clk notifier to gate then ungate...
2017-04-13 Tobias Regneryclk: sunxi-ng: fix build failure in ccu-sun9i-a80 driver
2017-04-13 Tobias Regneryclk: sunxi-ng: fix build error without CONFIG_RESET_CON...
2017-04-12 Kuninori Morimotoclk: cs2000: use existing priv_to_dev() to getting...
2017-04-12 Michael TurquetteMerge tag 'meson-clk-for-4.12' of git://github.com...
2017-04-12 Michael TurquetteMerge tag 'amlogic-clk' of git://git./linux/kernel...
2017-04-12 Peter De Schrijverclk: aggregate return codes of notify chains
2017-04-12 Peter De Schrijverclk: add clk_possible_parents debugfs file
2017-04-12 Robin van der... clk: imx: correct uart4_serial clock name in driver...
2017-04-12 Stephen Boydclk: zte: Mark pll config tables as const
2017-04-12 Shawn Guoclk: zte: add pll_vga clock for zx296718
2017-04-12 Shawn Guoclk: zte: pd_bit is not 0 on zx296718
2017-04-12 Shawn Guoclk: zte: set CLK_SET_RATE_PARENT for a few zx296718...
2017-04-12 Robin van der... clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock
2017-04-12 Michael TurquetteMerge tag 'tegra-for-4.12-clk' of git://git./linux...
2017-04-12 Kuninori Morimotocs-2000-cp: keep Reserved bit on each register
2017-04-12 Rajendra Nayakclk: qcom: msm8996: Fix the vfe1 powerdomain name
2017-04-12 Gabriel Fernandezclk: stm32f4: fix timeout management for pll and ready...
2017-04-12 Ray Juiclk: iproc: Remove redundant check
2017-04-12 Michael TurquetteMerge tag 'v4.12-rockchip-clk1' of git://git./linux...
2017-04-12 Michael TurquetteMerge tag 'clk-renesas-for-v4.12-tag2' of git://git...
2017-04-12 Stephen BoydMerge branch 'clk-fixes' into clk-next
2017-04-12 Gabriel Fernandezclk: stm32f4: fix: exclude values 0 and 1 for PLLQ
2017-04-12 Stephen BoydMerge branch 'for-4.12-ti-clk-cleanups' of https:/...
2017-04-12 Leo Yanclk: hi6220: add debug APB clock
2017-04-07 Martin Blumenstinglclk: meson: mpll: use 64bit math in rate_from_params
2017-04-07 Martin Blumenstinglclk: meson: mpll: fix division by zero in rate_from_params
2017-04-07 Jerome Brunetclk: meson: gxbb: add cts_i958 clock
2017-04-07 Jerome Brunetclk: meson: gxbb: add cts_mclk_i958
2017-04-07 Jerome Brunetclk: meson: gxbb: add cts_amclk
2017-04-07 Jerome Brunetclk: meson: add audio clock divider support
2017-04-07 Jerome Brunetclk: meson: gxbb: protect against holes in the onecell_...
2017-04-07 Jerome BrunetMAINTAINERS: Add maintainers for the meson clock driver
2017-04-06 Priit Laesclk: sunxi-ng: Display index when clock registration...
2017-04-05 Chen-Yu Tsaiclk: sunxi-ng: a33: Add offset and minimum value for...
2017-04-05 Chen-Yu Tsaiclk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type...
2017-04-05 Chen-Yu Tsaiclk: sunxi-ng: mult: Support PLL lock detection
2017-04-04 Kevin HilmanMerge branch 'v4.12/clk-drivers' into v4.12/clk
2017-04-04 Neil Armstrongclk: meson-gxbb: Add GXL/GXM GP0 Variant
2017-04-04 Neil Armstrongclk: meson-gxbb: Add GP0 PLL init parameters
2017-04-04 Neil Armstrongclk: meson: Add support for parameters for specific...
2017-04-04 Neil Armstrongclk: meson-gxbb: Add MALI clocks
2017-04-04 Neil Armstrongdt-bindings: clock: gxbb-clkc: Add GXL compatible variant
2017-04-04 Neil Armstrongclk: meson-gxbb: Expose GP0 dt-bindings clock id
2017-04-04 Neil Armstrongclk: meson-gxbb: Add MALI clock IDS
2017-04-04 Jerome Brunetdt-bindings: clk: gxbb: expose i2s output clock gates
2017-04-04 Icenowy Zhengclk: sunxi-ng: add support for PRCM CCUs
2017-04-04 Icenowy Zhengdt-bindings: update device tree binding for Allwinner...
2017-04-04 Jon Hunterclk: tegra: Don't reset PLL-CX if it is already enabled
2017-04-04 Peter De Schrijverclk: tegra: Add missing Tegra210 clocks
2017-04-04 Alex Fridclk: tegra: Propagate clk_out_x rate to parent
2017-04-04 Gabriel Fernandezclk: stm32f4: fix: exclude values 0 and 1 for PLLQ
2017-03-30 Geert Uytterhoevenclk: renesas: rcar-gen3-cpg: Add support for RCLK on...
2017-03-30 Geert Uytterhoevenclk: renesas: r8a7795: Add support for R-Car H3 ES2.0
2017-03-30 Geert Uytterhoevenclk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions
2017-03-30 Geert Uytterhoevenclk: renesas: cpg-mssr: Add support for fixing up clock...
2017-03-27 Jerome Brunetclk: meson: mpll: correct N2 maximum value
2017-03-27 Jerome Brunetclk: meson8b: add the mplls clocks 0, 1 and 2
2017-03-27 Jerome Brunetclk: meson: gxbb: mpll: use rw operation
2017-03-27 Jerome Brunetclk: meson: mpll: add rw operation
2017-03-27 Jerome Brunetclk: gxbb: put dividers and muxes in tables
2017-03-27 Jerome Brunetclk: meson8b: put dividers and muxes in tables
2017-03-27 Jerome Brunetclk: meson: add missing const qualifiers on gate arrays
2017-03-27 Jerome Brunetclk: meson: fix SET_PARM macro
2017-03-23 Stephen BoydMerge tag 'sunxi-clk-fixes-for-4.11' of https://git...
2017-03-22 Elaine Zhangclk: rockchip: add pll_wait_lock for pll_enable
2017-03-22 Andy Yanclk: rockchip: rename RK1108 to RV1108
2017-03-22 Andy Yandt-bindings: rk1108-cru: rename RK1108 to RV1108
2017-03-21 Geert Uytterhoevenclk: renesas: rcar-gen3: Add workaround for PLL0/2...
2017-03-21 Geert Uytterhoevenclk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen...
2017-03-21 Geert Uytterhoevenclk: renesas: r8a7796: Reformat core clock table
2017-03-21 Geert Uytterhoevenclk: renesas: r8a7795: Reformat core clock table
2017-03-21 Geert Uytterhoevenclk: renesas: r8a7796: Correct name of watchdog clock
2017-03-21 Geert Uytterhoevenclk: renesas: r8a7795: Correct name of watchdog clock
2017-03-21 Geert Uytterhoevenclk: renesas: r8a7795: Correct parent clock and sort...
2017-03-20 Thierry Redingclk: tegra: Fix build warnings on Tegra20/Tegra30
2017-03-20 Peter De Schrijverclk: tegra: Mark TEGRA210_CLK_DBGAPB as always on
2017-03-20 Peter De Schrijverclk: tegra: Add SATA seq input control
2017-03-20 Peter De Schrijverclk: tegra: Add Tegra210 special resets
2017-03-20 Peter De Schrijverclk: tegra: Rework pll_u
2017-03-20 Mikko Perttunenclk: tegra: Implement reset control reset
2017-03-20 Peter De Schrijverclk: tegra: Fix disable unused for clocks sharing enabl...
2017-03-20 Peter De Schrijverclk: tegra: Handle UTMIPLL IDDQ
2017-03-20 Peter De Schrijverclk: tegra: Add aclk
2017-03-20 Peter De Schrijverclk: tegra: Add super clock mux/divider
2017-03-20 Peter De Schrijverclk: tegra: Define Tegra210 DMIC clocks
2017-03-20 Peter De Schrijverclk: tegra: Fix constness for peripheral clocks
2017-03-20 Peter De Schrijverclk: tegra: Define Tegra210 DMIC sync clocks
2017-03-20 Peter De Schrijverclk: tegra: Add CEC clock
2017-03-20 Peter De Schrijverclk: tegra: Fix type for m field
2017-03-20 Peter De Schrijverclk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate...
2017-03-20 Peter De Schrijverclk: tegra: Don't warn for PLL defaults unnecessarily
2017-03-20 Peter De Schrijverclk: tegra: Remove non-existing pll_m_out1 clock
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