From fbdc6d11ae0594fb03f4c5556cbb8ff46e1971e3 Mon Sep 17 00:00:00 2001 From: Philippe Langlais Date: Thu, 27 Jan 2011 14:37:07 +0100 Subject: [PATCH] mach-ux500: set sd/mmc clock rate to 100MHz The clock speed for the SD/MMC clock was incorrect, rectify it. Signed-off-by: Philippe Langlais Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index b2b0a3b9be8f..9a0a6ed9cd5d 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -313,7 +313,7 @@ static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000); static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK); static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */ static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000); -static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 50000000); +static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 100000000); static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK); static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK); static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK); -- 2.20.1