From faea8b0e33c2e6a276d34a755258bb2176553616 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 22 May 2017 14:25:47 +0800 Subject: [PATCH] clk: sunxi-ng: a83t: Fix PLL lock status register offset The offset for the PLL lock status register was incorrectly set to 0x208, which actually points to an unused register. The correct register offset is 0x20c. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c index 4a201a7e03b8..a9c5cc87d9d0 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c @@ -28,7 +28,7 @@ #include "ccu-sun8i-a83t.h" -#define CCU_SUN8I_A83T_LOCK_REG 0x208 +#define CCU_SUN8I_A83T_LOCK_REG 0x20c /* * The CPU PLLs are actually NP clocks, with P being /1 or /4. However -- 2.20.1