From f5d69cfa7f84c743cf67d095abefeab149620d5d Mon Sep 17 00:00:00 2001 From: Kyungwoo Kang Date: Fri, 7 Apr 2017 17:45:55 +0900 Subject: [PATCH] [COMMON] spi: s3c64xx: Fix div factor for USI v2. This patch fixes SPI div factor from 2 to 4 due to HW change on USIv2 USIv2 has fixed 4 time divider so that SW needs to change requiring 4 time bigger source clock Change-Id: I6387556ad7f493d5d0e4a699979fb868704fddd8 Signed-off-by: Kyungwoo Kang --- drivers/spi/spi-s3c64xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 6ce061d84fe9..dbadaa8a9c35 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -790,8 +790,8 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) writel(val, regs + S3C64XX_SPI_MODE_CFG); if (sdd->port_conf->clk_from_cmu) { - /* There is half-multiplier before the SPI */ - clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); + /* There is a quarter-multiplier before the SPI */ + clk_set_rate(sdd->src_clk, sdd->cur_speed * 4); } else { /* Configure Clock */ val = readl(regs + S3C64XX_SPI_CLK_CFG); -- 2.20.1