From ef4d63e6f51d9669e247c47b670a83511b98eb68 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 14 Oct 2010 16:51:36 +0200 Subject: [PATCH] AT91: trivial: align comment of at91sam9g20_reset with one more tab Preparing next patch with longer names Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/at91sam9g20_reset.S | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-at91/at91sam9g20_reset.S b/arch/arm/mach-at91/at91sam9g20_reset.S index f6e9b037f73..1631c38bc6b 100644 --- a/arch/arm/mach-at91/at91sam9g20_reset.S +++ b/arch/arm/mach-at91/at91sam9g20_reset.S @@ -33,23 +33,23 @@ .globl at91sam9g20_reset at91sam9g20_reset: mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ flush I-cache + mcr p15, 0, r0, c7, c5, 0 @ flush I-cache mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #CP15_CR_I - mcr p15, 0, r0, c1, c0, 0 @ enable I-cache + mcr p15, 0, r0, c1, c0, 0 @ enable I-cache - ldr r0, =SDRAMC_BASE @ preload constants + ldr r0, =SDRAMC_BASE @ preload constants ldr r1, =RSTC_BASE mov r2, #1 mov r3, #SDRAMC_LPCB_POWER_DOWN ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST - .balign 32 @ align to cache line + .balign 32 @ align to cache line - str r2, [r0, #SDRAMC_TR] @ disable SDRAM access - str r3, [r0, #SDRAMC_LPR] @ power down SDRAM - str r4, [r1, #RSTC_CR] @ reset processor + str r2, [r0, #SDRAMC_TR] @ disable SDRAM access + str r3, [r0, #SDRAMC_LPR] @ power down SDRAM + str r4, [r1, #RSTC_CR] @ reset processor b . -- 2.20.1