From e5bf1991ea62b4f4fc906d0828f7eed988fc3835 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Mon, 26 Oct 2015 18:23:22 -0700 Subject: [PATCH] clk: qcom: msm8960: Fix dsi1/2 halt bits The halt bits for these clocks seem wrong. I get the following warning while booting on an msm8960-cdp: WARNING: CPU: 0 PID: 1 at drivers/clk/qcom/clk-branch.c:97 clk_branch_toggle+0xd0/0x138() dsi1_clk status stuck at 'on' Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.3.0-rc3-00113-g5532cfb567fe #110 Hardware name: Qualcomm (Flattened Device Tree) [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0x70/0xbc) [] (dump_stack) from [] (warn_slowpath_common+0x78/0xb4) [] (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40) [] (warn_slowpath_fmt) from [] (clk_branch_toggle+0xd0/0x138) [] (clk_branch_toggle) from [] (clk_disable_unused_subtree+0x98/0x1b0) [] (clk_disable_unused_subtree) from [] (clk_disable_unused_subtree+0x20/0x1b0) [] (clk_disable_unused_subtree) from [] (clk_disable_unused+0x58/0xd8) [] (clk_disable_unused) from [] (do_one_initcall+0xac/0x1ec) [] (do_one_initcall) from [] (kernel_init_freeable+0x11c/0x1e8) [] (kernel_init_freeable) from [] (kernel_init+0x8/0xec) [] (kernel_init) from [] (ret_from_fork+0x14/0x3c) Fix the status bits and the errors go away. Fixes: 5532cfb567fe ("clk: qcom: mmcc-8960: Add DSI related clocks") Acked-by: Archit Taneja Signed-off-by: Stephen Boyd --- drivers/clk/qcom/mmcc-msm8960.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c index 397f5df6422a..00e36192a1de 100644 --- a/drivers/clk/qcom/mmcc-msm8960.c +++ b/drivers/clk/qcom/mmcc-msm8960.c @@ -2104,7 +2104,7 @@ static struct clk_rcg dsi1_src = { static struct clk_branch dsi1_clk = { .halt_reg = 0x01d0, - .halt_bit = 1, + .halt_bit = 2, .clkr = { .enable_reg = 0x004c, .enable_mask = BIT(0), @@ -2152,7 +2152,7 @@ static struct clk_rcg dsi2_src = { static struct clk_branch dsi2_clk = { .halt_reg = 0x01d0, - .halt_bit = 2, + .halt_bit = 20, .clkr = { .enable_reg = 0x003c, .enable_mask = BIT(0), -- 2.20.1