From e194401cf4d49e7fe2f8ec994130d59e94f09137 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 22 Mar 2017 11:32:24 +0100 Subject: [PATCH] clk: meson-gxbb: Add GP0 PLL init parameters Tha Amlogic GXBB SoC GP0 PLL needs some vendor provided parameters to be initializated in the the GP0 control registers before configuring the rate with the rate table provided parameters. GXBB GP0 PLL tweaks are also selected to respect the vendor init procedure. Signed-off-by: Neil Armstrong Signed-off-by: Michael Turquette Link: lkml.kernel.org/r/1490178747-14837-3-git-send-email-narmstrong@baylibre.com --- drivers/clk/meson/gxbb.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index d07dc2255faf..db95038e50c6 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -352,6 +352,13 @@ static struct meson_clk_pll gxbb_sys_pll = { }, }; +struct pll_params_table gxbb_gp0_params_table[] = { + PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228), + PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000), + PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4), + PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d), +}; + static struct meson_clk_pll gxbb_gp0_pll = { .m = { .reg_off = HHI_GP0_PLL_CNTL, @@ -368,6 +375,12 @@ static struct meson_clk_pll gxbb_gp0_pll = { .shift = 16, .width = 2, }, + .params = { + .params_table = gxbb_gp0_params_table, + .params_count = ARRAY_SIZE(gxbb_gp0_params_table), + .no_init_reset = true, + .clear_reset_for_lock = true, + }, .rate_table = gp0_pll_rate_table, .rate_count = ARRAY_SIZE(gp0_pll_rate_table), .lock = &clk_lock, -- 2.20.1