From e0d155cadbc569319e49b97ebb8b062e241483e6 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 11 Jul 2014 17:28:45 +0200 Subject: [PATCH] drm/imx: ipuv3-crtc: Allow to divide DI clock from TVEv2 This patch allows the IPU to divide the 27 MHz input clock from the TVE by two to obtain the 13.5 MHz pixel clock needed for NTSC/PAL SD modes. Signed-off-by: Philipp Zabel --- drivers/gpu/drm/imx/ipuv3-crtc.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c index 09d6f98f4cbd..4a393f609220 100644 --- a/drivers/gpu/drm/imx/ipuv3-crtc.c +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c @@ -161,13 +161,15 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, __func__, encoder_types); /* - * If we have DAC, TVDAC or LDB, then we need the IPU DI clock - * to be the same as the LDB DI clock. + * If we have DAC or LDB, then we need the IPU DI clock to be + * the same as the LDB DI clock. For TVDAC, derive the IPU DI + * clock from 27 MHz TVE_DI clock, but allow to divide it. */ if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) | - BIT(DRM_MODE_ENCODER_TVDAC) | BIT(DRM_MODE_ENCODER_LVDS))) sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT; + else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC)) + sig_cfg.clkflags = IPU_DI_CLKMODE_EXT; else sig_cfg.clkflags = 0; -- 2.20.1