From e04c735029bc133466b89265a0745a226d0eac23 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 2 May 2012 20:43:56 +0100 Subject: [PATCH] drm/i915: Wait for the clocks to stabilise before updating PLLs When initialising the PLL registers we may have to clear existing state from the BIOS - that is the PLL may already be enabled. So we need to disable it, wait for the clocks to settle and then rewrite it. The issue came to light when Ben tested commit 88ca4bb7974277793e602d88739d4e8f56b89e64 Author: Jesse Barnes Date: Fri Apr 20 17:11:53 2012 +0100 drm/i915: manage PCH PLLs separately from pipes and found that booting into a VGA monitor was no longer working. Closer inspection suggests that it was a pre-existing bug now being hit by the rearranged code. Perhaps Ben was not even the first person to stumble upon this bug, https://bugs.freedesktop.org/show_bug.cgi?id=37029. Signed-off-by: Chris Wilson Reported-and-Tested-by: Ben Widawsky Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 059e4684efd1..6ab195c0097f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2708,11 +2708,14 @@ found: DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); prepare: /* separate function? */ DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); - I915_WRITE(pll->fp0_reg, fp); - I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); + /* Wait for the clocks to stabilize before rewriting the regs */ + I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); POSTING_READ(pll->pll_reg); udelay(150); + + I915_WRITE(pll->fp0_reg, fp); + I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); pll->on = false; return pll; } -- 2.20.1