From df1bdc0667eb3132fe60b3562347ca9133694ee0 Mon Sep 17 00:00:00 2001 From: Nick Piggin Date: Sat, 13 Oct 2007 03:06:00 +0200 Subject: [PATCH] x86: fence oostores on 64-bit movnt* instructions are not strongly ordered with respect to other stores, so if we are to assume stores are strongly ordered in the rest of the 64 bit code, we must fence these off (see similar examples in 32 bit code). [ The AMD memory ordering document seems to say that nontemporal stores can also pass earlier regular stores, so maybe we need sfences _before_ movnt* everywhere too? ] Signed-off-by: Nick Piggin Signed-off-by: Linus Torvalds --- arch/x86/lib/copy_user_nocache_64.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/lib/copy_user_nocache_64.S b/arch/x86/lib/copy_user_nocache_64.S index 4620efb12f13..5196762b3b0e 100644 --- a/arch/x86/lib/copy_user_nocache_64.S +++ b/arch/x86/lib/copy_user_nocache_64.S @@ -117,6 +117,7 @@ ENTRY(__copy_user_nocache) popq %rbx CFI_ADJUST_CFA_OFFSET -8 CFI_RESTORE rbx + sfence ret CFI_RESTORE_STATE -- 2.20.1