From deecb365445de6d136f27aab60709092d240ece0 Mon Sep 17 00:00:00 2001 From: Jaehyoung Choi Date: Fri, 12 Jan 2018 15:56:31 +0900 Subject: [PATCH] [COMMON] watchdog: s3c2410_wdt: Add debug log in watchdog function Change-Id: I74452d58a2e98efd395ba4efa1c950a1beeac656 Signed-off-by: Jaehyoung Choi --- drivers/watchdog/s3c2410_wdt.c | 86 +++++++++++++++++++++++++++++++--- 1 file changed, 80 insertions(+), 6 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index a840ff7a1338..9fdc5da2ccc1 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -139,6 +139,8 @@ struct s3c2410_wdt { struct regmap *pmureg; unsigned int cluster; int use_multistage_wdt; + unsigned int disable_reg_val; + unsigned int mask_reset_reg_val; }; static struct s3c2410_wdt *s3c_wdt[MAX_WATCHDOG_CLUSTER_CNT]; @@ -244,7 +246,7 @@ static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask) { int ret; u32 mask_val = 1 << wdt->drv_data->mask_bit; - u32 val = 0; + u32 val = 0, mask_reset_reg_val = 0, disable_reg_val = 0; /* No need to do anything if no PMU CONFIG needed */ if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG)) @@ -257,8 +259,30 @@ static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask) wdt->drv_data->mask_reset_reg, mask_val, val); - if (ret < 0) + if (ret < 0) { dev_err(wdt->dev, "failed to update reg(%d)\n", ret); + return ret; + } + + ret = regmap_read(wdt->pmureg, wdt->drv_data->mask_reset_reg, &mask_reset_reg_val); + if (ret < 0) { + dev_err(wdt->dev, "Couldn't get MASK_WDT_RESET register, ret = (%d)\n", ret); + return ret; + } + + ret = regmap_read(wdt->pmureg, wdt->drv_data->disable_reg, &disable_reg_val); + if (ret < 0) { + dev_err(wdt->dev, "Couldn't get DISABLE_WDT register, ret = (%d)\n", ret); + return ret; + } + + dev_info(wdt->dev, "DISABLE_WDT reg val: %x, MASK_WDT_RESET reg val: %x\n", + disable_reg_val, mask_reset_reg_val); + + wdt->disable_reg_val = disable_reg_val; + wdt->mask_reset_reg_val = mask_reset_reg_val; + + dev_info(wdt->dev, "Mask_wdt_reset set %s done, mask = %d\n", mask ? "true" : "false", mask); return ret; } @@ -267,7 +291,7 @@ static int s3c2410wdt_automatic_disable_wdt(struct s3c2410_wdt *wdt, bool mask) { int ret; u32 mask_val = 1 << wdt->drv_data->mask_bit; - u32 val = 0; + u32 val = 0, mask_reset_reg_val = 0, disable_reg_val = 0; /* No need to do anything if no PMU CONFIG needed */ if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG)) @@ -280,8 +304,30 @@ static int s3c2410wdt_automatic_disable_wdt(struct s3c2410_wdt *wdt, bool mask) wdt->drv_data->disable_reg, mask_val, val); - if (ret < 0) + if (ret < 0) { dev_err(wdt->dev, "failed to update reg(%d)\n", ret); + return ret; + } + + ret = regmap_read(wdt->pmureg, wdt->drv_data->mask_reset_reg, &mask_reset_reg_val); + if (ret < 0) { + dev_err(wdt->dev, "Couldn't get MASK_WDT_RESET register, ret = (%d)\n", ret); + return ret; + } + + ret = regmap_read(wdt->pmureg, wdt->drv_data->disable_reg, &disable_reg_val); + if (ret < 0) { + dev_err(wdt->dev, "Couldn't get DISABLE_WDT register, ret = (%d)\n", ret); + return ret; + } + + dev_info(wdt->dev, "DISABLE_WDT reg val: %x, MASK_WDT_RESET reg val: %x\n", + disable_reg_val, mask_reset_reg_val); + + wdt->disable_reg_val = disable_reg_val; + wdt->mask_reset_reg_val = mask_reset_reg_val; + + dev_info(wdt->dev, "Automatic_wdt set %s done, mask = %d\n", mask ? "true" : "false", mask); return ret; } @@ -289,7 +335,7 @@ static int s3c2410wdt_automatic_disable_wdt(struct s3c2410_wdt *wdt, bool mask) static int s3c2410wdt_keepalive(struct watchdog_device *wdd) { struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); - unsigned long flags; + unsigned long flags, wtcnt = 0; s3c2410wdt_multistage_wdt_keepalive(); @@ -297,6 +343,9 @@ static int s3c2410wdt_keepalive(struct watchdog_device *wdd) writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); spin_unlock_irqrestore(&wdt->lock, flags); + wtcnt = readl(wdt->reg_base + S3C2410_WTCNT); + dev_info(wdt->dev, "Watchdog cluster %u keepalive!, wtcnt = %lx\n", wdt->cluster, wtcnt); + return 0; } @@ -304,11 +353,15 @@ static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) { unsigned long wtcon; + /* If Cluster 0 Watchdog is disabled, Multistage watchdog is also disabled */ s3c2410wdt_multistage_wdt_stop(); wtcon = readl(wdt->reg_base + S3C2410_WTCON); wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); writel(wtcon, wdt->reg_base + S3C2410_WTCON); + + wtcon = readl(wdt->reg_base + S3C2410_WTCON); + dev_info(wdt->dev, "Watchdog cluster %u stop done, WTCON = %lx\n", wdt->cluster, wtcon); } static int s3c2410wdt_stop(struct watchdog_device *wdd) @@ -365,6 +418,8 @@ static int s3c2410wdt_start(struct watchdog_device *wdd) spin_unlock_irqrestore(&wdt->lock, flags); + wtcon = readl(wdt->reg_base + S3C2410_WTCON); + dev_info(wdt->dev, "Watchdog cluster %u start, WTCON = %lx\n", wdt->cluster, wtcon); return 0; } @@ -992,7 +1047,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev) struct s3c2410_wdt *wdt; struct resource *wdt_mem; struct resource *wdt_irq; - unsigned int wtcon; + unsigned int wtcon, disable_reg_val, mask_reset_reg_val; int started = 0; int ret, cluster_index; @@ -1038,6 +1093,25 @@ static int s3c2410wdt_probe(struct platform_device *pdev) } } + ret = regmap_read(wdt->pmureg, wdt->drv_data->mask_reset_reg, &mask_reset_reg_val); + if (ret) { + dev_err(wdt->dev, "Couldn't get MASK_WDT_RESET register\n"); + return PTR_ERR(wdt->pmureg); + } + + ret = regmap_read(wdt->pmureg, wdt->drv_data->disable_reg, &disable_reg_val); + if (ret) { + dev_err(wdt->dev, "Couldn't get DISABLE_WDT register\n"); + return PTR_ERR(wdt->pmureg); + } + + /* Watchdog bits in both registers must be masked */ + dev_info(wdt->dev, "DISABLE_WDT reg val: %x, MASK_WDT_RESET reg val: %x\n", + disable_reg_val, mask_reset_reg_val); + + wdt->disable_reg_val = disable_reg_val; + wdt->mask_reset_reg_val = mask_reset_reg_val; + wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (wdt_irq == NULL) { dev_err(dev, "no irq resource specified\n"); -- 2.20.1