From ccb8b12c4b72a5034a1e04efb68fe9a4682c1de0 Mon Sep 17 00:00:00 2001 From: =?utf8?q?St=C3=A9phane=20Marchesin?= Date: Thu, 22 May 2014 20:32:46 -0700 Subject: [PATCH] drm/tegra: sor - Remove pixel clock rounding MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The code currently rounds up the clock to the next MHZ, which is rounding up a 69.5MHz clock to 70MHz on my machine. This in turn prevents the display from syncing. Removing this rounding fixes eDP for me. Signed-off-by: Stéphane Marchesin Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 93ae4fac8ac2..e22325f12c12 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -876,9 +876,6 @@ static int tegra_output_sor_setup_clock(struct tegra_output *output, struct tegra_sor *sor = to_sor(output); int err; - /* round to next MHz */ - pclk = DIV_ROUND_UP(pclk, 1000000) * 1000000; - err = clk_set_parent(clk, sor->clk_parent); if (err < 0) { dev_err(sor->dev, "failed to set parent clock: %d\n", err); -- 2.20.1